avr: Separate out gpio pwm pin definitions from pwm register definitions

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

1 files changed, 44 insertions, 41 deletions

diff --git a/src/avr/gpio.c b/src/avr/gpio.c
index af127ba1..4ec1e316 100644
--- a/src/avr/gpio.c
+++ b/src/avr/gpio.c
@@ -47,54 +47,57 @@ struct gpio_digital_regs {
 struct gpio_pwm_info {
     volatile void *ocr;
     volatile uint8_t *rega, *regb;
-    uint8_t en_bit, pin, flags;
+    uint8_t en_bit, flags;
 };
 
 enum { GP_8BIT=1, GP_AFMT=2 };
 
 static const struct gpio_pwm_info pwm_regs[] PROGMEM = {
+    { &OCR0A, &TCCR0A, &TCCR0B, 1<<COM0A1, GP_8BIT },
+    { &OCR0B, &TCCR0A, &TCCR0B, 1<<COM0B1, GP_8BIT },
+    { &OCR1A, &TCCR1A, &TCCR1B, 1<<COM1A1, 0 },
+    { &OCR1B, &TCCR1A, &TCCR1B, 1<<COM1B1, 0 },
+#ifdef OCR1C
+    { &OCR1C, &TCCR1A, &TCCR1B, 1<<COM1C1, 0 },
+#endif
+    { &OCR2A, &TCCR2A, &TCCR2B, 1<<COM2A1, GP_8BIT|GP_AFMT },
+    { &OCR2B, &TCCR2A, &TCCR2B, 1<<COM2B1, GP_8BIT|GP_AFMT },
+#ifdef OCR3A
+    { &OCR3A, &TCCR3A, &TCCR3B, 1<<COM3A1, 0 },
+    { &OCR3B, &TCCR3A, &TCCR3B, 1<<COM3B1, 0 },
+    { &OCR3C, &TCCR3A, &TCCR3B, 1<<COM3C1, 0 },
+#endif
+#ifdef OCR4A
+    { &OCR4A, &TCCR4A, &TCCR4B, 1<<COM4A1, 0 },
+    { &OCR4B, &TCCR4A, &TCCR4B, 1<<COM4B1, 0 },
+    { &OCR4C, &TCCR4A, &TCCR4B, 1<<COM4C1, 0 },
+    { &OCR5A, &TCCR5A, &TCCR5B, 1<<COM5A1, 0 },
+    { &OCR5B, &TCCR5A, &TCCR5B, 1<<COM5B1, 0 },
+    { &OCR5C, &TCCR5A, &TCCR5B, 1<<COM5C1, 0 },
+#endif
+};
+
+static const uint8_t pwm_pins[ARRAY_SIZE(pwm_regs)] PROGMEM = {
 #if CONFIG_MACH_atmega168
-    { &OCR0A, &TCCR0A, &TCCR0B, 1<<COM0A1, GPIO('D', 6), GP_8BIT         },
-    { &OCR0B, &TCCR0A, &TCCR0B, 1<<COM0B1, GPIO('D', 5), GP_8BIT         },
-    { &OCR1A, &TCCR1A, &TCCR1B, 1<<COM1A1, GPIO('B', 1), 0               },
-    { &OCR1B, &TCCR1A, &TCCR1B, 1<<COM1B1, GPIO('B', 2), 0               },
-    { &OCR2A, &TCCR2A, &TCCR2B, 1<<COM2A1, GPIO('B', 3), GP_8BIT|GP_AFMT },
-    { &OCR2B, &TCCR2A, &TCCR2B, 1<<COM2B1, GPIO('D', 3), GP_8BIT|GP_AFMT },
+    GPIO('D', 6), GPIO('D', 5),
+    GPIO('B', 1), GPIO('B', 2),
+    GPIO('B', 3), GPIO('D', 3),
 #elif CONFIG_MACH_atmega644p
-    { &OCR0A, &TCCR0A, &TCCR0B, 1<<COM0A1, GPIO('B', 3), GP_8BIT         },
-    { &OCR0B, &TCCR0A, &TCCR0B, 1<<COM0B1, GPIO('B', 4), GP_8BIT         },
-    { &OCR1A, &TCCR1A, &TCCR1B, 1<<COM1A1, GPIO('D', 5), 0               },
-    { &OCR1B, &TCCR1A, &TCCR1B, 1<<COM1B1, GPIO('D', 4), 0               },
-    { &OCR2A, &TCCR2A, &TCCR2B, 1<<COM2A1, GPIO('D', 7), GP_8BIT|GP_AFMT },
-    { &OCR2B, &TCCR2A, &TCCR2B, 1<<COM2B1, GPIO('D', 6), GP_8BIT|GP_AFMT },
+    GPIO('B', 3), GPIO('B', 4),
+    GPIO('D', 5), GPIO('D', 4),
+    GPIO('D', 7), GPIO('D', 6),
 #elif CONFIG_MACH_at90usb1286
-    { &OCR0A, &TCCR0A, &TCCR0B, 1<<COM0A1, GPIO('B', 7), GP_8BIT         },
-    { &OCR0B, &TCCR0A, &TCCR0B, 1<<COM0B1, GPIO('D', 0), GP_8BIT         },
-    { &OCR1A, &TCCR1A, &TCCR1B, 1<<COM1A1, GPIO('B', 5), 0               },
-    { &OCR1B, &TCCR1A, &TCCR1B, 1<<COM1B1, GPIO('B', 6), 0               },
-    { &OCR1C, &TCCR1A, &TCCR1B, 1<<COM1C1, GPIO('B', 7), 0               },
-    { &OCR2A, &TCCR2A, &TCCR2B, 1<<COM2A1, GPIO('B', 4), GP_8BIT|GP_AFMT },
-    { &OCR2B, &TCCR2A, &TCCR2B, 1<<COM2B1, GPIO('D', 1), GP_8BIT|GP_AFMT },
-    { &OCR3A, &TCCR3A, &TCCR3B, 1<<COM3A1, GPIO('C', 6), 0               },
-    { &OCR3B, &TCCR3A, &TCCR3B, 1<<COM3B1, GPIO('C', 5), 0               },
-    { &OCR3C, &TCCR3A, &TCCR3B, 1<<COM3C1, GPIO('C', 4), 0               },
+    GPIO('B', 7), GPIO('D', 0),
+    GPIO('B', 5), GPIO('B', 6), GPIO('B', 7),
+    GPIO('B', 4), GPIO('D', 1),
+    GPIO('C', 6), GPIO('C', 5), GPIO('C', 4),
 #elif CONFIG_MACH_atmega1280 || CONFIG_MACH_atmega2560
-    { &OCR0A, &TCCR0A, &TCCR0B, 1<<COM0A1, GPIO('B', 7), GP_8BIT         },
-    { &OCR0B, &TCCR0A, &TCCR0B, 1<<COM0B1, GPIO('G', 5), GP_8BIT         },
-    { &OCR1A, &TCCR1A, &TCCR1B, 1<<COM1A1, GPIO('B', 5), 0               },
-    { &OCR1B, &TCCR1A, &TCCR1B, 1<<COM1B1, GPIO('B', 6), 0               },
-    { &OCR1C, &TCCR1A, &TCCR1B, 1<<COM1C1, GPIO('B', 7), 0               },
-    { &OCR2A, &TCCR2A, &TCCR2B, 1<<COM2A1, GPIO('B', 4), GP_8BIT|GP_AFMT },
-    { &OCR2B, &TCCR2A, &TCCR2B, 1<<COM2B1, GPIO('H', 6), GP_8BIT|GP_AFMT },
-    { &OCR3A, &TCCR3A, &TCCR3B, 1<<COM3A1, GPIO('E', 3), 0               },
-    { &OCR3B, &TCCR3A, &TCCR3B, 1<<COM3B1, GPIO('E', 4), 0               },
-    { &OCR3C, &TCCR3A, &TCCR3B, 1<<COM3C1, GPIO('E', 5), 0               },
-    { &OCR4A, &TCCR4A, &TCCR4B, 1<<COM4A1, GPIO('H', 3), 0               },
-    { &OCR4B, &TCCR4A, &TCCR4B, 1<<COM4B1, GPIO('H', 4), 0               },
-    { &OCR4C, &TCCR4A, &TCCR4B, 1<<COM4C1, GPIO('H', 5), 0               },
-    { &OCR5A, &TCCR5A, &TCCR5B, 1<<COM5A1, GPIO('L', 3), 0               },
-    { &OCR5B, &TCCR5A, &TCCR5B, 1<<COM5B1, GPIO('L', 4), 0               },
-    { &OCR5C, &TCCR5A, &TCCR5B, 1<<COM5C1, GPIO('L', 5), 0               },
+    GPIO('B', 7), GPIO('G', 5),
+    GPIO('B', 5), GPIO('B', 6), GPIO('B', 7),
+    GPIO('B', 4), GPIO('H', 6),
+    GPIO('E', 3), GPIO('E', 4), GPIO('E', 5),
+    GPIO('H', 3), GPIO('H', 4), GPIO('H', 5),
+    GPIO('L', 3), GPIO('L', 4), GPIO('L', 5),
 #endif
 };
 
@@ -204,9 +207,9 @@ gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val)
 {
     uint8_t chan;
     for (chan=0; chan<ARRAY_SIZE(pwm_regs); chan++) {
-        const struct gpio_pwm_info *p = &pwm_regs[chan];
-        if (READP(p->pin) != pin)
+        if (READP(pwm_pins[chan]) != pin)
             continue;
+        const struct gpio_pwm_info *p = &pwm_regs[chan];
         uint8_t flags = READP(p->flags), cs;
         if (flags & GP_AFMT) {
             switch (cycle_time) {