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authorKevin O'Connor <kevin@koconnor.net>2025-04-22 02:48:15 -0400
committerKevin O'Connor <kevin@koconnor.net>2025-04-28 19:36:55 -0400
commit5d1f773ffb5d4a718ba544400958744bab88e1c6 (patch)
tree241ba3670263ccf17f09d991e17f3e8b450550ce /src
parentda8e0a6e509c22e7de326f93bff89e36f78b68c8 (diff)
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stm32h7: Always clear AHB1ENR at startup on stm32h7
Entirely clear the AHB1ENR register. There is no need to modify AHB1LPENR. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
-rw-r--r--src/stm32/stm32h7.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c
index d3e70c79..6d875819 100644
--- a/src/stm32/stm32h7.c
+++ b/src/stm32/stm32h7.c
@@ -86,11 +86,6 @@ DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
static void
clock_setup(void)
{
-#if !CONFIG_MACH_STM32H723
- // Ensure USB OTG ULPI is not enabled
- CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);
- CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN);
-#endif
// Set this despite correct defaults.
// "The software has to program the supply configuration in PWR control
// register 3" (pg. 259)
@@ -239,6 +234,7 @@ armcm_main(void)
RCC->APB2ENR = 0x00000000;
RCC->APB3ENR = 0x00000000;
RCC->APB4ENR = 0x00000000;
+ RCC->AHB1ENR = 0x00000000;
SCB->VTOR = (uint32_t)VectorTable;