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| author | Kevin O'Connor <kevin@koconnor.net> | 2025-04-18 21:23:21 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2025-04-19 12:09:58 -0400 |
| commit | 5001983d349ef1a1608e2c884888b9040f80ef89 (patch) | |
| tree | 00638538285ea73e41f52f76e2bbed72e87bb3ff /src | |
| parent | 73e27aee4f579fd3b34ad01ccd5318f18b2a6711 (diff) | |
| download | kutter-5001983d349ef1a1608e2c884888b9040f80ef89.tar.gz kutter-5001983d349ef1a1608e2c884888b9040f80ef89.tar.xz kutter-5001983d349ef1a1608e2c884888b9040f80ef89.zip | |
stm32: Fix pll_base on stm32h7 when using a clock other than 25Mhz
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/stm32/stm32h7.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index 387e47dd..d3e70c79 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -100,7 +100,7 @@ clock_setup(void) ; // (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz) // /DIVP1(2) (SYSCLK 480Mhz) - uint32_t pll_base = 5000000; + uint32_t pll_base = CONFIG_STM32_CLOCK_REF_25M ? 5000000 : 4000000; // Only even dividers (DIVP1) are allowed uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2; if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { |