diff options
| author | Kevin O'Connor <kevin@koconnor.net> | 2021-01-18 12:47:59 -0500 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2021-01-18 12:49:41 -0500 |
| commit | 28bca7da7741bafbbe8619da2c46892b38696191 (patch) | |
| tree | 9a30260538a2c25678c0a8dea7fd2585264382ba /src | |
| parent | 611b76369f9c36e8f68c58f1e96617d1a1e76b04 (diff) | |
| download | kutter-28bca7da7741bafbbe8619da2c46892b38696191.tar.gz kutter-28bca7da7741bafbbe8619da2c46892b38696191.tar.xz kutter-28bca7da7741bafbbe8619da2c46892b38696191.zip | |
stm32: Support setting the stm32f0 internal clock trim value
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/stm32/Kconfig | 9 | ||||
| -rw-r--r-- | src/stm32/stm32f0.c | 3 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/stm32/Kconfig b/src/stm32/Kconfig index 4b2cd7db..98e5aed8 100644 --- a/src/stm32/Kconfig +++ b/src/stm32/Kconfig @@ -187,6 +187,15 @@ choice bool "Pins PB12(rx) and PB13(tx)" if MACH_STM32F4 endchoice +config STM32F0_TRIM + int "Internal clock trim override" if LOW_LEVEL_OPTIONS && MACH_STM32F0 && STM32_CLOCK_REF_INTERNAL && !USBSERIAL + default 16 + help + Specify the internal clock trim value. Setting this can be + useful if the factory default internal clock is not accurate. + Default is 16 (use factory default). Each increment increases + the clock rate by ~240KHz. + config STM32F042_PIN_SWAP bool "Use PA9/PA10 for USB or CAN" if MACH_STM32F042 depends on (USBSERIAL || CANSERIAL) && MACH_STM32F042 diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index 3b4d35d4..0232b602 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -127,7 +127,8 @@ pll_setup(void) if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { // Configure 48Mhz PLL from external crystal (HSE) uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ; - RCC->CR |= RCC_CR_HSEON; + RCC->CR = ((RCC->CR & ~RCC_CR_HSITRIM) | RCC_CR_HSEON + | (CONFIG_STM32F0_TRIM << RCC_CR_HSITRIM_Pos)); cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((div - 2) << RCC_CFGR_PLLMUL_Pos); } else { // Configure 48Mhz PLL from internal 8Mhz oscillator (HSI) |