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authorKevin O'Connor <kevin@koconnor.net>2025-05-30 20:36:09 -0400
committerKevin O'Connor <kevin@koconnor.net>2025-05-30 20:36:09 -0400
commit1f3b4cc749be7b0ad1a4e60d4b9c3eb3c0a4167c (patch)
tree65bb356ff22578f5814019f1f08eb835bdcd959f /src
parent8e58f8fb39f275a23c6209cc856e3464b188fdf5 (diff)
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stm32: Fix spi overflow issue on stm32h7
Completely filling the spi transmit fifo could lead to a situation where the rx fifo overflows. Make sure not to write past the rx fifo size. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src')
-rw-r--r--src/stm32/stm32h7_spi.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/stm32/stm32h7_spi.c b/src/stm32/stm32h7_spi.c
index 0f49b5e9..d1e514e7 100644
--- a/src/stm32/stm32h7_spi.c
+++ b/src/stm32/stm32h7_spi.c
@@ -124,13 +124,13 @@ spi_prepare(struct spi_config config)
;
}
+#define MAX_FIFO 8 // Limit tx fifo usage so rx fifo doesn't overrun
+
void
spi_transfer(struct spi_config config, uint8_t receive_data,
uint8_t len, uint8_t *data)
{
- uint8_t rdata = 0;
- uint8_t* wptr = data;
- uint8_t* end = data + len;
+ uint8_t *wptr = data, *end = data + len;
SPI_TypeDef *spi = config.spi;
spi->CR2 = len << SPI_CR2_TSIZE_Pos;
@@ -140,15 +140,13 @@ spi_transfer(struct spi_config config, uint8_t receive_data,
while (data < end) {
uint32_t sr = spi->SR & (SPI_SR_TXP | SPI_SR_RXP);
- if ((sr == SPI_SR_TXP) && wptr < end)
+ if (sr == SPI_SR_TXP && wptr < end && wptr < data + MAX_FIFO)
writeb((void*)&spi->TXDR, *wptr++);
if (!(sr & SPI_SR_RXP))
continue;
- rdata = readb((void *)&spi->RXDR);
-
- if (receive_data) {
+ uint8_t rdata = readb((void *)&spi->RXDR);
+ if (receive_data)
*data = rdata;
- }
data++;
}