diff options
author | Grigori Goronzy <greg@chown.ath.cx> | 2018-07-02 23:17:28 +0200 |
---|---|---|
committer | KevinOConnor <kevin@koconnor.net> | 2018-07-07 11:05:33 -0400 |
commit | 5c7c8c984b582304d1f1c36de0f1d9bacbd8d42d (patch) | |
tree | 780781bf7d848453eabf4b8364addfb04478df88 /src/stm32f1/gpio.c | |
parent | b0ee323e2e01ba2084bea8de733f16474f1167eb (diff) | |
download | kutter-5c7c8c984b582304d1f1c36de0f1d9bacbd8d42d.tar.gz kutter-5c7c8c984b582304d1f1c36de0f1d9bacbd8d42d.tar.xz kutter-5c7c8c984b582304d1f1c36de0f1d9bacbd8d42d.zip |
stm32f1: add SPI support
Add basic SPI support and associated documentation.
v2: remove baud rate check, fix baud rate calculations
v3: finish transaction with BSY check, disable SPI when not in use
Signed-off-by: Grigori Goronzy <greg@chown.ath.cx>
Diffstat (limited to 'src/stm32f1/gpio.c')
-rw-r--r-- | src/stm32f1/gpio.c | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/src/stm32f1/gpio.c b/src/stm32f1/gpio.c index caadf277..ed507496 100644 --- a/src/stm32f1/gpio.c +++ b/src/stm32f1/gpio.c @@ -11,8 +11,10 @@ #include "compiler.h" // ARRAY_SIZE #include "gpio.h" // gpio_out_setup #include "stm32f1xx.h" +#include "stm32f1xx_ll_rcc.h" #include "stm32f1xx_ll_gpio.h" #include "stm32f1xx_ll_adc.h" +#include "stm32f1xx_ll_spi.h" #include "sched.h" // sched_shutdown #include "board/irq.h" #include "board/io.h" @@ -219,3 +221,102 @@ gpio_adc_cancel_sample(struct gpio_adc g) LL_ADC_ClearFlag_EOS(ADC1); } } + +/**************************************************************** + * Serial Peripheral Interface (SPI) pins + ****************************************************************/ + +void spi_set_mode(SPI_TypeDef *spi, uint8_t mode) +{ + switch (mode) { + case 0: + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW); + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE); + break; + case 1: + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW); + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE); + break; + case 2: + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH); + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE); + break; + case 3: + LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH); + LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE); + break; + default: + shutdown("Invalid SPI mode"); + } +} + +void spi_set_baudrate(SPI_TypeDef *spi, uint32_t rate) +{ + const uint32_t pclk = __LL_RCC_CALC_PCLK1_FREQ(SystemCoreClock, LL_RCC_GetAPB1Prescaler()); + const uint32_t prescaler = pclk / rate; + + uint32_t setting = LL_SPI_BAUDRATEPRESCALER_DIV256; + if (prescaler <= 2) + setting = LL_SPI_BAUDRATEPRESCALER_DIV2; + else if (prescaler <= 4) + setting = LL_SPI_BAUDRATEPRESCALER_DIV4; + else if (prescaler <= 8) + setting = LL_SPI_BAUDRATEPRESCALER_DIV8; + else if (prescaler <= 16) + setting = LL_SPI_BAUDRATEPRESCALER_DIV16; + else if (prescaler <= 32) + setting = LL_SPI_BAUDRATEPRESCALER_DIV32; + else if (prescaler <= 64) + setting = LL_SPI_BAUDRATEPRESCALER_DIV64; + else if (prescaler <= 128) + setting = LL_SPI_BAUDRATEPRESCALER_DIV128; + + LL_SPI_SetBaudRatePrescaler(spi, setting); +} + +void spi_init_pins(void) +{ + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_13, LL_GPIO_MODE_ALTERNATE); + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_14, LL_GPIO_MODE_INPUT); + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_15, LL_GPIO_MODE_ALTERNATE); + LL_GPIO_SetPinOutputType(GPIOB, LL_GPIO_PIN_13, LL_GPIO_OUTPUT_PUSHPULL); + LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_14, LL_GPIO_PULL_UP); + LL_GPIO_SetPinOutputType(GPIOB, LL_GPIO_PIN_15, LL_GPIO_OUTPUT_PUSHPULL); +} + +struct spi_config +spi_setup(uint32_t bus, uint8_t mode, uint32_t rate) +{ + struct spi_config config; + config.config = *SPI2; + + if (bus > 0 || !rate) + shutdown("Invalid spi_setup parameters"); + + spi_init_pins(); + spi_set_mode(&config.config, mode); + spi_set_baudrate(&config.config, rate); + + return config; +} + +void +spi_transfer(struct spi_config config, uint8_t receive_data, + uint8_t len, uint8_t *data) +{ + *SPI2 = config.config; + LL_SPI_Enable(SPI2); + + while (len--) { + LL_SPI_TransmitData8(SPI2, *data); + while (!LL_SPI_IsActiveFlag_TXE(SPI2)); + if (receive_data) { + while (!LL_SPI_IsActiveFlag_RXNE(SPI2)); + *data = LL_SPI_ReceiveData8(SPI2); + } + data++; + } + + while (LL_SPI_IsActiveFlag_BSY(SPI2)); + LL_SPI_Disable(SPI2); +} |