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| author | Kevin O'Connor <kevin@koconnor.net> | 2022-06-10 22:48:53 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2022-06-16 11:03:48 -0400 |
| commit | 913c6a913dceb11eeaf9fa62b0f3ba5cd88463e3 (patch) | |
| tree | 669eb4ee765ade9bed89f5f52c7a6d02b2bfc0d0 /src/stm32 | |
| parent | ce186c6af6e6b9f4656c0c09d1a92c27d5b1aa2d (diff) | |
| download | kutter-913c6a913dceb11eeaf9fa62b0f3ba5cd88463e3.tar.gz kutter-913c6a913dceb11eeaf9fa62b0f3ba5cd88463e3.tar.xz kutter-913c6a913dceb11eeaf9fa62b0f3ba5cd88463e3.zip | |
stm32: Support PA11/PA12 and PB8/PB9 on fdcan
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32')
| -rw-r--r-- | src/stm32/Kconfig | 4 | ||||
| -rwxr-xr-x | src/stm32/fdcan.c | 32 |
2 files changed, 20 insertions, 16 deletions
diff --git a/src/stm32/Kconfig b/src/stm32/Kconfig index bad86a8c..875d138e 100644 --- a/src/stm32/Kconfig +++ b/src/stm32/Kconfig @@ -322,7 +322,7 @@ choice select SERIAL config STM32_CANBUS_PA11_PA12 bool "CAN bus (on PA11/PA12)" - depends on HAVE_STM32_CANBUS + depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS select CANSERIAL config STM32_CANBUS_PA11_PA12_REMAP bool "CAN bus (on PA9/PA10)" if LOW_LEVEL_OPTIONS @@ -330,7 +330,7 @@ choice select CANSERIAL config STM32_CANBUS_PB8_PB9 bool "CAN bus (on PB8/PB9)" if LOW_LEVEL_OPTIONS - depends on HAVE_STM32_CANBUS + depends on HAVE_STM32_CANBUS || HAVE_STM32_FDCANBUS select CANSERIAL config STM32_CANBUS_PI9_PH13 bool "CAN bus (on PI9/PH13)" if LOW_LEVEL_OPTIONS diff --git a/src/stm32/fdcan.c b/src/stm32/fdcan.c index 6a1dfe93..afd59b5d 100755 --- a/src/stm32/fdcan.c +++ b/src/stm32/fdcan.c @@ -61,24 +61,31 @@ FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE); #define FDCAN_IE_TC (FDCAN_IE_TCE | FDCAN_IE_TCFE | FDCAN_IE_TFEE) -#if CONFIG_STM32_CANBUS_PB0_PB1 +#if CONFIG_STM32_CANBUS_PA11_PA12 + DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PA11,PA12"); + #define GPIO_Rx GPIO('A', 11) + #define GPIO_Tx GPIO('A', 12) +#elif CONFIG_STM32_CANBUS_PB8_PB9 + DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB8,PB9"); + #define GPIO_Rx GPIO('B', 8) + #define GPIO_Tx GPIO('B', 9) +#elif CONFIG_STM32_CANBUS_PB0_PB1 DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB0,PB1"); #define GPIO_Rx GPIO('B', 0) #define GPIO_Tx GPIO('B', 1) #endif -#if CONFIG_MACH_STM32G0 - #if CONFIG_STM32_CANBUS_PB0_PB1 - #define SOC_CAN FDCAN2 - #define MSG_RAM fdcan_ram->fdcan2 - #else - #error Uknown pins for STMF32G0 CAN - #endif - - #define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn - #define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number +#if !CONFIG_STM32_CANBUS_PB0_PB1 + #define SOC_CAN FDCAN1 + #define MSG_RAM fdcan_ram->fdcan1 +#else + #define SOC_CAN FDCAN2 + #define MSG_RAM fdcan_ram->fdcan2 #endif +#define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn +#define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number + #ifndef SOC_CAN #error No known CAN device for configured MCU #endif @@ -240,9 +247,6 @@ can_init(void) /* Enable configuration change */ SOC_CAN->CCCR |= FDCAN_CCCR_CCE; - if (SOC_CAN == FDCAN1) - FDCAN_CONFIG->CKDIV = 0; - /* Disable protocol exception handling */ SOC_CAN->CCCR |= FDCAN_CCCR_PXHD; |