stm32f7: add support for stm32f7 and remram board

Signed-off-by: Frederic Morin <frederic.morin.8@gmail.com>

10 files changed, 217 insertions, 11 deletions

diff --git a/src/stm32/Kconfig b/src/stm32/Kconfig
index 5d82f9c3..1561aa6b 100644
--- a/src/stm32/Kconfig
+++ b/src/stm32/Kconfig
@@ -10,7 +10,7 @@ config STM32_SELECT
     select HAVE_GPIO_I2C if !(MACH_STM32F031)
     select HAVE_GPIO_SPI if !MACH_STM32F031
     select HAVE_GPIO_SDIO if MACH_STM32F4
-    select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32G0 || MACH_STM32H7
+    select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32H7
     select HAVE_GPIO_BITBANGING if !MACH_STM32F031
     select HAVE_STRICT_TIMING
     select HAVE_CHIPID
@@ -52,6 +52,9 @@ choice
     config MACH_STM32F446
         bool "STM32F446"
         select MACH_STM32F4
+    config MACH_STM32F765
+        bool "STM32F765"
+        select MACH_STM32F7
     config MACH_STM32F031
         bool "STM32F031"
         select MACH_STM32F0
@@ -119,6 +122,8 @@ config MACH_STM32F2
     bool
 config MACH_STM32F4
     bool
+config MACH_STM32F7
+    bool
 config MACH_STM32G0
     bool
 config MACH_STM32G07x
@@ -143,7 +148,7 @@ config HAVE_STM32_USBFS
     default y if (MACH_STM32F1 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL
 config HAVE_STM32_USBOTG
     bool
-    default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7
+    default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32H7
 config HAVE_STM32_CANBUS
     bool
     default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
@@ -170,6 +175,7 @@ config MCU
     default "stm32f407xx" if MACH_STM32F407
     default "stm32f429xx" if MACH_STM32F429
     default "stm32f446xx" if MACH_STM32F446
+    default "stm32f765xx" if MACH_STM32F765
     default "stm32g070xx" if MACH_STM32G070
     default "stm32g071xx" if MACH_STM32G071
     default "stm32g0b0xx" if MACH_STM32G0B0
@@ -190,6 +196,7 @@ config CLOCK_FREQ
     default 84000000 if MACH_STM32F401
     default 168000000 if MACH_STM32F4x5
     default 180000000 if MACH_STM32F446
+    default 216000000 if MACH_STM32F765
     default 64000000 if MACH_STM32G0
     default 150000000 if MACH_STM32G431
     default 400000000 if MACH_STM32H7 # 400Mhz is max Klipper currently supports
@@ -207,7 +214,7 @@ config FLASH_SIZE
     default 0x80000 if MACH_STM32F4x5 || MACH_STM32F446
     default 0x20000 if MACH_STM32G0 || MACH_STM32G431
     default 0x20000 if MACH_STM32H750
-    default 0x200000 if MACH_STM32H743
+    default 0x200000 if MACH_STM32H743 || MACH_STM32F765
     default 0x20000 if MACH_N32G45x
 
 config FLASH_BOOT_ADDRESS
@@ -230,6 +237,7 @@ config RAM_SIZE
     default 0x20000 if MACH_STM32F207
     default 0x10000 if MACH_STM32F401
     default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446
+    default 0x80000 if MACH_STM32F765
     default 0x9000 if MACH_STM32G07x
     default 0x24000 if MACH_STM32G0Bx
     default 0x20000 if MACH_STM32H7
@@ -254,7 +262,7 @@ config STM32_DFU_ROM_ADDRESS
     default 0 if !USB
     default 0x1fffc400 if MACH_STM32F042
     default 0x1fffc800 if MACH_STM32F072
-    default 0x1fff0000 if MACH_STM32F4 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
+    default 0x1fff0000 if MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
     default 0x1ff09800 if MACH_STM32H7
     default 0
 
@@ -272,7 +280,7 @@ choice
     config STM32_FLASH_START_7000
         bool "28KiB bootloader" if MACH_STM32F1
     config STM32_FLASH_START_8000
-        bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4
+        bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7
     config STM32_FLASH_START_8800
         bool "34KiB bootloader (Chitu v6 Bootloader)" if MACH_STM32F103
     config STM32_FLASH_START_20200
@@ -289,7 +297,7 @@ choice
     config STM32_FLASH_START_4000
         bool "16KiB bootloader (HID Bootloader)" if MACH_STM32F207 || MACH_STM32F401 || MACH_STM32F4x5 || MACH_STM32F103 || MACH_STM32F072
     config STM32_FLASH_START_20000
-        bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723
+        bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723 || MACH_STM32F7
 
     config STM32_FLASH_START_0000
         bool "No bootloader"
@@ -330,6 +338,8 @@ choice
         bool "16 MHz crystal"
     config STM32_CLOCK_REF_20M
         bool "20 MHz crystal"
+    config STM32_CLOCK_REF_24M
+        bool "24 MHz crystal"
     config STM32_CLOCK_REF_25M
         bool "25 MHz crystal"
     config STM32_CLOCK_REF_INTERNAL
@@ -338,6 +348,7 @@ endchoice
 config CLOCK_REF_FREQ
     int
     default 25000000 if STM32_CLOCK_REF_25M
+    default 24000000 if STM32_CLOCK_REF_24M
     default 20000000 if STM32_CLOCK_REF_20M
     default 16000000 if STM32_CLOCK_REF_16M
     default 12000000 if STM32_CLOCK_REF_12M
diff --git a/src/stm32/Makefile b/src/stm32/Makefile
index e5dac2aa..18af2e9d 100644
--- a/src/stm32/Makefile
+++ b/src/stm32/Makefile
@@ -9,6 +9,7 @@ dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1
 dirs-$(CONFIG_MACH_N32G45x) += lib/n32g45x
 dirs-$(CONFIG_MACH_STM32F2) += lib/stm32f2
 dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4
+dirs-$(CONFIG_MACH_STM32F7) += lib/stm32f7
 dirs-$(CONFIG_MACH_STM32G0) += lib/stm32g0
 dirs-$(CONFIG_MACH_STM32G4) += lib/stm32g4
 dirs-$(CONFIG_MACH_STM32H7) += lib/stm32h7
@@ -23,6 +24,7 @@ CFLAGS-$(CONFIG_MACH_N32G45x) += -mcpu=cortex-m4 -Ilib/n32g45x/include
 CFLAGS-$(CONFIG_MACH_STM32F1) += -Ilib/stm32f1/include
 CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include
 CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
+CFLAGS-$(CONFIG_MACH_STM32F7) += -mcpu=cortex-m7 -Ilib/stm32f7/include
 CFLAGS-$(CONFIG_MACH_STM32G0) += -mcpu=cortex-m0plus -Ilib/stm32g0/include
 CFLAGS-$(CONFIG_MACH_STM32G4) += -mcpu=cortex-m4 -Ilib/stm32g4/include
 CFLAGS-$(CONFIG_MACH_STM32H7) += -mcpu=cortex-m7 -Ilib/stm32h7/include
@@ -52,6 +54,9 @@ src-$(CONFIG_MACH_STM32F2) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
 src-$(CONFIG_MACH_STM32F4) += ../lib/stm32f4/system_stm32f4xx.c
 src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c generic/armcm_timer.c
 src-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
+src-$(CONFIG_MACH_STM32F7) += ../lib/stm32f7/system_stm32f7xx.c
+src-$(CONFIG_MACH_STM32F7) += stm32/stm32f7.c generic/armcm_timer.c
+src-$(CONFIG_MACH_STM32F7) += stm32/gpioperiph.c stm32/adc.c stm32/stm32f0_i2c.c
 src-$(CONFIG_MACH_STM32G0) += generic/timer_irq.c stm32/stm32f0_timer.c
 src-$(CONFIG_MACH_STM32G0) += stm32/stm32g0.c stm32/gpioperiph.c
 src-$(CONFIG_MACH_STM32G0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c
diff --git a/src/stm32/dfu_reboot.c b/src/stm32/dfu_reboot.c
index 68f023d1..2b98e0da 100644
--- a/src/stm32/dfu_reboot.c
+++ b/src/stm32/dfu_reboot.c
@@ -36,7 +36,7 @@ dfu_reboot(void)
     irq_disable();
     uint64_t *bflag = (void*)USB_BOOT_FLAG_ADDR;
     *bflag = USB_BOOT_FLAG;
-#if CONFIG_MACH_STM32H7
+#if __CORTEX_M >= 7
     SCB_CleanDCache_by_Addr((void*)bflag, sizeof(*bflag));
 #endif
     NVIC_SystemReset();
diff --git a/src/stm32/gpioperiph.c b/src/stm32/gpioperiph.c
index ef421c77..10d03738 100644
--- a/src/stm32/gpioperiph.c
+++ b/src/stm32/gpioperiph.c
@@ -32,6 +32,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
     // stm32f0 is ~10Mhz at 50pF
     // stm32f2 is ~25Mhz at 40pF
     // stm32f4 is ~50Mhz at 40pF
+    // stm32f7 is ~50Mhz at 40pF
     // stm32g0 is ~30Mhz at 50pF
     // stm32h7 is ~85Mhz at 50pF
     uint32_t ospeed = hs ? 0x03 : (CONFIG_MACH_STM32F0 ? 0x01 : 0x02);
diff --git a/src/stm32/hard_pwm.c b/src/stm32/hard_pwm.c
index a15b1c37..ad30051f 100644
--- a/src/stm32/hard_pwm.c
+++ b/src/stm32/hard_pwm.c
@@ -102,6 +102,19 @@ static const struct gpio_pwm_info pwm_regs[] = {
     {TIM9,  GPIO('E',  6),  2, GPIO_FUNCTION(3)},
     {TIM10, GPIO('B',  8),  1, GPIO_FUNCTION(3)},
     {TIM11, GPIO('B',  9),  1, GPIO_FUNCTION(3)}
+#elif CONFIG_MACH_STM32F7
+    {TIM2, GPIO('A', 15), 1, GPIO_FUNCTION(1)},
+    {TIM2, GPIO('B',  3), 2, GPIO_FUNCTION(1)},
+    {TIM2, GPIO('B', 10), 3, GPIO_FUNCTION(1)},
+    {TIM2, GPIO('B', 11), 4, GPIO_FUNCTION(1)},
+    {TIM3, GPIO('B',  4), 1, GPIO_FUNCTION(1)},
+    {TIM3, GPIO('B',  5), 1, GPIO_FUNCTION(1)},
+    {TIM3, GPIO('C',  8), 2, GPIO_FUNCTION(1)},
+    {TIM3, GPIO('C',  9), 2, GPIO_FUNCTION(1)},
+    {TIM5, GPIO('A', 10), 3, GPIO_FUNCTION(1)},
+    {TIM5, GPIO('E', 13), 3, GPIO_FUNCTION(1)},
+    {TIM5, GPIO('A', 11), 4, GPIO_FUNCTION(1)},
+    {TIM5, GPIO('E', 14), 4, GPIO_FUNCTION(1)},
 #elif CONFIG_MACH_STM32G0
     {TIM15, GPIO('A',  2), 1, GPIO_FUNCTION(5)},
     {TIM15, GPIO('A',  3), 2, GPIO_FUNCTION(5)},
diff --git a/src/stm32/internal.h b/src/stm32/internal.h
index 0422bf65..1d1e0a96 100644
--- a/src/stm32/internal.h
+++ b/src/stm32/internal.h
@@ -12,6 +12,8 @@
 #include "stm32f2xx.h"
 #elif CONFIG_MACH_STM32F4
 #include "stm32f4xx.h"
+#elif CONFIG_MACH_STM32F7
+#include "stm32f7xx.h"
 #elif CONFIG_MACH_STM32G0
 #include "stm32g0xx.h"
 #elif CONFIG_MACH_STM32G4
diff --git a/src/stm32/spi.c b/src/stm32/spi.c
index 17a84232..709055c2 100644
--- a/src/stm32/spi.c
+++ b/src/stm32/spi.c
@@ -86,9 +86,10 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
         gpio_peripheral(spi_bus[bus].mosi_pin, spi_bus[bus].function, 0);
         gpio_peripheral(spi_bus[bus].sck_pin, spi_bus[bus].function, 0);
 
-        // Configure CR2 on stm32 f0/g0/l4/g4
-#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 \
-    || CONFIG_MACH_STM32G4
+        // Configure CR2 on stm32 f0/f7/g0/l4/g4
+#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32F7 || \
+    CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4 || \
+    CONFIG_MACH_STM32L4
         spi->CR2 = SPI_CR2_FRXTH | (7 << SPI_CR2_DS_Pos);
 #endif
     }
diff --git a/src/stm32/stm32f0_i2c.c b/src/stm32/stm32f0_i2c.c
index 48c3ae3e..e9cadccb 100644
--- a/src/stm32/stm32f0_i2c.c
+++ b/src/stm32/stm32f0_i2c.c
@@ -27,6 +27,9 @@ struct i2c_info {
   DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7");
   DECL_ENUMERATION("i2c_bus", "i2c1a", 1);
   DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0");
+#elif CONFIG_MACH_STM32F7
+  DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
+  DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
 #elif CONFIG_MACH_STM32G0
   DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
   DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
@@ -86,6 +89,8 @@ static const struct i2c_info i2c_bus[] = {
     { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
     { I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) },
     { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) },
+#elif CONFIG_MACH_STM32F7
+    { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
 #elif CONFIG_MACH_STM32G0
     { I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(6) },
     { I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(6) },
diff --git a/src/stm32/stm32f7.c b/src/stm32/stm32f7.c
new file mode 100644
index 00000000..f6f27618
--- /dev/null
+++ b/src/stm32/stm32f7.c
@@ -0,0 +1,168 @@
+// Code to setup clocks on stm32f7
+//
+// Copyright (C) 2023  Frederic Morin <frederic.morin.8@gmail.com>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
+#include "board/armcm_boot.h" // VectorTable
+#include "board/armcm_reset.h" // try_request_canboot
+#include "board/irq.h" // irq_disable
+#include "board/misc.h" // bootloader_request
+#include "command.h" // DECL_CONSTANT_STR
+#include "internal.h" // enable_pclock
+#include "sched.h" // sched_main
+
+
+/****************************************************************
+ * Clock setup
+ ****************************************************************/
+
+#define FREQ_PERIPH_DIV 4
+#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
+#define FREQ_USB 48000000
+
+// Map a peripheral address to its enable bits
+struct cline
+lookup_clock_line(uint32_t periph_base)
+{
+    if (periph_base >= AHB1PERIPH_BASE) {
+        uint32_t bit = 1 << ((periph_base - AHB1PERIPH_BASE) / 0x400);
+        return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
+    } else if (periph_base >= APB2PERIPH_BASE) {
+        uint32_t bit = 1 << ((periph_base - APB2PERIPH_BASE) / 0x400);
+        if (bit & 0x700)
+            // Skip ADC peripheral reset as they share a bit
+            return (struct cline){.en=&RCC->APB2ENR, .bit=bit};
+        return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
+    } else {
+        uint32_t bit = 1 << ((periph_base - APB1PERIPH_BASE) / 0x400);
+        return (struct cline){.en=&RCC->APB1ENR, .rst=&RCC->APB1RSTR, .bit=bit};
+    }
+}
+
+// Return the frequency of the given peripheral clock
+uint32_t
+get_pclock_frequency(uint32_t periph_base)
+{
+    return FREQ_PERIPH;
+}
+
+// Enable a GPIO peripheral clock
+void
+gpio_clock_enable(GPIO_TypeDef *regs)
+{
+    uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400;
+    RCC->AHB1ENR |= 1 << rcc_pos;
+    RCC->AHB1ENR;
+}
+
+#if !CONFIG_STM32_CLOCK_REF_INTERNAL
+DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
+#endif
+
+// Main clock setup called at chip startup
+static void
+clock_setup(void)
+{
+    // Configure and enable PLL
+    const uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2;
+    uint32_t pllcfgr;
+    if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
+        // Configure 216Mhz PLL from external crystal (HSE)
+        const uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
+        RCC->CR |= RCC_CR_HSEON;
+        pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
+    } else {
+        // Configure 216Mhz PLL from internal 16Mhz oscillator (HSI)
+        const uint32_t div = 16000000 / pll_base;
+        pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
+    }
+    RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
+                    | (0 << RCC_PLLCFGR_PLLP_Pos)  //  /2
+                    | ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos)
+                    | (2 << RCC_PLLCFGR_PLLR_Pos));
+    RCC->CR |= RCC_CR_PLLON;
+
+    // Enable "over drive"
+    enable_pclock(PWR_BASE);
+    PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN;
+    while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
+        ;
+    PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN | PWR_CR1_ODSWEN;
+    while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
+        ;
+
+    // Enable 48Mhz USB clock
+    if (CONFIG_USB) {
+        // setup PLLSAI
+        const uint32_t plls_base = 2000000, plls_freq = FREQ_USB * 4;
+        RCC->PLLSAICFGR = (
+            ((plls_freq/plls_base) << RCC_PLLSAICFGR_PLLSAIN_Pos)  // *96
+            | (((plls_freq/FREQ_USB)/2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)// /4
+            | ((plls_freq/FREQ_USB) << RCC_PLLSAICFGR_PLLSAIQ_Pos));
+        // enable PLLSAI and wait for PLLSAI lock
+        RCC->CR |= RCC_CR_PLLSAION;
+        while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+            ;
+        // set CLK48 source to PLLSAI
+        RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL;  // RCC_CLK48SOURCE_PLLSAIP
+    }
+
+    // Set flash latency
+    MODIFY_REG(
+        FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_ACR_LATENCY_7WS));
+
+    // Wait for PLL lock
+    while (!(RCC->CR & RCC_CR_PLLRDY))
+        ;
+
+    // Switch system clock to PLL
+    RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL;
+    while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
+        ;
+}
+
+
+/****************************************************************
+ * Bootloader
+ ****************************************************************/
+
+// Handle reboot requests
+void
+bootloader_request(void)
+{
+    try_request_canboot();
+    dfu_reboot();
+}
+
+
+/****************************************************************
+ * Startup
+ ****************************************************************/
+
+// Main entry point - called from armcm_boot.c:ResetHandler()
+void
+armcm_main(void)
+{
+    // Run SystemInit() and then restore VTOR
+    SystemInit();
+    SCB->VTOR = (uint32_t)VectorTable;
+
+    // Reset peripheral clocks (for some bootloaders that don't)
+    RCC->AHB1ENR = 0x00100000;
+    RCC->AHB2ENR = 0x00000000;
+    RCC->AHB3ENR = 0x00000000;
+    RCC->APB1ENR = 0x00000400;
+    RCC->APB2ENR = 0x00000000;
+
+    dfu_reboot_check();
+
+    // STM32F7 specific DWT unlock required prior to timer_init() DWT setup.
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    DWT->LAR = 0xC5ACCE55;
+
+    clock_setup();
+
+    sched_main();
+}
diff --git a/src/stm32/usbotg.c b/src/stm32/usbotg.c
index 74829256..b2d52456 100644
--- a/src/stm32/usbotg.c
+++ b/src/stm32/usbotg.c
@@ -426,7 +426,7 @@ usb_init(void)
     OTG->GUSBCFG = (USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL
                     | (6 << USB_OTG_GUSBCFG_TRDT_Pos));
     OTGD->DCFG |= (3 << USB_OTG_DCFG_DSPD_Pos);
-#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7
+#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32F7
     OTG->GOTGCTL = USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
 #else
     OTG->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;