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| author | Kevin O'Connor <kevin@koconnor.net> | 2020-02-29 13:07:32 -0500 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2020-02-29 13:14:12 -0500 |
| commit | 31b2c3ea7a21a45c975bc6847c39b82d3c458af2 (patch) | |
| tree | 084a285b1fbf2f41b552c47c5d01f688ee7146b8 /src/stm32 | |
| parent | 1c06ea8afe385b65fda9dc140853ff8577014d16 (diff) | |
| download | kutter-31b2c3ea7a21a45c975bc6847c39b82d3c458af2.tar.gz kutter-31b2c3ea7a21a45c975bc6847c39b82d3c458af2.tar.xz kutter-31b2c3ea7a21a45c975bc6847c39b82d3c458af2.zip | |
stm32: Fix broken clock setup on stm32f1
Commit bd6c25c9 introduced a typo that caused the clock divisors to
not be set correctly on stm32f1.
Reported by @brianrjones69.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32')
| -rw-r--r-- | src/stm32/stm32f1.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index 66c4933b..bb07d340 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -140,8 +140,8 @@ clock_setup(void) cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) | ((div2 - 2) << RCC_CFGR_PLLMULL_Pos)); } - RCC->CFGR = (cfgr | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 - | RCC_CFGR_ADCPRE_DIV4); + cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV4; + RCC->CFGR = cfgr; RCC->CR |= RCC_CR_PLLON; // Set flash latency |