stm32: add STM32H723 support

Signed-off-by: Chen.BJ from BigTreeTech chenbj@biqu3d.com
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

1 files changed, 76 insertions, 43 deletions

diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c
index c44f291e..08d68fa2 100644
--- a/src/stm32/stm32h7_adc.c
+++ b/src/stm32/stm32h7_adc.c
@@ -14,47 +14,50 @@
 #include "sched.h" // sched_shutdown
 
 #if CONFIG_MACH_STM32H7
-#define ADCIN_BANK_SIZE                     (20)
-#define RCC_AHBENR_ADC                      (RCC->AHB1ENR)
-#define RCC_AHBENR_ADCEN                    (RCC_AHB1ENR_ADC12EN)
-#define ADC_CKMODE                          (0b11)
-#define ADC_ATICKS                          (0b101)
-#define ADC_RES                             (0b110)
-#define ADC_TS                              (ADC3_COMMON)
+  #define ADCIN_BANK_SIZE                     (20)
+  #define RCC_AHBENR_ADC                      (RCC->AHB1ENR)
+  #define RCC_AHBENR_ADCEN                    (RCC_AHB1ENR_ADC12EN)
+  #define ADC_CKMODE                          (0b11)
+  #define ADC_ATICKS                          (0b101)
+  #define ADC_RES                             (0b110)
+  #define ADC_TS                              (ADC3_COMMON)
+  #if CONFIG_MACH_STM32H723
+    #define PCSEL                               PCSEL_RES0
+  #endif
 
-// Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10)
-#define OVERSAMPLES_EXPONENT 3
-#define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT)
-#define ADC_MEAS_DELAY  (1 + 2.3666*OVERSAMPLES)
+  // Number of samples is 2^OVERSAMPLES_EXPONENT (exponent can be 0-10)
+  #define OVERSAMPLES_EXPONENT 3
+  #define OVERSAMPLES (1 << OVERSAMPLES_EXPONENT)
+  #define ADC_MEAS_DELAY  (1 + 2.3666*OVERSAMPLES)
 
-// LDORDY registers are missing from CMSIS (only available on revision V!)
-#define ADC_ISR_LDORDY_Pos                  (12U)
-#define ADC_ISR_LDORDY_Msk                  (0x1UL << ADC_ISR_LDORDY_Pos)
-#define ADC_ISR_LDORDY                      ADC_ISR_LDORDY_Msk
+  // LDORDY registers are missing from CMSIS (only available on revision V!)
+  #define ADC_ISR_LDORDY_Pos                  (12U)
+  #define ADC_ISR_LDORDY_Msk                  (0x1UL << ADC_ISR_LDORDY_Pos)
+  #define ADC_ISR_LDORDY                      ADC_ISR_LDORDY_Msk
 
 #elif CONFIG_MACH_STM32L4
-#define RCC_AHBENR_ADC                      (RCC->AHB2ENR)
-#define RCC_AHBENR_ADCEN                    (RCC_AHB2ENR_ADCEN)
-#define ADC_CKMODE                          (0)
-#define ADC_ATICKS                          (0b100)
-#define ADC_RES                             (0b00)
-#define ADC_TS                              (ADC12_COMMON)
+  #define RCC_AHBENR_ADC                      (RCC->AHB2ENR)
+  #define RCC_AHBENR_ADCEN                    (RCC_AHB2ENR_ADCEN)
+  #define ADC_CKMODE                          (0)
+  #define ADC_ATICKS                          (0b100)
+  #define ADC_RES                             (0b00)
+  #define ADC_TS                              (ADC12_COMMON)
 
-#define OVERSAMPLES                         (0)
-#define ADC_MEAS_DELAY                      (10)
+  #define OVERSAMPLES                         (0)
+  #define ADC_MEAS_DELAY                      (10)
 
 #elif CONFIG_MACH_STM32G4
-#define ADCIN_BANK_SIZE                     (19)
-#define RCC_AHBENR_ADC                      (RCC->AHB2ENR)
-#define RCC_AHBENR_ADCEN                    (RCC_AHB2ENR_ADC12EN)
-#define ADC_CKMODE                          (0b11)
-#define ADC_ATICKS                          (0b100)
-#define ADC_RES                             (0b00)
-#define ADC_TS                              (ADC12_COMMON)
-#define ADC_CCR_TSEN                        (ADC_CCR_VSENSESEL)
+  #define ADCIN_BANK_SIZE                     (19)
+  #define RCC_AHBENR_ADC                      (RCC->AHB2ENR)
+  #define RCC_AHBENR_ADCEN                    (RCC_AHB2ENR_ADC12EN)
+  #define ADC_CKMODE                          (0b11)
+  #define ADC_ATICKS                          (0b100)
+  #define ADC_RES                             (0b00)
+  #define ADC_TS                              (ADC12_COMMON)
+  #define ADC_CCR_TSEN                        (ADC_CCR_VSENSESEL)
 
-#define OVERSAMPLES                         (0)
-#define ADC_MEAS_DELAY                      (10)
+  #define OVERSAMPLES                         (0)
+  #define ADC_MEAS_DELAY                      (10)
 #endif
 
 #define ADC_TEMPERATURE_PIN 0xfe
@@ -126,8 +129,13 @@ static const uint8_t adc_pins[] = {
     GPIO('H', 3),  //          ADC3_INP14
     GPIO('H', 4),  //          ADC3_INP15
     GPIO('H', 5),  //          ADC3_INP16
+  #if CONFIG_MACH_STM32H723
+    ADC_TEMPERATURE_PIN,
+    0,
+  #else
     0,             //              Vbat/4
     ADC_TEMPERATURE_PIN,//         VSENSE
+  #endif
     0,             //             VREFINT
 #elif CONFIG_MACH_STM32G4
     0,                      // [0] vssa
@@ -239,20 +247,31 @@ gpio_adc_setup(uint32_t pin)
     }
 
     // Enable the ADC
-    if (!(adc->CR & ADC_CR_ADEN)){
+    if (!(adc->CR & ADC_CR_ADEN)) {
+        // STM32H723 ADC3 and ADC1/2 registers are slightly different
+        uint8_t is_stm32h723_adc3 = 0;
+#if CONFIG_MACH_STM32H723
+        if (adc == ADC3) {
+            is_stm32h723_adc3 = 1;
+        }
+#endif
         // Pwr
         // Exit deep power down
         MODIFY_REG(adc->CR, ADC_CR_DEEPPWD_Msk, 0);
         // Switch on voltage regulator
         adc->CR |= ADC_CR_ADVREGEN;
 #ifdef ADC_ISR_LDORDY
-        while(!(adc->ISR & ADC_ISR_LDORDY))
-            ;
-#else // stm32l4 lacks ldordy, delay to spec instead
-        uint32_t end = timer_read_time() + timer_from_us(20);
-        while (timer_is_before(timer_read_time(), end))
-            ;
+        if (is_stm32h723_adc3 == 0) {
+            while(!(adc->ISR & ADC_ISR_LDORDY))
+                ;
+        } else
 #endif
+        {
+            // stm32h723 ADC3 & stm32l4 lacks ldordy, delay to spec instead
+            uint32_t end = timer_read_time() + timer_from_us(20);
+            while (timer_is_before(timer_read_time(), end))
+                ;
+        }
 
         // Set Boost mode for 25Mhz < ADC clock <= 50Mhz
 #ifdef ADC_CR_BOOST
@@ -295,12 +314,26 @@ gpio_adc_setup(uint32_t pin)
         // Disable Continuous Mode
         MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0);
         // Set to 12 bit
-        MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES << ADC_CFGR_RES_Pos);
+        if (is_stm32h723_adc3) {
+#ifdef ADC3_CFGR_RES
+            MODIFY_REG(adc->CFGR, ADC3_CFGR_RES_Msk, 0 << ADC3_CFGR_RES_Pos);
+            MODIFY_REG(adc->CFGR, ADC3_CFGR_ALIGN_Msk, 0<<ADC3_CFGR_ALIGN_Pos);
+#endif
+        } else {
+            MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos);
+        }
 #if CONFIG_MACH_STM32H7
         // Set hardware oversampling
         MODIFY_REG(adc->CFGR2, ADC_CFGR2_ROVSE_Msk, ADC_CFGR2_ROVSE);
-        MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk,
-            (OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos);
+        if (is_stm32h723_adc3) {
+#ifdef ADC3_CFGR2_OVSR
+            MODIFY_REG(adc->CFGR2, ADC3_CFGR2_OVSR_Msk,
+                       (OVERSAMPLES_EXPONENT - 1) << ADC3_CFGR2_OVSR_Pos);
+#endif
+        } else {
+            MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSR_Msk,
+                       (OVERSAMPLES - 1) << ADC_CFGR2_OVSR_Pos);
+        }
         MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk,
             OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos);
 #else // stm32l4