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authorKevin O'Connor <kevin@koconnor.net>2019-08-12 09:37:21 -0400
committerKevin O'Connor <kevin@koconnor.net>2019-08-14 19:33:11 -0400
commit841150ff007556e13664716d5ad0cdf7507d0482 (patch)
tree5091f8d877afe8d3a109c045dfa84395572b434e /src/stm32/stm32f4.c
parenteffe6f6ddd5132db4ab4f88bf8616aab575e7691 (diff)
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stm32: Enable 48Mhz USB clock on stm32f446
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f4.c')
-rw-r--r--src/stm32/stm32f4.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c
index d0a2f249..dab8d524 100644
--- a/src/stm32/stm32f4.c
+++ b/src/stm32/stm32f4.c
@@ -131,6 +131,28 @@ enable_clock_stm32f446(void)
PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN | PWR_CR_ODSWEN;
while (!(PWR->CSR & PWR_CSR_ODSWRDY))
;
+
+ // Enable 48Mhz USB clock
+ if (CONFIG_USBSERIAL) {
+ if (CONFIG_CLOCK_REF_8M) {
+ RCC->PLLSAICFGR = (
+ (4 << RCC_PLLSAICFGR_PLLSAIM_Pos)
+ | (96 << RCC_PLLSAICFGR_PLLSAIN_Pos)
+ | (1 << RCC_PLLSAICFGR_PLLSAIP_Pos)
+ | (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos));
+ } else {
+ RCC->PLLSAICFGR = (
+ (8 << RCC_PLLSAICFGR_PLLSAIM_Pos)
+ | (96 << RCC_PLLSAICFGR_PLLSAIN_Pos)
+ | (1 << RCC_PLLSAICFGR_PLLSAIP_Pos)
+ | (4 << RCC_PLLSAICFGR_PLLSAIQ_Pos));
+ }
+ RCC->CR |= RCC_CR_PLLSAION;
+ while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+ ;
+
+ RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL;
+ }
#endif
}