diff options
| author | Kevin O'Connor <kevin@koconnor.net> | 2019-11-25 14:00:30 -0500 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-11-25 14:04:26 -0500 |
| commit | bd6c25c9f8c28831d146f9077a0a2aa636c6e037 (patch) | |
| tree | cbeeb8a98ebca96b815b6cffb2d60affcf744cb6 /src/stm32/stm32f1.c | |
| parent | 0b0e5a911eb398482b9d73043fe82b5db99affe9 (diff) | |
| download | kutter-bd6c25c9f8c28831d146f9077a0a2aa636c6e037.tar.gz kutter-bd6c25c9f8c28831d146f9077a0a2aa636c6e037.tar.xz kutter-bd6c25c9f8c28831d146f9077a0a2aa636c6e037.zip | |
stm32: Allow external crystal speed to be customized in Kconfig
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f1.c')
| -rw-r--r-- | src/stm32/stm32f1.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index 33509ab7..66c4933b 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -4,7 +4,7 @@ // // This file may be distributed under the terms of the GNU GPLv3 license. -#include "autoconf.h" // CONFIG_CLOCK_REF_8M +#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ #include "board/armcm_boot.h" // VectorTable #include "board/irq.h" // irq_disable #include "board/usb_cdc.h" // usb_request_bootloader @@ -129,19 +129,19 @@ clock_setup(void) { // Configure and enable PLL uint32_t cfgr; - if (CONFIG_CLOCK_REF_8M) { - // Configure 72Mhz PLL from external 8Mhz crystal (HSE) + if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { + // Configure 72Mhz PLL from external crystal (HSE) + uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ; RCC->CR |= RCC_CR_HSEON; - cfgr = ((1 << RCC_CFGR_PLLSRC_Pos) | ((9 - 2) << RCC_CFGR_PLLMULL_Pos) - | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 - | RCC_CFGR_ADCPRE_DIV4); + cfgr = (1 << RCC_CFGR_PLLSRC_Pos) | ((div - 2) << RCC_CFGR_PLLMULL_Pos); } else { // Configure 72Mhz PLL from internal 8Mhz oscillator (HSI) - cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) | ((18 - 2) << RCC_CFGR_PLLMULL_Pos) - | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 - | RCC_CFGR_ADCPRE_DIV4); + uint32_t div2 = (CONFIG_CLOCK_FREQ / 8000000) * 2; + cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) + | ((div2 - 2) << RCC_CFGR_PLLMULL_Pos)); } - RCC->CFGR = cfgr; + RCC->CFGR = (cfgr | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 + | RCC_CFGR_ADCPRE_DIV4); RCC->CR |= RCC_CR_PLLON; // Set flash latency |