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author | Kevin O'Connor <kevin@koconnor.net> | 2021-12-24 12:23:56 -0500 |
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committer | Kevin O'Connor <kevin@koconnor.net> | 2021-12-30 12:18:05 -0500 |
commit | 8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d (patch) | |
tree | c6f888a77627d6276ed84394c203c552ba348a15 /src/stm32/stm32f1.c | |
parent | 9bdd61758e61d4652ae09515425c3316c6cfe905 (diff) | |
download | kutter-8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d.tar.gz kutter-8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d.tar.xz kutter-8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d.zip |
stm32: Unify enable_pclock() code
Unify the handling of the enable_pclock() and is_enabled_pclock() code
across all stm32 chips. All chips will now perform a peripheral reset
on enable_pclock() (this is a change for stm32f0 and stm32h7). The
enable_pclock() code will now also disable irqs during the enable.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f1.c')
-rw-r--r-- | src/stm32/stm32f1.c | 45 |
1 files changed, 11 insertions, 34 deletions
diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index 9508a291..5680cfba 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -18,42 +18,19 @@ #define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 2) -// Enable a peripheral clock -void -enable_pclock(uint32_t periph_base) -{ - if (periph_base < APB2PERIPH_BASE) { - uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; - RCC->APB1ENR |= (1<<pos); - RCC->APB1ENR; - RCC->APB1RSTR |= (1<<pos); - RCC->APB1RSTR &= ~(1<<pos); - } else if (periph_base < AHBPERIPH_BASE) { - uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400; - RCC->APB2ENR |= (1<<pos); - RCC->APB2ENR; - RCC->APB2RSTR |= (1<<pos); - RCC->APB2RSTR &= ~(1<<pos); - } else { - uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400; - RCC->AHBENR |= (1<<pos); - RCC->AHBENR; - } -} - -// Check if a peripheral clock has been enabled -int -is_enabled_pclock(uint32_t periph_base) +// Map a peripheral address to its enable bits +struct cline +lookup_clock_line(uint32_t periph_base) { - if (periph_base < APB2PERIPH_BASE) { - uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; - return RCC->APB1ENR & (1<<pos); - } else if (periph_base < AHBPERIPH_BASE) { - uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400; - return RCC->APB2ENR & (1<<pos); + if (periph_base >= AHBPERIPH_BASE) { + uint32_t bit = 1 << ((periph_base - AHBPERIPH_BASE) / 0x400); + return (struct cline){.en=&RCC->AHBENR, .bit=bit}; + } else if (periph_base >= APB2PERIPH_BASE) { + uint32_t bit = 1 << ((periph_base - APB2PERIPH_BASE) / 0x400); + return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit}; } else { - uint32_t pos = (periph_base - AHBPERIPH_BASE) / 0x400; - return RCC->AHBENR & (1<<pos); + uint32_t bit = 1 << ((periph_base - APB1PERIPH_BASE) / 0x400); + return (struct cline){.en=&RCC->APB1ENR, .rst=&RCC->APB1RSTR, .bit=bit}; } } |