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| author | Kevin O'Connor <kevin@koconnor.net> | 2022-10-31 13:13:32 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2022-10-31 15:12:30 -0400 |
| commit | 972ae4ab7c968d133e5160fe1a71dac63fd08a7b (patch) | |
| tree | 11d97b4e683ce56ec2be1b74d5b830670e1dabe2 /src/stm32/stm32f0_serial.c | |
| parent | 26e6ade1757e20ce3a1253c4c4d0a915960a38d8 (diff) | |
| download | kutter-972ae4ab7c968d133e5160fe1a71dac63fd08a7b.tar.gz kutter-972ae4ab7c968d133e5160fe1a71dac63fd08a7b.tar.xz kutter-972ae4ab7c968d133e5160fe1a71dac63fd08a7b.zip | |
stm32: Use stm32f0_serial.c on stm32h7 chips
The stm32h7 uses similar usart hardware as the stm32f0 and stm32g0
chips. Use the same code implementation for all these chips.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/stm32f0_serial.c')
| -rw-r--r-- | src/stm32/stm32f0_serial.c | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/src/stm32/stm32f0_serial.c b/src/stm32/stm32f0_serial.c index da76be42..f7f17dfc 100644 --- a/src/stm32/stm32f0_serial.c +++ b/src/stm32/stm32f0_serial.c @@ -16,21 +16,21 @@ DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9"); #define GPIO_Rx GPIO('A', 10) #define GPIO_Tx GPIO('A', 9) - #define USARTx_FUNCTION GPIO_FUNCTION(1) + #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 1) #define USARTx USART1 #define USARTx_IRQn USART1_IRQn #elif CONFIG_STM32_SERIAL_USART1_ALT_PB7_PB6 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB7,PB6"); #define GPIO_Rx GPIO('B', 7) #define GPIO_Tx GPIO('B', 6) - #define USARTx_FUNCTION GPIO_FUNCTION(0) + #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 0) #define USARTx USART1 #define USARTx_IRQn USART1_IRQn #elif CONFIG_STM32_SERIAL_USART2 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2"); #define GPIO_Rx GPIO('A', 3) #define GPIO_Tx GPIO('A', 2) - #define USARTx_FUNCTION GPIO_FUNCTION(1) + #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32H7 ? 7 : 1) #define USARTx USART2 #define USARTx_IRQn USART2_IRQn #elif CONFIG_STM32_SERIAL_USART2_ALT_PA15_PA14 @@ -40,6 +40,34 @@ #define USARTx_FUNCTION GPIO_FUNCTION(1) #define USARTx USART2 #define USARTx_IRQn USART2_IRQn +#elif CONFIG_STM32_SERIAL_USART2_ALT_PD6_PD5 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD6,PD5"); + #define GPIO_Rx GPIO('D', 6) + #define GPIO_Tx GPIO('D', 5) + #define USARTx_FUNCTION GPIO_FUNCTION(7) + #define USARTx USART2 + #define USARTx_IRQn USART2_IRQn +#elif CONFIG_STM32_SERIAL_USART3 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB11,PB10"); + #define GPIO_Rx GPIO('B', 11) + #define GPIO_Tx GPIO('B', 10) + #define USARTx_FUNCTION GPIO_FUNCTION(7) + #define USARTx USART3 + #define USARTx_IRQn USART3_IRQn +#elif CONFIG_STM32_SERIAL_USART3_ALT_PD9_PD8 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD9,PD8"); + #define GPIO_Rx GPIO('D', 9) + #define GPIO_Tx GPIO('D', 8) + #define USARTx_FUNCTION GPIO_FUNCTION(7) + #define USARTx USART3 + #define USARTx_IRQn USART3_IRQn +#elif CONFIG_STM32_SERIAL_UART4 + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA1,PA0"); + #define GPIO_Rx GPIO('A', 1) + #define GPIO_Tx GPIO('A', 0) + #define USARTx_FUNCTION GPIO_FUNCTION(8) + #define USARTx UART4 + #define USARTx_IRQn UART4_IRQn #endif #if CONFIG_MACH_STM32F031 @@ -57,6 +85,10 @@ #define USART_ISR_TXE USART_ISR_TXE_TXFNF #define USART_BRR_DIV_MANTISSA_Pos 4 #define USART_BRR_DIV_FRACTION_Pos 0 +#elif CONFIG_MACH_STM32H7 + // The stm32h7 has slightly different register names + #define USART_ISR_RXNE USART_ISR_RXNE_RXFNE + #define USART_ISR_TXE USART_ISR_TXE_TXFNF #endif #define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \ |