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| author | Kevin O'Connor <kevin@koconnor.net> | 2019-08-21 13:52:43 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-08-22 09:58:58 -0400 |
| commit | 4ef53ab0953ac664a9935b26cd6536aac44eaec7 (patch) | |
| tree | 5cb2fb571e7ae34c30457eed01c8c8766c4cd115 /src/stm32/serial.c | |
| parent | a44bc950a393644b1af6b2e83bdcfc265a852583 (diff) | |
| download | kutter-4ef53ab0953ac664a9935b26cd6536aac44eaec7.tar.gz kutter-4ef53ab0953ac664a9935b26cd6536aac44eaec7.tar.xz kutter-4ef53ab0953ac664a9935b26cd6536aac44eaec7.zip | |
stm32: Update code to use armcm_boot mechanism
Replace the stm32 provided assembler with the src/generic/armcm_boot.c
mechanism.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/serial.c')
| -rw-r--r-- | src/stm32/serial.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/stm32/serial.c b/src/stm32/serial.c index 925d4f8e..20eda817 100644 --- a/src/stm32/serial.c +++ b/src/stm32/serial.c @@ -5,6 +5,7 @@ // This file may be distributed under the terms of the GNU GPLv3 license. #include "autoconf.h" // CONFIG_SERIAL_BAUD +#include "board/armcm_boot.h" // armcm_enable_irq #include "board/serial_irq.h" // serial_rx_byte #include "command.h" // DECL_CONSTANT_STR #include "internal.h" // enable_pclock @@ -17,34 +18,30 @@ DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9"); #define GPIO_Tx GPIO('A', 9) #define USARTx USART1 #define USARTx_IRQn USART1_IRQn -#define USARTx_IRQHandler USART1_IRQHandler #elif CONFIG_SERIAL_PORT == 2 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2"); #define GPIO_Rx GPIO('A', 3) #define GPIO_Tx GPIO('A', 2) #define USARTx USART2 #define USARTx_IRQn USART2_IRQn -#define USARTx_IRQHandler USART2_IRQHandler #elif CONFIG_SERIAL_PORT == 103 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD9,PD8"); #define GPIO_Rx GPIO('D', 9) #define GPIO_Tx GPIO('D', 8) #define USARTx USART3 #define USARTx_IRQn USART3_IRQn -#define USARTx_IRQHandler USART3_IRQHandler #else DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB11,PB10"); #define GPIO_Rx GPIO('B', 11) #define GPIO_Tx GPIO('B', 10) #define USARTx USART3 #define USARTx_IRQn USART3_IRQn -#define USARTx_IRQHandler USART3_IRQHandler #endif #define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \ | USART_CR1_RXNEIE) -void __visible +void USARTx_IRQHandler(void) { uint32_t sr = USARTx->SR; @@ -76,8 +73,7 @@ serial_init(void) USARTx->BRR = (((div / 16) << USART_BRR_DIV_Mantissa_Pos) | ((div % 16) << USART_BRR_DIV_Fraction_Pos)); USARTx->CR1 = CR1_FLAGS; - NVIC_SetPriority(USARTx_IRQn, 0); - NVIC_EnableIRQ(USARTx_IRQn); + armcm_enable_irq(USARTx_IRQHandler, USARTx_IRQn, 0); gpio_peripheral(GPIO_Rx, GPIO_FUNCTION(7), 1); gpio_peripheral(GPIO_Tx, GPIO_FUNCTION(7), 0); |