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| author | Dropeffect GmbH <code@dropeffect.com> | 2024-05-02 11:25:08 +0100 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2024-05-14 11:53:38 -0400 |
| commit | 80b55d352811c628bd0204fdda837acb9fce31d1 (patch) | |
| tree | ae82f08c7482992a79f151793259c9be6f068fa3 /src/stm32/fdcan.c | |
| parent | 8f510da12bf51a58205ebd81873ec8efbaa32c43 (diff) | |
| download | kutter-80b55d352811c628bd0204fdda837acb9fce31d1.tar.gz kutter-80b55d352811c628bd0204fdda837acb9fce31d1.tar.xz kutter-80b55d352811c628bd0204fdda837acb9fce31d1.zip | |
stm32: Add FDCAN2 channel needed for stm32g4 alternate pins
Some of the alternate pins defined are routed to FDCAN2 instead of
FDCAN1, this commit uses the correct IRQ register and peripheral
clock enable bit to enable FDCAN on those pins.
Signed-off-by: Amr Elsayed from Dropeffect GmbH <code@dropeffect.com>
Diffstat (limited to 'src/stm32/fdcan.c')
| -rw-r--r-- | src/stm32/fdcan.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/stm32/fdcan.c b/src/stm32/fdcan.c index b0e8c01d..5344d26b 100644 --- a/src/stm32/fdcan.c +++ b/src/stm32/fdcan.c @@ -60,16 +60,23 @@ || CONFIG_STM32_CANBUS_PB5_PB6 ||CONFIG_STM32_CANBUS_PB12_PB13) #define SOC_CAN FDCAN1 #define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1) + #if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4 + #define CAN_IT0_IRQn FDCAN1_IT0_IRQn + #endif #else #define SOC_CAN FDCAN2 #define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan2) + #if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4 + #define CAN_IT0_IRQn FDCAN2_IT0_IRQn + #endif #endif #if CONFIG_MACH_STM32G0 #define CAN_IT0_IRQn TIM16_FDCAN_IT0_IRQn #define CAN_FUNCTION GPIO_FUNCTION(3) // Alternative function mapping number -#elif CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4 - #define CAN_IT0_IRQn FDCAN1_IT0_IRQn +#endif + +#if CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32G4 #define CAN_FUNCTION GPIO_FUNCTION(9) // Alternative function mapping number #endif |