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authorbigtreetech <tech@biqu3d.com>2023-01-12 15:47:08 +0800
committerKevin O'Connor <kevin@koconnor.net>2023-02-03 15:12:09 -0500
commit1979c9d090c9cef241de4e7f06b6ed39a2bf2c9b (patch)
tree20e63edf3f66b340bac7241fb7ee0d9f823853ee /src/stm32/fdcan.c
parent13fd2833ce3b485d3c20ace6260fa87166746771 (diff)
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stm32: add PB12/PB13 FDCAN2 support STM32G0B1
Signed-off-by: Alan.Ma from BigTreeTech tech@biqu3d.com Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/fdcan.c')
-rw-r--r--src/stm32/fdcan.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/stm32/fdcan.c b/src/stm32/fdcan.c
index 3b01b482..9198c7dc 100644
--- a/src/stm32/fdcan.c
+++ b/src/stm32/fdcan.c
@@ -46,9 +46,14 @@
DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC2,PC3");
#define GPIO_Rx GPIO('C', 2)
#define GPIO_Tx GPIO('C', 3)
+#elif CONFIG_STM32_CANBUS_PB12_PB13
+ DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB12,PB13");
+ #define GPIO_Rx GPIO('B', 12)
+ #define GPIO_Tx GPIO('B', 13)
#endif
-#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3)
+#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3 \
+ || CONFIG_STM32_CANBUS_PB12_PB13)
#define SOC_CAN FDCAN1
#define MSG_RAM (((struct fdcan_ram_layout*)SRAMCAN_BASE)->fdcan1)
#else