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authorKevin O'Connor <kevin@koconnor.net>2020-01-25 11:23:58 -0500
committerKevin O'Connor <kevin@koconnor.net>2020-01-25 11:23:58 -0500
commit502e83725b1bbcdf684d9a99220769ca831c0164 (patch)
tree4afcb67effbcd788be8b5c03297ea3b9a7a86d3c /src/stm32/adc.c
parentbf3fa979f9a75288aaae74214e5e8536a1fa3b6b (diff)
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stm32: Reset adc calibration prior to starting calibration
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/stm32/adc.c')
-rw-r--r--src/stm32/adc.c25
1 files changed, 17 insertions, 8 deletions
diff --git a/src/stm32/adc.c b/src/stm32/adc.c
index efe71a2f..03d599b2 100644
--- a/src/stm32/adc.c
+++ b/src/stm32/adc.c
@@ -39,6 +39,22 @@ static const uint8_t adc_pins[] = {
// stm32f407: ADC clock=21Mhz, Tconv=12, Tsamp=84, total=4.571us
// stm32f446: ADC clock=22.5Mhz, Tconv=12, Tsamp=84, total=4.267us
+// Perform calibration on stm32f103
+static void
+adc_calibrate(ADC_TypeDef *adc)
+{
+#if CONFIG_MACH_STM32F1
+ adc->CR2 = ADC_CR2_ADON;
+ udelay(10);
+ adc->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
+ while (adc->CR2 & ADC_CR2_RSTCAL)
+ ;
+ adc->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
+ while (adc->CR2 & ADC_CR2_CAL)
+ ;
+#endif
+}
+
struct gpio_adc
gpio_adc_setup(uint32_t pin)
{
@@ -66,6 +82,7 @@ gpio_adc_setup(uint32_t pin)
// Enable the ADC
if (!is_enabled_pclock(adc_base)) {
enable_pclock(adc_base);
+ adc_calibrate(adc);
uint32_t aticks = 4; // 4-6us sample time (depending on stm32 chip)
adc->SMPR1 = (aticks | (aticks << 3) | (aticks << 6) | (aticks << 9)
| (aticks << 12) | (aticks << 15) | (aticks << 18)
@@ -75,14 +92,6 @@ gpio_adc_setup(uint32_t pin)
| (aticks << 12) | (aticks << 15) | (aticks << 18)
| (aticks << 21) | (aticks << 24) | (aticks << 27));
adc->CR2 = CR2_FLAGS;
-
-#if CONFIG_MACH_STM32F1
- // Perform calibration
- udelay(10);
- adc->CR2 = ADC_CR2_CAL | CR2_FLAGS;
- while (adc->CR2 & ADC_CR2_CAL)
- ;
-#endif
}
gpio_peripheral(pin, GPIO_ANALOG, 0);