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| author | Kevin O'Connor <kevin@koconnor.net> | 2024-10-26 19:00:42 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2024-11-14 11:17:52 -0500 |
| commit | 61f81bdb26e91a18eddd5dd118a45011ee9e314d (patch) | |
| tree | 00f762b1522a17ba609dae9b72bdcd83f9b804c6 /src/rp2040 | |
| parent | c28ed06e9802a93b329f7b275677650b21b2ce92 (diff) | |
| download | kutter-61f81bdb26e91a18eddd5dd118a45011ee9e314d.tar.gz kutter-61f81bdb26e91a18eddd5dd118a45011ee9e314d.tar.xz kutter-61f81bdb26e91a18eddd5dd118a45011ee9e314d.zip | |
rp2040: Use a higher USB PLL internal frequency
The rp2350 chip requires a higher internal frequency, so choose a
value that works for both rp2040 and rp2350.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/rp2040')
| -rw-r--r-- | src/rp2040/main.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/rp2040/main.c b/src/rp2040/main.c index 75d8760d..f94f4782 100644 --- a/src/rp2040/main.c +++ b/src/rp2040/main.c @@ -94,6 +94,10 @@ pll_setup(pll_hw_t *pll, uint32_t mul, uint32_t postdiv) { // Setup pll uint32_t refdiv = 1, fbdiv = mul, postdiv2 = 2, postdiv1 = postdiv/postdiv2; + if (postdiv1 > 0x07) { + postdiv1 >>= 1; + postdiv2 <<= 1; + } pll->cs = refdiv; pll->fbdiv_int = fbdiv; pll->pwr = PLL_PWR_DSMPD_BITS | PLL_PWR_POSTDIVPD_BITS; @@ -143,7 +147,7 @@ clock_setup(void) // Setup pll_usb enable_pclock(RESETS_RESET_PLL_USB_BITS); - pll_setup(pll_usb_hw, 40, 40*FREQ_XOSC/FREQ_USB); + pll_setup(pll_usb_hw, 80, 80*FREQ_XOSC/FREQ_USB); // Setup peripheral clocks clk_aux_setup(clk_peri, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS); |