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| author | Kevin O'Connor <kevin@koconnor.net> | 2020-07-10 13:41:13 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2020-07-10 16:08:18 -0400 |
| commit | c83688b7bc7fcbc1a413d5707d11a2d2b674d48d (patch) | |
| tree | 0c31a119012752a62bed2a86cf5a1bfd2a075f81 /src/lpc176x | |
| parent | 5dc0c8aac0c1469270779d399ecdd7dcdbd53247 (diff) | |
| download | kutter-c83688b7bc7fcbc1a413d5707d11a2d2b674d48d.tar.gz kutter-c83688b7bc7fcbc1a413d5707d11a2d2b674d48d.tar.xz kutter-c83688b7bc7fcbc1a413d5707d11a2d2b674d48d.zip | |
lpc176x: Fix spi mode bits
The lpc176x hardware spi initialization code was swapping the CPOL and
CPHA bits. This caused the MAX31865 and MAX31856 chips to not work
correctly.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/lpc176x')
| -rw-r--r-- | src/lpc176x/spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/lpc176x/spi.c b/src/lpc176x/spi.c index 28bce200..2e644a1e 100644 --- a/src/lpc176x/spi.c +++ b/src/lpc176x/spi.c @@ -61,7 +61,7 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate) uint32_t pclk = SystemCoreClock; uint32_t div = DIV_ROUND_UP(pclk/2, rate) << 1; res.cpsr = div < 2 ? 2 : (div > 254 ? 254 : div); - res.cr0 = 0x07 | (mode << 6); + res.cr0 = 0x07 | ((mode & 2) << 5) | ((mode & 1) << 7); return res; } |