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| author | Kevin O'Connor <kevin@koconnor.net> | 2019-08-22 09:16:37 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-08-22 09:58:58 -0400 |
| commit | 6409eda0580810599422c2a8a2ddce171d9e47ad (patch) | |
| tree | 38fa305af82a237da53f957475f4e0c43b7c8010 /src/lpc176x/serial.c | |
| parent | 44f862388fd9275199276e70abcea1dd819450d8 (diff) | |
| download | kutter-6409eda0580810599422c2a8a2ddce171d9e47ad.tar.gz kutter-6409eda0580810599422c2a8a2ddce171d9e47ad.tar.xz kutter-6409eda0580810599422c2a8a2ddce171d9e47ad.zip | |
lpc176x: Move irq handler code above irq setup
Only code movement.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/lpc176x/serial.c')
| -rw-r--r-- | src/lpc176x/serial.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/src/lpc176x/serial.c b/src/lpc176x/serial.c index 63755467..f36a485c 100644 --- a/src/lpc176x/serial.c +++ b/src/lpc176x/serial.c @@ -12,35 +12,6 @@ #include "internal.h" // gpio_peripheral #include "sched.h" // DECL_INIT -DECL_CONSTANT_STR("RESERVE_PINS_serial", "P0.3,P0.2"); - -void -serial_init(void) -{ - // Setup baud - LPC_UART0->LCR = (1<<7); // set DLAB bit - enable_pclock(PCLK_UART0); - uint32_t pclk = SystemCoreClock; - uint32_t div = pclk / (CONFIG_SERIAL_BAUD * 16); - LPC_UART0->DLL = div & 0xff; - LPC_UART0->DLM = (div >> 8) & 0xff; - LPC_UART0->FDR = 0x10; - LPC_UART0->LCR = 3; // 8N1 ; clear DLAB bit - - // Enable fifo - LPC_UART0->FCR = 0x01; - - // Setup pins - gpio_peripheral(GPIO(0, 3), 1, 0); - gpio_peripheral(GPIO(0, 2), 1, 0); - - // Enable receive irq - NVIC_SetPriority(UART0_IRQn, 0); - NVIC_EnableIRQ(UART0_IRQn); - LPC_UART0->IER = 0x01; -} -DECL_INIT(serial_init); - // Write tx bytes to the serial port static void kick_tx(void) @@ -81,3 +52,32 @@ serial_enable_tx_irq(void) irq_restore(flag); } } + +DECL_CONSTANT_STR("RESERVE_PINS_serial", "P0.3,P0.2"); + +void +serial_init(void) +{ + // Setup baud + LPC_UART0->LCR = (1<<7); // set DLAB bit + enable_pclock(PCLK_UART0); + uint32_t pclk = SystemCoreClock; + uint32_t div = pclk / (CONFIG_SERIAL_BAUD * 16); + LPC_UART0->DLL = div & 0xff; + LPC_UART0->DLM = (div >> 8) & 0xff; + LPC_UART0->FDR = 0x10; + LPC_UART0->LCR = 3; // 8N1 ; clear DLAB bit + + // Enable fifo + LPC_UART0->FCR = 0x01; + + // Setup pins + gpio_peripheral(GPIO(0, 3), 1, 0); + gpio_peripheral(GPIO(0, 2), 1, 0); + + // Enable receive irq + NVIC_SetPriority(UART0_IRQn, 0); + NVIC_EnableIRQ(UART0_IRQn); + LPC_UART0->IER = 0x01; +} +DECL_INIT(serial_init); |