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authorKevin O'Connor <kevin@koconnor.net>2019-03-31 23:37:17 -0400
committerKevin O'Connor <kevin@koconnor.net>2019-04-04 18:29:31 -0400
commitbc9fd03dabc38ae55fae3151e94cffe7157b95bd (patch)
treebee1984f5afd76e6c4d9e013d8984076dd90e422 /src/atsamd/serial.c
parent7e8ecfe177945e10a1e4adaac64c1d803e9405ff (diff)
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atsamd: Use enumerations for buses and reserve pins
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/atsamd/serial.c')
-rw-r--r--src/atsamd/serial.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/atsamd/serial.c b/src/atsamd/serial.c
index 91e85796..fd7dcaac 100644
--- a/src/atsamd/serial.c
+++ b/src/atsamd/serial.c
@@ -5,27 +5,30 @@
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "board/serial_irq.h" // serial_rx_data
+#include "command.h" // DECL_CONSTANT_STR
#include "internal.h" // enable_pclock
#include "sched.h" // DECL_INIT
+DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA11,PA10");
+
void
serial_init(void)
{
// Enable serial clock
enable_pclock(SERCOM0_GCLK_ID_CORE, ID_SERCOM0);
// Enable pins
- gpio_peripheral(GPIO('A', 10), 'C', 0);
gpio_peripheral(GPIO('A', 11), 'C', 0);
+ gpio_peripheral(GPIO('A', 10), 'C', 0);
// Configure serial
SercomUsart *su = &SERCOM0->USART;
su->CTRLA.reg = 0;
uint32_t areg = (SERCOM_USART_CTRLA_MODE(1)
| SERCOM_USART_CTRLA_DORD
| SERCOM_USART_CTRLA_SAMPR(1)
- | SERCOM_USART_CTRLA_TXPO(1)
- | SERCOM_USART_CTRLA_RXPO(3));
+ | SERCOM_USART_CTRLA_RXPO(3)
+ | SERCOM_USART_CTRLA_TXPO(1));
su->CTRLA.reg = areg;
- su->CTRLB.reg = SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN;
+ su->CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN;
uint32_t freq = get_pclock_frequency(SERCOM0_GCLK_ID_CORE);
uint32_t baud8 = freq / (2 * CONFIG_SERIAL_BAUD);
su->BAUD.reg = (SERCOM_USART_BAUD_FRAC_BAUD(baud8 / 8)