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author | Kevin O'Connor <kevin@koconnor.net> | 2021-06-19 20:05:48 -0400 |
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committer | Kevin O'Connor <kevin@koconnor.net> | 2021-07-04 10:11:02 -0400 |
commit | cc0969dd0539c7bcc89652a793d7ccfc0c3b0fcd (patch) | |
tree | 29255c13a084015696ed32c25761823b1e1f456f /lib/rp2040/hardware/structs/dma.h | |
parent | 1b79ffcad2822a6105a453f78ab6d6af9c6f692a (diff) | |
download | kutter-cc0969dd0539c7bcc89652a793d7ccfc0c3b0fcd.tar.gz kutter-cc0969dd0539c7bcc89652a793d7ccfc0c3b0fcd.tar.xz kutter-cc0969dd0539c7bcc89652a793d7ccfc0c3b0fcd.zip |
lib: Add rp2040 build files
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'lib/rp2040/hardware/structs/dma.h')
-rw-r--r-- | lib/rp2040/hardware/structs/dma.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/lib/rp2040/hardware/structs/dma.h b/lib/rp2040/hardware/structs/dma.h new file mode 100644 index 00000000..06cdf792 --- /dev/null +++ b/lib/rp2040/hardware/structs/dma.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/dma.h" + +typedef struct { + io_rw_32 read_addr; + io_rw_32 write_addr; + io_rw_32 transfer_count; + io_rw_32 ctrl_trig; + io_rw_32 al1_ctrl; + io_rw_32 al1_read_addr; + io_rw_32 al1_write_addr; + io_rw_32 al1_transfer_count_trig; + io_rw_32 al2_ctrl; + io_rw_32 al2_transfer_count; + io_rw_32 al2_read_addr; + io_rw_32 al2_write_addr_trig; + io_rw_32 al3_ctrl; + io_rw_32 al3_write_addr; + io_rw_32 al3_transfer_count; + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; + uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + io_ro_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_rw_32 ints0; + uint32_t _pad1[1]; + io_rw_32 inte1; + io_rw_32 intf1; + io_rw_32 ints1; + io_rw_32 timer[4]; + io_wo_32 multi_channel_trigger; + io_rw_32 sniff_ctrl; + io_rw_32 sniff_data; + uint32_t _pad2[1]; + io_ro_32 fifo_levels; + io_wo_32 abort; +} dma_hw_t; + +typedef struct { + struct dma_debug_hw_channel { + io_ro_32 ctrdeq; + io_ro_32 tcr; + uint32_t pad[14]; + } ch[NUM_DMA_CHANNELS]; +} dma_debug_hw_t; + +#define dma_hw ((dma_hw_t *const)DMA_BASE) +#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif |