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| author | Kevin O'Connor <kevin@koconnor.net> | 2021-05-04 10:09:29 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2021-05-04 20:29:48 -0400 |
| commit | 45cd3543e3154e8dfa8488fe6948689a6c07c389 (patch) | |
| tree | 3281358f5abc74a79d1f2f64666847b8b8ffc0ab /lib/lpc176x | |
| parent | 5fb5b3afe1fd568a0cb79706268b6a484c0aa850 (diff) | |
| download | kutter-45cd3543e3154e8dfa8488fe6948689a6c07c389.tar.gz kutter-45cd3543e3154e8dfa8488fe6948689a6c07c389.tar.xz kutter-45cd3543e3154e8dfa8488fe6948689a6c07c389.zip | |
lpc176x: Use full peripheral clock speed; fix UART interface
Commit ae89a659 caused a regression in the lpc176x UART handling.
After that commit the UART clock divisor would need to be 6.25 on
lpc1768 or 7.5 on lpc1769, but the code only supports whole numbers.
Set the PCLKSELx registers at startup and return to using full speed
peripheral clocks.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'lib/lpc176x')
| -rw-r--r-- | lib/lpc176x/device/system_LPC17xx.c | 4 | ||||
| -rw-r--r-- | lib/lpc176x/lpc176x.patch | 13 |
2 files changed, 11 insertions, 6 deletions
diff --git a/lib/lpc176x/device/system_LPC17xx.c b/lib/lpc176x/device/system_LPC17xx.c index c4e56121..eae33cbc 100644 --- a/lib/lpc176x/device/system_LPC17xx.c +++ b/lib/lpc176x/device/system_LPC17xx.c @@ -308,8 +308,8 @@ #define CCLKCFG_Val 0x00000002 #define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 +#define PCLKSEL0_Val 0x55515155 +#define PCLKSEL1_Val 0x54555455 #define PCONP_Val 0x042887DE #define CLKOUTCFG_Val 0x00000000 diff --git a/lib/lpc176x/lpc176x.patch b/lib/lpc176x/lpc176x.patch index 00babe91..4fe8c57a 100644 --- a/lib/lpc176x/lpc176x.patch +++ b/lib/lpc176x/lpc176x.patch @@ -1,6 +1,6 @@ --- device/system_LPC17xx.c 2018-05-02 12:23:57.292132454 -0400 -+++ device/system_LPC17xx.c 2018-05-23 20:09:29.681308483 -0400 -@@ -297,19 +297,16 @@ ++++ device/system_LPC17xx.c 2021-05-04 10:08:17.637502030 -0400 +@@ -297,22 +297,19 @@ #define CLKSRCSEL_Val 0x00000001 #define PLL0_SETUP 1 @@ -26,5 +26,10 @@ +#define CCLKCFG_Val 0x00000002 +#define USBCLKCFG_Val 0x00000000 - #define PCLKSEL0_Val 0x00000000 - #define PCLKSEL1_Val 0x00000000 +-#define PCLKSEL0_Val 0x00000000 +-#define PCLKSEL1_Val 0x00000000 ++#define PCLKSEL0_Val 0x55515155 ++#define PCLKSEL1_Val 0x54555455 + #define PCONP_Val 0x042887DE + #define CLKOUTCFG_Val 0x00000000 + |