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| author | Kevin O'Connor <kevin@koconnor.net> | 2019-07-21 20:29:14 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-07-21 22:40:56 -0400 |
| commit | 893acdb56bddbe8c24b51050187325f71e439798 (patch) | |
| tree | 705cd4b3422c83967a8e0b4533aee21b32ea3b3d /lib/hal-stm32f1/source | |
| parent | 17bd595b155304e9f1defa480f5eb7d8c060d9d6 (diff) | |
| download | kutter-893acdb56bddbe8c24b51050187325f71e439798.tar.gz kutter-893acdb56bddbe8c24b51050187325f71e439798.tar.xz kutter-893acdb56bddbe8c24b51050187325f71e439798.zip | |
lib: Update stm32f1 code to version 1.8.0
Update the stm32f1 code to the latest from ST. Merge the
lib/cmsis-stm32f1/ and lib/hal-stm32f1/ into a single lib/stm32f1/
directory. Document all the differences from the pristine upstream
code.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'lib/hal-stm32f1/source')
61 files changed, 0 insertions, 71561 deletions
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal.c b/lib/hal-stm32f1/source/stm32f1xx_hal.c deleted file mode 100644 index ad2f4b31..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal.c +++ /dev/null @@ -1,546 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief HAL module driver.
- * This is the common part of the HAL initialization
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The common HAL driver contains a set of generic and common APIs that can be
- used by the PPP peripheral drivers and the user to start using the HAL.
- [..]
- The HAL contains two APIs' categories:
- (+) Common HAL APIs
- (+) Services HAL APIs
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL HAL
- * @brief HAL module driver.
- * @{
- */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Constants HAL Private Constants
- * @{
- */
-/**
- * @brief STM32F1xx HAL Driver version number V1.1.1
- */
-#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
-#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
-#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
- |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
- |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
- |(__STM32F1xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK 0x00000FFFU
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-__IO uint32_t uwTick;
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
- * @{
- */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initializes the Flash interface, the NVIC allocation and initial clock
- configuration. It initializes the source of time base also when timeout
- is needed and the backup domain when enabled.
- (+) de-Initializes common part of the HAL.
- (+) Configure The time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) Systick timer is used by default as source of time base, but user
- can eventually implement his proper time base source (a general purpose
- timer for example or other time source), keeping in mind that Time base
- duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
- handled in milliseconds basis.
- (++) Time base configuration function (HAL_InitTick ()) is called automatically
- at the beginning of the program after reset by HAL_Init() or at any time
- when clock is configured, by HAL_RCC_ClockConfig().
- (++) Source of time base is configured to generate interrupts at regular
- time intervals. Care must be taken if HAL_Delay() is called from a
- peripheral ISR process, the Tick interrupt line must have higher priority
- (numerically lower) than the peripheral interrupt. Otherwise the caller
- ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __weak
- to make override possible in case of other implementations in user file.
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is used to initialize the HAL Library; it must be the first
- * instruction to be executed in the main program (before to call any other
- * HAL function), it performs the following:
- * Configure the Flash prefetch.
- * Configures the SysTick to generate an interrupt each 1 millisecond,
- * which is clocked by the HSI (at this stage, the clock is not yet
- * configured and thus the system is running from the internal HSI at 16 MHz).
- * Set NVIC Group Priority to 4.
- * Calls the HAL_MspInit() callback function defined in user file
- * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
- *
- * @note SysTick is used as time base for the HAL_Delay() function, the application
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- /* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0)
-#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
- defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
- /* Prefetch buffer is not available on value line devices */
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
-
- /* Init the low level hardware */
- HAL_MspInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief This function de-Initializes common part of the HAL and stops the source
- * of time base.
- * @note This function is optional.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
- /* Reset of all peripherals */
- __HAL_RCC_APB1_FORCE_RESET();
- __HAL_RCC_APB1_RELEASE_RESET();
-
- __HAL_RCC_APB2_FORCE_RESET();
- __HAL_RCC_APB2_RELEASE_RESET();
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- __HAL_RCC_AHB_FORCE_RESET();
- __HAL_RCC_AHB_RELEASE_RESET();
-#endif
-
- /* De-Init the low level hardware */
- HAL_MspDeInit();
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the MSP.
- * @retval None
- */
-__weak void HAL_MspInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the MSP.
- * @retval None
- */
-__weak void HAL_MspDeInit(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief This function configures the source of the time base.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
- * @note In the default implementation, SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals.
- * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
- * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __weak to be overwritten in case of other
- * implementation in user file.
- * @param TickPriority: Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- /*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(SystemCoreClock/1000U);
-
- /*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
-@verbatim
- ===============================================================================
- ##### HAL Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Provide a tick value in millisecond
- (+) Provide a blocking delay in millisecond
- (+) Suspend the time base source interrupt
- (+) Resume the time base source interrupt
- (+) Get the HAL API driver version
- (+) Get the device identifier
- (+) Get the device revision identifier
- (+) Enable/Disable Debug module during SLEEP mode
- (+) Enable/Disable Debug module during STOP mode
- (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function is called to increment a global variable "uwTick"
- * used as application time base.
- * @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- uwTick++;
-}
-
-/**
- * @brief Provides a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- return uwTick;
-}
-
-/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
- * @note In the default implementation , SysTick timer is the source of time base.
- * It is used to generate interrupts at regular time intervals where uwTick
- * is incremented.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @param Delay: specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(__IO uint32_t Delay)
-{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a period to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait++;
- }
-
- while((HAL_GetTick() - tickstart) < wait)
- {
- }
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-{
- /* Disable SysTick Interrupt */
- CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Returns the HAL revision
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
- */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32F1xx_HAL_VERSION;
-}
-
-/**
- * @brief Returns the device revision identifier.
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval Device revision identifier
- */
-uint32_t HAL_GetREVID(void)
-{
- return((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Returns the device identifier.
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval Device identifier
- */
-uint32_t HAL_GetDEVID(void)
-{
- return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * Note: On all STM32F1 devices:
- * If the system tick timer interrupt is enabled during the Stop mode
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
- * the system from Stop mode.
- * Workaround: To debug the Stop mode, disable the system tick timer
- * interrupt.
- * Refer to errata sheet of these devices for more details.
- * Note: On all STM32F1 devices:
- * If the system tick timer interrupt is enabled during the Stop mode
- * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
- * the system from Stop mode.
- * Workaround: To debug the Stop mode, disable the system tick timer
- * interrupt.
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Return the unique device identifier (UID based on 96 bits)
- * @param UID: pointer to 3 words array.
- * @retval Device identifier
- */
-void HAL_GetUID(uint32_t *UID)
-{
- UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
- UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
- UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_adc.c b/lib/hal-stm32f1/source/stm32f1xx_hal_adc.c deleted file mode 100644 index b72327d8..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_adc.c +++ /dev/null @@ -1,2112 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_adc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Channels configuration on injected group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
- * Other functions (extended functions) are available in file
- * "stm32f1xx_hal_adc_ex.c".
- *
- @verbatim
- ==============================================================================
- ##### ADC peripheral features #####
- ==============================================================================
- [..]
- (+) 12-bit resolution
-
- (+) Interrupt generation at the end of regular conversion, end of injected
- conversion, and in case of analog watchdog or overrun events.
-
- (+) Single and continuous conversion modes.
-
- (+) Scan mode for conversion of several channels sequentially.
-
- (+) Data alignment with in-built data coherency.
-
- (+) Programmable sampling time (channel wise)
-
- (+) ADC conversion of regular group and injected group.
-
- (+) External trigger (timer or EXTI)
- for both regular and injected groups.
-
- (+) DMA request generation for transfer of conversions data of regular group.
-
- (+) Multimode Dual mode (available on devices with 2 ADCs or more).
-
- (+) Configurable DMA data storage in Multimode Dual mode (available on devices
- with 2 DCs or more).
-
- (+) Configurable delay between conversions in Dual interleaved mode (available
- on devices with 2 DCs or more).
-
- (+) ADC calibration
-
- (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
- slower speed.
-
- (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
- Vdda or to an external voltage reference).
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- *** Configuration of top level parameters related to ADC ***
- ============================================================
- [..]
-
- (#) Enable the ADC interface
- (++) As prerequisite, ADC clock must be configured at RCC top level.
- Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
- to device datasheet).
- Therefore, ADC clock prescaler must be configured in
- function of ADC clock source frequency to remain below
- this maximum frequency.
- (++) One clock setting is mandatory:
- ADC clock (core clock, also possibly conversion clock).
- (+++) Example:
- Into HAL_ADC_MspInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit;
- (+++) __ADC1_CLK_ENABLE();
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Configure these ADC pins in analog mode
- using function HAL_GPIO_Init()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Configure the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding ADC interruption vector
- ADCx_IRQHandler().
-
- (#) Optionally, in case of usage of DMA:
- (++) Configure the DMA (DMA channel, mode normal or circular, ...)
- using function HAL_DMA_Init().
- (++) Configure the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
- (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
- into the function of corresponding DMA interruption vector
- DMAx_Channelx_IRQHandler().
-
- *** Configuration of ADC, groups regular/injected, channels parameters ***
- ==========================================================================
- [..]
-
- (#) Configure the ADC parameters (resolution, data alignment, ...)
- and regular group parameters (conversion trigger, sequencer, ...)
- using function HAL_ADC_Init().
-
- (#) Configure the channels for regular group parameters (channel number,
- channel rank into sequencer, ..., into regular group)
- using function HAL_ADC_ConfigChannel().
-
- (#) Optionally, configure the injected group parameters (conversion trigger,
- sequencer, ..., of injected group)
- and the channels for injected group parameters (channel number,
- channel rank into sequencer, ..., into injected group)
- using function HAL_ADCEx_InjectedConfigChannel().
-
- (#) Optionally, configure the analog watchdog parameters (channels
- monitored, thresholds, ...)
- using function HAL_ADC_AnalogWDGConfig().
-
- (#) Optionally, for devices with several ADC instances: configure the
- multimode parameters
- using function HAL_ADCEx_MultiModeConfigChannel().
-
- *** Execution of ADC conversions ***
- ====================================
- [..]
-
- (#) Optionally, perform an automatic ADC calibration to improve the
- conversion accuracy
- using function HAL_ADCEx_Calibration_Start().
-
- (#) ADC driver can be used among three modes: polling, interruption,
- transfer by DMA.
-
- (++) ADC conversion by polling:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start()
- (+++) Wait for ADC conversion completion
- using function HAL_ADC_PollForConversion()
- (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (or for injected group: HAL_ADCEx_InjectedGetValue() )
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop()
-
- (++) ADC conversion by interruption:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_IT()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback()
- (this function must be implemented in user program)
- (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
- (+++) Retrieve conversion results
- using function HAL_ADC_GetValue()
- (or for injected group: HAL_ADCEx_InjectedGetValue() )
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_IT()
-
- (++) ADC conversion with transfer by DMA:
- (+++) Activate the ADC peripheral and start conversions
- using function HAL_ADC_Start_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral
- using function HAL_ADC_Stop_DMA()
-
- (++) For devices with several ADCs: ADC multimode conversion
- with transfer by DMA:
- (+++) Activate the ADC peripheral (slave) and start conversions
- using function HAL_ADC_Start()
- (+++) Activate the ADC peripheral (master) and start conversions
- using function HAL_ADCEx_MultiModeStart_DMA()
- (+++) Wait for ADC conversion completion by call of function
- HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
- (these functions must be implemented in user program)
- (+++) Conversion results are automatically transferred by DMA into
- destination variable address.
- (+++) Stop conversion and disable the ADC peripheral (master)
- using function HAL_ADCEx_MultiModeStop_DMA()
- (+++) Stop conversion and disable the ADC peripheral (slave)
- using function HAL_ADC_Stop_IT()
-
- [..]
-
- (@) Callback functions must be implemented in user program:
- (+@) HAL_ADC_ErrorCallback()
- (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
- (+@) HAL_ADC_ConvCpltCallback()
- (+@) HAL_ADC_ConvHalfCpltCallback
- (+@) HAL_ADCEx_InjectedConvCpltCallback()
-
- *** Deinitialization of ADC ***
- ============================================================
- [..]
-
- (#) Disable the ADC interface
- (++) ADC clock can be hard reset and disabled at RCC top level.
- (++) Hard reset of ADC peripherals
- using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
- (++) ADC clock disable
- using the equivalent macro/functions as configuration step.
- (+++) Example:
- Into HAL_ADC_MspDeInit() (recommended code location) or with
- other device clock parameters configuration:
- (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
- (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
- (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
-
- (#) ADC pins configuration
- (++) Disable the clock for the ADC GPIOs
- using macro __HAL_RCC_GPIOx_CLK_DISABLE()
-
- (#) Optionally, in case of usage of ADC with interruptions:
- (++) Disable the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-
- (#) Optionally, in case of usage of DMA:
- (++) Deinitialize the DMA
- using function HAL_DMA_Init().
- (++) Disable the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-
- [..]
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADC ADC
- * @brief ADC HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
- /* Timeout values for ADC enable and disable settling time. */
- /* Values defined to be higher than worst cases: low clocks freq, */
- /* maximum prescaler. */
- /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
- /* Unit: ms */
- #define ADC_ENABLE_TIMEOUT 2U
- #define ADC_DISABLE_TIMEOUT 2U
-
- /* Delay for ADC stabilization time. */
- /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
- /* Unit: us */
- #define ADC_STAB_DELAY_US 1U
-
- /* Delay for temperature sensor stabilization time. */
- /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
- /* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US 10U
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC.
- (+) De-initialize the ADC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the ADC peripheral and regular group according to
- * parameters specified in structure "ADC_InitTypeDef".
- * @note As prerequisite, ADC clock must be configured at RCC top level
- * (clock source APB2).
- * See commented example code below that can be copied and uncommented
- * into HAL_ADC_MspInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
- * coming from ADC state reset. Following calls to this function can
- * be used to reconfigure some parameters of ADC_InitTypeDef
- * structure on the fly, without modifying MSP configuration. If ADC
- * MSP has to be modified again, HAL_ADC_DeInit() must be called
- * before HAL_ADC_Init().
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_InitTypeDef".
- * @note This function configures the ADC within 2 scopes: scope of entire
- * ADC and scope of regular group. For parameters details, see comments
- * of structure "ADC_InitTypeDef".
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmp_cr1 = 0U;
- uint32_t tmp_cr2 = 0U;
- uint32_t tmp_sqr1 = 0U;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
- assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
- if(hadc->Init.DiscontinuousConvMode != DISABLE)
- {
- assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
- }
- }
-
- /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
- /* at RCC top level. */
- /* Refer to header of this file for more details on clock enabling */
- /* procedure. */
-
- /* Actions performed only if ADC is coming from state reset: */
- /* - Initialization of ADC MSP */
- if (hadc->State == HAL_ADC_STATE_RESET)
- {
- /* Initialize ADC error code */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Allocate lock resource and initialize it */
- hadc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
- }
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- /* Note: In case of ADC already enabled, precaution to not launch an */
- /* unwanted conversion while modifying register CR2 by writing 1 to */
- /* bit ADON. */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
- (tmp_hal_status == HAL_OK) )
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Set ADC parameters */
-
- /* Configuration of ADC: */
- /* - data alignment */
- /* - external trigger to start conversion */
- /* - external trigger polarity (always set to 1, because needed for all */
- /* triggers: external trigger of SW start) */
- /* - continuous conversion mode */
- /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
- /* HAL_ADC_Start_xxx functions because if set in this function, */
- /* a conversion on injected group would start a conversion also on */
- /* regular group after ADC enabling. */
- tmp_cr2 |= (hadc->Init.DataAlign |
- ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
- ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
-
- /* Configuration of ADC: */
- /* - scan mode */
- /* - discontinuous mode disable/enable */
- /* - discontinuous mode number of conversions */
- tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
-
- /* Enable discontinuous mode only if continuous mode is disabled */
- /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
- /* discontinuous is set anyway, but will have no effect on ADC HW. */
- if (hadc->Init.DiscontinuousConvMode == ENABLE)
- {
- if (hadc->Init.ContinuousConvMode == DISABLE)
- {
- /* Enable the selected ADC regular discontinuous mode */
- /* Set the number of channels to be converted in discontinuous mode */
- SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
- ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
- }
- else
- {
- /* ADC regular group settings continuous and sequencer discontinuous*/
- /* cannot be enabled simultaneously. */
-
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- }
- }
-
- /* Update ADC configuration register CR1 with previous settings */
- MODIFY_REG(hadc->Instance->CR1,
- ADC_CR1_SCAN |
- ADC_CR1_DISCEN |
- ADC_CR1_DISCNUM ,
- tmp_cr1 );
-
- /* Update ADC configuration register CR2 with previous settings */
- MODIFY_REG(hadc->Instance->CR2,
- ADC_CR2_ALIGN |
- ADC_CR2_EXTSEL |
- ADC_CR2_EXTTRIG |
- ADC_CR2_CONT ,
- tmp_cr2 );
-
- /* Configuration of regular group sequencer: */
- /* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
- /* Parameter "NbrOfConversion" is discarded. */
- /* Note: Scan mode is present by hardware on this device and, if */
- /* disabled, discards automatically nb of conversions. Anyway, nb of */
- /* conversions is forced to 0x00 for alignment over all STM32 devices. */
- /* - if scan mode is enabled, regular channels sequence length is set to */
- /* parameter "NbrOfConversion" */
- if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
- {
- tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
- }
-
- MODIFY_REG(hadc->Instance->SQR1,
- ADC_SQR1_L ,
- tmp_sqr1 );
-
- /* Check back that ADC registers have effectively been configured to */
- /* ensure of no potential problem of ADC core IP clocking. */
- /* Check through register CR2 (excluding bits set in other functions: */
- /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
- /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
- /* measurement path bit (TSVREFE). */
- if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
- ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
- ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
- ADC_CR2_TSVREFE ))
- == tmp_cr2)
- {
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set the ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Deinitialize the ADC peripheral registers to their default reset
- * values, with deinitialization of the ADC MSP.
- * If needed, the example code can be copied and uncommented into
- * function HAL_ADC_MspDeInit().
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check ADC handle */
- if(hadc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
-
- /* Configuration of ADC parameters if previous preliminary actions are */
- /* correctly completed. */
- if (tmp_hal_status == HAL_OK)
- {
- /* ========== Reset ADC registers ========== */
-
-
-
-
- /* Reset register SR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
- ADC_FLAG_JSTRT | ADC_FLAG_STRT));
-
- /* Reset register CR1 */
- CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
- ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
- ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
- ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
-
- /* Reset register CR2 */
- CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
- ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
- ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
- ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
- ADC_CR2_ADON ));
-
- /* Reset register SMPR1 */
- CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
- ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
- ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
-
- /* Reset register SMPR2 */
- CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
- ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
- ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
- ADC_SMPR2_SMP0 ));
-
- /* Reset register JOFR1 */
- CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
- /* Reset register JOFR2 */
- CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
- /* Reset register JOFR3 */
- CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
- /* Reset register JOFR4 */
- CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
-
- /* Reset register HTR */
- CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
- /* Reset register LTR */
- CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
- ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
- ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
-
- /* Reset register SQR1 */
- CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
- ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
- ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
-
- /* Reset register SQR2 */
- CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
- ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
-
- /* Reset register SQR3 */
- CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
- ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
-
- /* Reset register JSQR */
- CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
- ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
-
- /* Reset register JSQR */
- CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
- ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable*/
-
- /* ========== Hard reset ADC peripheral ========== */
- /* Performs a global reset of the entire ADC peripheral: ADC state is */
- /* forced to a similar state after device power-on. */
- /* If needed, copy-paste and uncomment the following reset code into */
- /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
- /* */
- /* __HAL_RCC_ADC1_FORCE_RESET() */
- /* __HAL_RCC_ADC1_RELEASE_RESET() */
-
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
- /* Set ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
-
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Initializes the ADC MSP.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspInit must be implemented in the user file.
- */
-}
-
-/**
- * @brief DeInitializes the ADC MSP.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_MspDeInit must be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of regular group.
- (+) Stop conversion of regular group.
- (+) Poll for conversion complete on regular group.
- (+) Poll for conversion event.
- (+) Get result of regular channel conversion.
- (+) Start conversion of regular group and enable interruptions.
- (+) Stop conversion of regular group and disable interruptions.
- (+) Handle ADC interrupt request
- (+) Start conversion of regular group and enable DMA transfer.
- (+) Stop conversion of regular group and disable ADC DMA transfer.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables ADC, starts conversion of regular group.
- * Interruptions enabled in this function: None.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled: */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- /* If ADC is master, ADC is enabled and conversion is started. */
- /* Note: Alternate trigger for single conversion could be to force an */
- /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Wait for regular group conversion to be completed.
- * @note This function cannot be used in a particular setup: ADC configured
- * in DMA mode.
- * In this case, DMA resets the flag EOC and polling cannot be
- * performed on each conversion.
- * @note On STM32F1 devices, limitation in case of sequencer enabled
- * (several ranks selected): polling cannot be done on each
- * conversion inside the sequence. In this case, polling is replaced by
- * wait for maximum conversion time.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Variables for polling in case of scan mode enabled and polling for each */
- /* conversion. */
- __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
- uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Verification that ADC configuration is compliant with polling for */
- /* each conversion: */
- /* Particular case is ADC configured in DMA mode */
- if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Polling for end of conversion: differentiation if single/sequence */
- /* conversion. */
- /* - If single conversion for regular group (Scan mode disabled or enabled */
- /* with NbrOfConversion =1), flag EOC is used to determine the */
- /* conversion completion. */
- /* - If sequence conversion for regular group (scan mode enabled and */
- /* NbrOfConversion >=2), flag EOC is set only at the end of the */
- /* sequence. */
- /* To poll for each conversion, the maximum conversion time is computed */
- /* from ADC conversion time (selected sampling time + conversion time of */
- /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
- /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
- /* As flag EOC is not set after each conversion, no timeout status can */
- /* be set. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
- HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
- {
- /* Wait until End of Conversion flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* Replace polling by wait for maximum conversion time */
- /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
- /* and ADC maximum conversion cycles on all channels. */
- /* - Wait for the expected ADC clock cycles delay */
- Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
- / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
- * ADC_CONVCYCLES_MAX_RANGE(hadc) );
-
- while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- Conversion_Timeout_CPU_cycles ++;
- }
- }
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F1 devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-
-/**
- * @brief Poll for conversion event.
- * @param hadc: ADC handle
- * @param EventType: the ADC event type.
- * This parameter can be one of the following values:
- * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
- * @param Timeout: Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EVENT_TYPE(EventType));
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Check selected event flag */
- while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Analog watchdog (level out of window) event */
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Clear ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-
- /* Return ADC state */
- return HAL_OK;
-}
-
-/**
- * @brief Enables ADC, starts conversion of regular group with interruption.
- * Interruptions enabled in this function:
- * - EOC (end of conversion of regular group)
- * Each of these interruptions has its dedicated callback function.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable end of conversion interrupt for regular group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Case of multimode enabled: */
- /* - if ADC is slave, ADC is enabled only (conversion is not started). */
- /* - if ADC is master, ADC is enabled and conversion is started. */
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable interrution of
- * end-of-conversion, disable ADC peripheral.
- * @param hadc: ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * Each of these interruptions has its dedicated callback function.
- * @note For devices with several ADCs: This function is for single-ADC mode
- * only. For multimode, use the dedicated MultimodeStart function.
- * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
- * on devices) have DMA capability.
- * ADC2 converted data can be transferred in dual ADC mode using DMA
- * of ADC1 (ADC master in multimode).
- * In case of using ADC1 with DMA on a device featuring 2 ADC
- * instances: ADC1 conversion register DR contains ADC1 conversion
- * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
- * conversion result (ADC1 register DR bits 16 to 27). Therefore, to
- * have DMA transferring the conversion results of ADC1 only, DMA must
- * be configured to transfer size: half word.
- * @param hadc: ADC handle
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
-
- /* Verification if multimode is disabled (for devices with several ADC) */
- /* If multimode is enabled, dedicated function multimode conversion */
- /* start DMA must be used. */
- if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
- {
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
- HAL_ADC_STATE_REG_BUSY);
-
- /* Set group injected state (from auto-injection) and multimode state */
- /* for all cases of multimode: independent mode, multimode ADC master */
- /* or multimode ADC slave (for devices with several ADCs): */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- /* Set ADC state (ADC independent or master) */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
- else
- {
- /* Set ADC state (ADC slave) */
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
- }
-
- /* State machine update: Check if an injected conversion is ongoing */
- if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- /* Reset ADC error code fields related to conversions on group regular */
- CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
- }
- else
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC */
- /* operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable ADC DMA mode */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Enable conversion of regular group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
- }
- else
- {
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected group in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note: ADC peripheral disable is forcing stop of potential
- * conversion on injected group. If injected group is under use, it
- * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @note For devices with several ADCs: This function is for single-ADC mode
- * only. For multimode, use the dedicated MultimodeStop function.
- * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
- * on devices) have DMA capability.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC DMA mode */
- CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Get ADC regular group conversion result.
- * @note Reading register DR automatically clears ADC flag EOC
- * (ADC group regular end of unitary conversion).
- * @note This function does not clear ADC flag EOS
- * (ADC group regular end of sequence conversion).
- * Occurrence of flag EOS rising:
- * - If sequencer is composed of 1 rank, flag EOS is equivalent
- * to flag EOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag EOC only is raised, at the end of the scan sequence
- * both flags EOC and EOS are raised.
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADC_PollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc: ADC handle
- * @retval ADC group regular conversion data
- */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: EOC flag is not cleared here by software because automatically */
- /* cleared by hardware when reading register DR. */
-
- /* Return ADC converted value */
- return hadc->Instance->DR;
-}
-
-/**
- * @brief Handles ADC interrupt request
- * @param hadc: ADC handle
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
- assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-
-
- /* ========== Check End of Conversion flag for regular group ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
- }
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F1 devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Disable ADC end of conversion interrupt on group regular */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
-
- /* Clear regular group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
- }
- }
-
- /* ========== Check End of Conversion flag for injected group ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
- {
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
- }
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger, scan sequence on going or by automatic injected */
- /* conversion from group regular (same conditions as group regular */
- /* interruption disabling above). */
- /* Note: On STM32F1 devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
- {
- /* Disable ADC end of conversion interrupt on group injected */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
-
- /* Clear injected group conversion flag */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
- }
- }
-
- /* ========== Check Analog watchdog flags ========== */
- if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
- {
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
- {
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
-
- /* Level out of window callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
-
- /* Clear the ADC analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
- }
- }
-
-}
-
-/**
- * @brief Conversion complete callback in non blocking mode
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Conversion DMA half-transfer callback in non blocking mode
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief Analog watchdog callback in non blocking mode.
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
- */
-}
-
-/**
- * @brief ADC error callback in non blocking mode
- * (ADC conversion with interruption or transfer by DMA)
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function should not be modified. When the callback is needed,
- function HAL_ADC_ErrorCallback must be implemented in the user file.
- */
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on regular group
- (+) Configure the analog watchdog
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the the selected channel to be linked to the regular
- * group.
- * @note In case of usage of internal measurement channels:
- * Vbat/VrefInt/TempSensor.
- * These internal paths can be be disabled using function
- * HAL_ADC_DeInit().
- * @note Possibility to update parameters on the fly:
- * This function initializes channel into regular group, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
- * the ADC.
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_ChannelConfTypeDef".
- * @param hadc: ADC handle
- * @param sConfig: Structure of ADC channel for regular group.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CHANNEL(sConfig->Channel));
- assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* Regular sequence configuration */
- /* For Rank 1 to 6 */
- if (sConfig->Rank < 7U)
- {
- MODIFY_REG(hadc->Instance->SQR3 ,
- ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
- ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 7 to 12 */
- else if (sConfig->Rank < 13U)
- {
- MODIFY_REG(hadc->Instance->SQR2 ,
- ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
- ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
- }
- /* For Rank 13 to 16 */
- else
- {
- MODIFY_REG(hadc->Instance->SQR1 ,
- ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
- ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
- }
-
-
- /* Channel sampling time configuration */
- /* For channels 10 to 17 */
- if (sConfig->Channel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR1 ,
- ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
- }
- else /* For channels 0 to 9 */
- {
- MODIFY_REG(hadc->Instance->SMPR2 ,
- ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
- }
-
- /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
- /* and VREFINT measurement path. */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
- (sConfig->Channel == ADC_CHANNEL_VREFINT) )
- {
- /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
- /* measurement channels (VrefInt/TempSensor). If these channels are */
- /* intended to be set on other ADC instances, an error is reported. */
- if (hadc->Instance == ADC1)
- {
- if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
- {
- SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
-
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
- {
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Configures the analog watchdog.
- * @note Analog watchdog thresholds can be modified while ADC conversion
- * is on going.
- * In this case, some constraints must be taken into account:
- * the programmed threshold values are effective from the next
- * ADC EOC (end of unitary conversion).
- * Considering that registers write delay may happen due to
- * bus activity, this might cause an uncertainty on the
- * effective timing of the new programmed threshold values.
- * @param hadc: ADC handle
- * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
- assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
- assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
-
- if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
- (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
- {
- assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Analog watchdog configuration */
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- /* Enable the ADC Analog watchdog interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
- }
- else
- {
- /* Disable the ADC Analog watchdog interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
- }
-
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog enable mode: regular and/or injected groups, */
- /* one or all channels. */
- /* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
- MODIFY_REG(hadc->Instance->CR1 ,
- ADC_CR1_AWDSGL |
- ADC_CR1_JAWDEN |
- ADC_CR1_AWDEN |
- ADC_CR1_AWDCH ,
- AnalogWDGConfig->WatchdogMode |
- AnalogWDGConfig->Channel );
-
- /* Set the high threshold */
- WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
-
- /* Set the low threshold */
- WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions to get in run-time the status of the
- peripheral.
- (+) Check the ADC state
- (+) Check the ADC error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the ADC state
- * @param hadc: ADC handle
- * @retval HAL state
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
- /* Return ADC state */
- return hadc->State;
-}
-
-/**
- * @brief Return the ADC error code
- * @param hadc: ADC handle
- * @retval ADC Error Code
- */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
- return hadc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-
-/**
- * @brief Enable the selected ADC.
- * @note Prerequisite condition to use this function: ADC must be disabled
- * and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
- __IO uint32_t wait_loop_index = 0U;
-
- /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
- /* enabling phase not yet completed: flag ADC ready not yet set). */
- /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
- /* causes: ADC clock not running, ...). */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- /* Enable the Peripheral */
- __HAL_ADC_ENABLE(hadc);
-
- /* Delay for ADC stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait for ADC effectively enabled */
- while(ADC_IS_ENABLE(hadc) == RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop ADC conversion and disable the selected ADC
- * @note Prerequisite condition to use this function: ADC conversions must be
- * stopped to disable the ADC.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
-{
- uint32_t tickstart = 0U;
-
- /* Verification if ADC is not already disabled */
- if (ADC_IS_ENABLE(hadc) != RESET)
- {
- /* Disable the ADC peripheral */
- __HAL_ADC_DISABLE(hadc);
-
- /* Get tick count */
- tickstart = HAL_GetTick();
-
- /* Wait for ADC effectively disabled */
- while(ADC_IS_ENABLE(hadc) != RESET)
- {
- if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Set ADC error code to ADC IP internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
- return HAL_ERROR;
- }
- }
- }
-
- /* Return HAL status */
- return HAL_OK;
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update state machine on conversion status if not in error state */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
- {
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
-
- /* Determine whether any further conversion upcoming on group regular */
- /* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F1 devices, in case of sequencer enabled */
- /* (several ranks selected), end of conversion flag is raised */
- /* at the end of the sequence. */
- if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
- }
- else
- {
- /* Call DMA error callback */
- hadc->DMA_Handle->XferErrorCallback(hdma);
- }
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Half conversion callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set ADC state */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
- /* Set ADC error code to DMA error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_adc_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_adc_ex.c deleted file mode 100644 index 2df1e0bb..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_adc_ex.c +++ /dev/null @@ -1,1341 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_adc_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
- * peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of injected
- * group, using 2 possible modes: polling, interruption.
- * ++ Multimode feature (available on devices with 2 ADCs or more)
- * ++ Calibration (ADC automatic self-calibration)
- * + Control functions
- * ++ Channels configuration on injected group
- * Other functions (generic functions) are available in file
- * "stm32f1xx_hal_adc.c".
- *
- @verbatim
- [..]
- (@) Sections "ADC peripheral features" and "How to use this driver" are
- available in file of generic functions "stm32f1xx_hal_adc.c".
- [..]
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup ADCEx ADCEx
- * @brief ADC Extension HAL module driver
- * @{
- */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
- * @{
- */
-
- /* Delay for ADC calibration: */
- /* Hardware prerequisite before starting a calibration: the ADC must have */
- /* been in power-on state for at least two ADC clock cycles. */
- /* Unit: ADC clock cycles */
- #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U
-
- /* Timeout value for ADC calibration */
- /* Value defined to be higher than worst cases: low clocks freq, */
- /* maximum prescaler. */
- /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
- /* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT 10U
-
- /* Delay for temperature sensor stabilization time. */
- /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
- /* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US 10U
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
- * @{
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
- * @brief Extended Extended Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion of injected group.
- (+) Stop conversion of injected group.
- (+) Poll for conversion complete on injected group.
- (+) Get result of injected channel conversion.
- (+) Start conversion of injected group and enable interruptions.
- (+) Stop conversion of injected group and disable interruptions.
-
- (+) Start multimode and enable DMA transfer.
- (+) Stop multimode and disable ADC DMA transfer.
- (+) Get result of multimode conversion.
-
- (+) Perform the ADC self-calibration for single or differential ending.
- (+) Get calibration factors for single or differential ending.
- (+) Set calibration factors for single or differential ending.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform an ADC automatic self-calibration
- * Calibration prerequisite: ADC must be disabled (execute this
- * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * During calibration process, ADC is enabled. ADC is let enabled at
- * the completion of this function.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tickstart;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* 1. Calibration prerequisite: */
- /* - ADC must be disabled for at least two ADC clock cycles in disable */
- /* mode before ADC enable */
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_BUSY_INTERNAL);
-
- /* Hardware prerequisite: delay before starting the calibration. */
- /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
- /* - Wait for the expected ADC clock cycles delay */
- wait_loop_index = ((SystemCoreClock
- / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
- * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
-
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
-
- /* 2. Enable the ADC peripheral */
- ADC_Enable(hadc);
-
- /* 3. Resets ADC calibration registers */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
-
- tickstart = HAL_GetTick();
-
- /* Wait for calibration reset completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
- {
- if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
-
- /* 4. Start ADC calibration */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
-
- tickstart = HAL_GetTick();
-
- /* Wait for calibration completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
- {
- if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_BUSY_INTERNAL,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Enables ADC, starts conversion of injected group.
- * Interruptions enabled in this function: None.
- * @param hadc: ADC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Case of independent mode or multimode (for devices with several ADCs): */
- /* Set multimode state. */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
- /* Enable conversion of injected group. */
- /* If software start has been selected, conversion starts immediately. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If automatic injected conversion is enabled, conversion will start */
- /* after next regular group conversion. */
- /* Case of multimode enabled (for devices with several ADCs): if ADC is */
- /* slave, ADC is enabled only (conversion is not started). If ADC is */
- /* master, ADC is enabled and conversion is started. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
- {
- if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
- ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
- {
- /* Start ADC conversion on injected group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
- }
- else
- {
- /* Start ADC conversion on injected group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
- }
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop conversion of injected channels. Disable ADC peripheral if
- * no regular conversion is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc: ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion and disable ADC peripheral */
- /* Conditioned to: */
- /* - No conversion on the other group (regular group) is intended to */
- /* continue (injected and regular groups stop conversion and ADC disable */
- /* are common) */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Wait for injected group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
- uint32_t tickstart;
-
- /* Variables for polling in case of scan mode enabled and polling for each */
- /* conversion. */
- __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
- uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Polling for end of conversion: differentiation if single/sequence */
- /* conversion. */
- /* For injected group, flag JEOC is set only at the end of the sequence, */
- /* not for each conversion within the sequence. */
- /* - If single conversion for injected group (scan mode disabled or */
- /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
- /* conversion completion. */
- /* - If sequence conversion for injected group (scan mode enabled and */
- /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
- /* sequence. */
- /* To poll for each conversion, the maximum conversion time is computed */
- /* from ADC conversion time (selected sampling time + conversion time of */
- /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
- /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
- /* As flag JEOC is not set after each conversion, no timeout status can */
- /* be set. */
- if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
- {
- /* Wait until End of Conversion flag is raised */
- while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- /* Replace polling by wait for maximum conversion time */
- /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
- /* and ADC maximum conversion cycles on all channels. */
- /* - Wait for the expected ADC clock cycles delay */
- Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
- / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
- * ADC_CONVCYCLES_MAX_RANGE(hadc) );
-
- while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
- {
- /* Check if timeout is disabled (set to infinite wait) */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- Conversion_Timeout_CPU_cycles ++;
- }
- }
-
- /* Clear injected group conversion flag */
- /* Note: On STM32F1 ADC, clear regular conversion flag raised */
- /* simultaneously. */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
-
- /* Update ADC state machine */
- SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
-
- /* Determine whether any further conversion upcoming on group injected */
- /* by external trigger or by automatic injected conversion */
- /* from group regular. */
- if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
- (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
- (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
- {
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
-
- /* Return ADC state */
- return HAL_OK;
-}
-
-/**
- * @brief Enables ADC, starts conversion of injected group with interruption.
- * - JEOC (end of conversion of injected group)
- * Each of these interruptions has its dedicated callback function.
- * @param hadc: ADC handle
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Enable the ADC peripheral */
- tmp_hal_status = ADC_Enable(hadc);
-
- /* Start conversion if ADC is effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state */
- /* - Clear state bitfield related to injected group conversion results */
- /* - Set state bitfield related to injected operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
- HAL_ADC_STATE_INJ_BUSY);
-
- /* Case of independent mode or multimode (for devices with several ADCs): */
- /* Set multimode state. */
- if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
- {
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
- else
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
- }
-
- /* Check if a regular conversion is ongoing */
- /* Note: On this device, there is no ADC error code fields related to */
- /* conversions on group injected only. In case of conversion on */
- /* going on group regular, no error code is reset. */
- if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
- {
- /* Reset ADC all error code fields */
- ADC_CLEAR_ERRORCODE(hadc);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Clear injected group conversion flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-
- /* Enable end of conversion interrupt for injected channels */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Start conversion of injected group if software start has been selected */
- /* and if automatic injected conversion is disabled. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* If automatic injected conversion is enabled, conversion will start */
- /* after next regular group conversion. */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
- {
- if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
- ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
- {
- /* Start ADC conversion on injected group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
- }
- else
- {
- /* Start ADC conversion on injected group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
- }
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop conversion of injected channels, disable interruption of
- * end-of-conversion. Disable ADC peripheral if no regular conversion
- * is on going.
- * @note If ADC must be disabled and if conversion is on going on
- * regular group, function HAL_ADC_Stop must be used to stop both
- * injected and regular groups, and disable the ADC.
- * @note If injected group mode auto-injection is enabled,
- * function HAL_ADC_Stop must be used.
- * @param hadc: ADC handle
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Stop potential conversion and disable ADC peripheral */
- /* Conditioned to: */
- /* - No conversion on the other group (regular group) is intended to */
- /* continue (injected and regular groups stop conversion and ADC disable */
- /* are common) */
- /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
- if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
- HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
- {
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Disable ADC end of conversion interrupt for injected channels */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-
- /* Set ADC state */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
- * @brief Enables ADC, starts conversion of regular group and transfers result
- * through DMA.
- * Multimode must have been previously configured using
- * HAL_ADCEx_MultiModeConfigChannel() function.
- * Interruptions enabled in this function:
- * - DMA transfer complete
- * - DMA half transfer
- * Each of these interruptions has its dedicated callback function.
- * @note: On STM32F1 devices, ADC slave regular group must be configured
- * with conversion trigger ADC_SOFTWARE_START.
- * @note: ADC slave can be enabled preliminarily using single-mode
- * HAL_ADC_Start() function.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- /* On STM32F1 devices, ADC slave regular group must be configured with */
- /* conversion trigger ADC_SOFTWARE_START. */
- /* Note: External trigger of ADC slave must be enabled, it is already done */
- /* into function "HAL_ADC_Init()". */
- if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Enable the ADC peripherals: master and slave (in case if not already */
- /* enabled previously) */
- tmp_hal_status = ADC_Enable(hadc);
- if (tmp_hal_status == HAL_OK)
- {
- tmp_hal_status = ADC_Enable(&tmphadcSlave);
- }
-
- /* Start conversion if all ADCs of multimode are effectively enabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Set ADC state (ADC master) */
- /* - Clear state bitfield related to regular group conversion results */
- /* - Set state bitfield related to regular operation */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
- HAL_ADC_STATE_REG_BUSY);
-
- /* If conversions on group regular are also triggering group injected, */
- /* update ADC state. */
- if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
- {
- ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
- }
-
- /* Process unlocked */
- /* Unlock before starting ADC conversions: in case of potential */
- /* interruption, to let the process to ADC IRQ Handler. */
- __HAL_UNLOCK(hadc);
-
- /* Set ADC error code to none */
- ADC_CLEAR_ERRORCODE(hadc);
-
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
- /* start (in case of SW start): */
-
- /* Clear regular group conversion flag and overrun flag */
- /* (To ensure of no unknown state from potential previous ADC operations) */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
- /* Enable ADC DMA mode of ADC master */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
-
- /* Start the DMA channel */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Start conversion of regular group if software start has been selected. */
- /* If external trigger has been selected, conversion will start at next */
- /* trigger event. */
- /* Note: Alternate trigger for single conversion could be to force an */
- /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
- if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
- {
- /* Start ADC conversion on regular group with SW start */
- SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
- }
- else
- {
- /* Start ADC conversion on regular group with external trigger */
- SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
- }
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- }
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-/**
- * @brief Stop ADC conversion of regular group (and injected channels in
- * case of auto_injection mode), disable ADC DMA transfer, disable
- * ADC peripheral.
- * @note Multimode is kept enabled after this function. To disable multimode
- * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
- * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
- * @note In case of DMA configured in circular mode, function
- * HAL_ADC_Stop_DMA must be called after this function with handle of
- * ADC slave, to properly disable the DMA channel.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
- /* Stop potential conversion on going, on regular and injected groups */
- /* Disable ADC master peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if(tmp_hal_status == HAL_OK)
- {
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- /* Disable ADC slave peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
-
- /* Check if ADC is effectively disabled */
- if(tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Disable ADC DMA mode */
- CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
-
- /* Reset configuration of ADC DMA continuous request for dual mode */
- CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
-
- /* Disable the DMA channel (in case of DMA in circular mode or stop while */
- /* while DMA transfer is on going) */
- tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
- /* Change ADC state (ADC master) */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @brief Get ADC injected group conversion result.
- * @note Reading register JDRx automatically clears ADC flag JEOC
- * (ADC group injected end of unitary conversion).
- * @note This function does not clear ADC flag JEOS
- * (ADC group injected end of sequence conversion)
- * Occurrence of flag JEOS rising:
- * - If sequencer is composed of 1 rank, flag JEOS is equivalent
- * to flag JEOC.
- * - If sequencer is composed of several ranks, during the scan
- * sequence flag JEOC only is raised, at the end of the scan sequence
- * both flags JEOC and EOS are raised.
- * Flag JEOS must not be cleared by this function because
- * it would not be compliant with low power features
- * (feature low power auto-wait, not available on all STM32 families).
- * To clear this flag, either use function:
- * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
- * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
- * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc: ADC handle
- * @param InjectedRank: the converted ADC injected rank.
- * This parameter can be one of the following values:
- * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
- * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
- * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
- * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
- * @retval ADC group injected conversion data
- */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
- uint32_t tmp_jdr = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-
- /* Get ADC converted value */
- switch(InjectedRank)
- {
- case ADC_INJECTED_RANK_4:
- tmp_jdr = hadc->Instance->JDR4;
- break;
- case ADC_INJECTED_RANK_3:
- tmp_jdr = hadc->Instance->JDR3;
- break;
- case ADC_INJECTED_RANK_2:
- tmp_jdr = hadc->Instance->JDR2;
- break;
- case ADC_INJECTED_RANK_1:
- default:
- tmp_jdr = hadc->Instance->JDR1;
- break;
- }
-
- /* Return ADC converted value */
- return tmp_jdr;
-}
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
- * @brief Returns the last ADC Master&Slave regular conversions results data
- * in the selected multi mode.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @retval The converted data value.
- */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
-{
- uint32_t tmpDR = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
- /* Note: EOC flag is not cleared here by software because automatically */
- /* cleared by hardware when reading register DR. */
-
- /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */
- /* only if ADC1 DMA mode is enabled. */
- tmpDR = hadc->Instance->DR;
-
- if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
- {
- tmpDR |= (ADC2->DR << 16U);
- }
-
- /* Return ADC converted value */
- return tmpDR;
-}
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @brief Injected conversion complete callback in non blocking mode
- * @param hadc: ADC handle
- * @retval None
- */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hadc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels on injected group
- (+) Configure multimode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the ADC injected group and the selected channel to be
- * linked to the injected group.
- * @note Possibility to update parameters on the fly:
- * This function initializes injected group, following calls to this
- * function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
- * The setting of these parameters is conditioned to ADC state:
- * this function must be called when ADC is not under conversion.
- * @param hadc: ADC handle
- * @param sConfigInjected: Structure of ADC injected group and ADC channel for
- * injected group.
- * @retval None
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0U;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
- assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
- assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
-
- if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
- {
- assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
- assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
- assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
- }
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Configuration of injected group sequencer: */
- /* - if scan mode is disabled, injected channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
- /* Parameter "InjectedNbrOfConversion" is discarded. */
- /* Note: Scan mode is present by hardware on this device and, if */
- /* disabled, discards automatically nb of conversions. Anyway, nb of */
- /* conversions is forced to 0x00 for alignment over all STM32 devices. */
- /* - if scan mode is enabled, injected channels sequence length is set to */
- /* parameter "InjectedNbrOfConversion". */
- if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
- {
- if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
- {
- /* Clear the old SQx bits for all injected ranks */
- MODIFY_REG(hadc->Instance->JSQR ,
- ADC_JSQR_JL |
- ADC_JSQR_JSQ4 |
- ADC_JSQR_JSQ3 |
- ADC_JSQR_JSQ2 |
- ADC_JSQR_JSQ1 ,
- ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
- ADC_INJECTED_RANK_1,
- 0x01U));
- }
- /* If another injected rank than rank1 was intended to be set, and could */
- /* not due to ScanConvMode disabled, error is reported. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
- else
- {
- /* Since injected channels rank conv. order depends on total number of */
- /* injected conversions, selected rank must be below or equal to total */
- /* number of injected conversions to be updated. */
- if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
- {
- /* Clear the old SQx bits for the selected rank */
- /* Set the SQx bits for the selected rank */
- MODIFY_REG(hadc->Instance->JSQR ,
-
- ADC_JSQR_JL |
- ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) ,
-
- ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
- ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) );
- }
- else
- {
- /* Clear the old SQx bits for the selected rank */
- MODIFY_REG(hadc->Instance->JSQR ,
-
- ADC_JSQR_JL |
- ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
- sConfigInjected->InjectedRank,
- sConfigInjected->InjectedNbrOfConversion) ,
-
- 0x00000000U);
- }
- }
-
- /* Configuration of injected group */
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - external trigger to start conversion */
- /* Parameters update not conditioned to ADC state: */
- /* - Automatic injected conversion */
- /* - Injected discontinuous mode */
- /* Note: In case of ADC already enabled, caution to not launch an unwanted */
- /* conversion while modifying register CR2 by writing 1 to bit ADON. */
- if (ADC_IS_ENABLE(hadc) == RESET)
- {
- MODIFY_REG(hadc->Instance->CR2 ,
- ADC_CR2_JEXTSEL |
- ADC_CR2_ADON ,
- ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
- }
-
-
- /* Configuration of injected group */
- /* - Automatic injected conversion */
- /* - Injected discontinuous mode */
-
- /* Automatic injected conversion can be enabled if injected group */
- /* external triggers are disabled. */
- if (sConfigInjected->AutoInjectedConv == ENABLE)
- {
- if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
- {
- SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- /* Injected discontinuous can be enabled only if auto-injected mode is */
- /* disabled. */
- if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
- {
- if (sConfigInjected->AutoInjectedConv == DISABLE)
- {
- SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
-
- /* InjectedChannel sampling time configuration */
- /* For channels 10 to 17 */
- if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
- {
- MODIFY_REG(hadc->Instance->SMPR1 ,
- ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) ,
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
- else /* For channels 0 to 9 */
- {
- MODIFY_REG(hadc->Instance->SMPR2 ,
- ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) ,
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
- }
-
- /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */
- /* and VREFINT measurement path. */
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
- (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
- {
- SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
- }
-
-
- /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
- switch(sConfigInjected->InjectedRank)
- {
- case 1:
- /* Set injected channel 1 offset */
- MODIFY_REG(hadc->Instance->JOFR1,
- ADC_JOFR1_JOFFSET1,
- sConfigInjected->InjectedOffset);
- break;
- case 2:
- /* Set injected channel 2 offset */
- MODIFY_REG(hadc->Instance->JOFR2,
- ADC_JOFR2_JOFFSET2,
- sConfigInjected->InjectedOffset);
- break;
- case 3:
- /* Set injected channel 3 offset */
- MODIFY_REG(hadc->Instance->JOFR3,
- ADC_JOFR3_JOFFSET3,
- sConfigInjected->InjectedOffset);
- break;
- case 4:
- default:
- MODIFY_REG(hadc->Instance->JOFR4,
- ADC_JOFR4_JOFFSET4,
- sConfigInjected->InjectedOffset);
- break;
- }
-
- /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
- /* and VREFINT measurement path. */
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
- (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
- {
- /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
- /* measurement channels (VrefInt/TempSensor). If these channels are */
- /* intended to be set on other ADC instances, an error is reported. */
- if (hadc->Instance == ADC1)
- {
- if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
- {
- SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
-
- if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
- {
- /* Delay for temperature sensor stabilization time */
- /* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
- while(wait_loop_index != 0U)
- {
- wait_loop_index--;
- }
- }
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
- * @brief Enable ADC multimode and configure multimode parameters
- * @note Possibility to update parameters on the fly:
- * This function initializes multimode parameters, following
- * calls to this function can be used to reconfigure some parameters
- * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
- * the ADCs (both ADCs of the common group).
- * The setting of these parameters is conditioned to ADC state.
- * For parameters constraints, see comments of structure
- * "ADC_MultiModeTypeDef".
- * @note To change back configuration from multimode to single mode, ADC must
- * be reset (using function HAL_ADC_Init() ).
- * @param hadc: ADC handle
- * @param multimode: Structure of ADC multimode configuration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
-{
- HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- ADC_HandleTypeDef tmphadcSlave;
-
- /* Check the parameters */
- assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_MODE(multimode->Mode));
-
- /* Process locked */
- __HAL_LOCK(hadc);
-
- /* Set a temporary handle of the ADC slave associated to the ADC master */
- ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going on regular group: */
- /* - ADC master and ADC slave DMA configuration */
- /* Parameters that can be updated only when ADC is disabled: */
- /* - Multimode mode selection */
- /* To optimize code, all multimode settings can be set when both ADCs of */
- /* the common group are in state: disabled. */
- if ((ADC_IS_ENABLE(hadc) == RESET) &&
- (ADC_IS_ENABLE(&tmphadcSlave) == RESET) &&
- (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) )
- {
- MODIFY_REG(hadc->Instance->CR1,
- ADC_CR1_DUALMOD ,
- multimode->Mode );
- }
- /* If one of the ADC sharing the same common group is enabled, no update */
- /* could be done on neither of the multimode structure parameters. */
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
- tmp_hal_status = HAL_ERROR;
- }
-
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Return function status */
- return tmp_hal_status;
-}
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_can.c b/lib/hal-stm32f1/source/stm32f1xx_hal_can.c deleted file mode 100644 index aa62b831..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_can.c +++ /dev/null @@ -1,1702 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_can.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief CAN HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (++) Connect and configure the involved CAN pins using the
- following function HAL_GPIO_Init();
-
- (#) Initialize and configure the CAN using HAL_CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN HAL driver header file for more useful macros
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CAN CAN
- * @brief CAN driver modules
- * @{
- */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-#define CAN_TIMEOUT_VALUE 10U
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
- * @{
- */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the CAN.
- (+) De-initialize the CAN.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
-{
- uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0U;
- uint32_t tmp_mcr = 0U;
-
- /* Check CAN handle */
- if(hcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
- assert_param(IS_CAN_MODE(hcan->Init.Mode));
- assert_param(IS_CAN_SJW(hcan->Init.SJW));
- assert_param(IS_CAN_BS1(hcan->Init.BS1));
- assert_param(IS_CAN_BS2(hcan->Init.BS2));
- assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
- if(hcan->State == HAL_CAN_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcan->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_CAN_MspInit(hcan);
- }
-
- /* Initialize the CAN state*/
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Exit from sleep mode */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
- /* Request initialisation */
- SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- /* Set the time triggered communication mode */
- if (hcan->Init.TTCM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_TTCM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
- }
-
- /* Set the automatic bus-off management */
- if (hcan->Init.ABOM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_ABOM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
- }
-
- /* Set the automatic wake-up mode */
- if (hcan->Init.AWUM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_AWUM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
- }
- /* Set the no automatic retransmission */
- if (hcan->Init.NART == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_NART);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
- }
-
- /* Set the receive FIFO locked mode */
- if (hcan->Init.RFLM == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_RFLM);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
- }
- /* Set the transmit FIFO priority */
- if (hcan->Init.TXFP == ENABLE)
- {
- SET_BIT(tmp_mcr, CAN_MCR_TXFP);
- }
- else
- {
- CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
- }
-
- /* Update register MCR */
- MODIFY_REG(hcan->Instance->MCR,
- CAN_MCR_TTCM |
- CAN_MCR_ABOM |
- CAN_MCR_AWUM |
- CAN_MCR_NART |
- CAN_MCR_RFLM |
- CAN_MCR_TXFP,
- tmp_mcr);
-
- /* Set the bit timing register */
- WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
- hcan->Init.SJW |
- hcan->Init.BS1 |
- hcan->Init.BS2 |
- (hcan->Init.Prescaler - 1U)));
-
- /* Request leave initialisation */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check acknowledged */
- if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- status = CAN_INITSTATUS_SUCCESS;
- }
- }
-
- if(status == CAN_INITSTATUS_SUCCESS)
- {
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
- * contains the filter configuration information.
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
- uint32_t filternbrbitpos = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
-
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
- assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
- filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
-
- /* Initialisation mode for the filter */
- /* Select the start slave bank */
- MODIFY_REG(hcan->Instance->FMR ,
- CAN_FMR_CAN2SB ,
- CAN_FMR_FINIT |
- (uint32_t)(sFilterConfig->BankNumber << 8U) );
-
- /* Filter Deactivation */
- CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
-
- /* Filter Scale */
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
- {
- /* 16-bit scale for the filter */
- CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
- }
-
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
- {
- /* 32-bit scale for the filter */
- SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
- /* 32-bit identifier or First 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
- {
- /*Id/Mask mode for the filter*/
- CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
- }
-
- /* Filter FIFO assignment */
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
- }
- else
- {
- /* FIFO 1 assignation for the filter */
- SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
- }
-
- /* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
- {
- SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
- }
-
- /* Leave the initialisation mode for the filter */
- CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
-{
- /* Check CAN handle */
- if(hcan == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CAN_MspDeInit(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Transmit a CAN frame message.
- (+) Receive a CAN frame message.
- (+) Enter CAN peripheral in sleep mode.
- (+) Wake up the CAN peripheral from sleep mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
-{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Select one empty transmit mailbox */
- if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
-
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
- /* Request transmission */
- SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check End of transmission flag */
- while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Cancel transmission */
- __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- }
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process Locked */
- __HAL_LOCK(hcan);
-
- /* Select one empty transmit mailbox */
- if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
-
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
- ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- }
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
- {
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
- }
- else
- {
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
-
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
- {
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if(FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- }
- }
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- else
- {
- /* Enable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Request Sleep mode */
- MODIFY_REG(hcan->Instance->MCR,
- CAN_MCR_INRQ ,
- CAN_MCR_SLEEP );
-
- /* Sleep mode status */
- if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
- * is in the normal mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Wake up request */
- CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Sleep mode status */
- while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
- {
- if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handles CAN interrupt request
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
- uint32_t errorcode = HAL_CAN_ERROR_NONE;
-
- /* Check Overrun flag for FIFO0 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
- if((tmp1 != 0U) && tmp2)
- {
- /* Set CAN error code to FOV0 error */
- errorcode |= HAL_CAN_ERROR_FOV0;
-
- /* Clear FIFO0 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
- }
-
- /* Check Overrun flag for FIFO1 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
- if((tmp1 != 0U) && tmp2)
- {
- /* Set CAN error code to FOV1 error */
- errorcode |= HAL_CAN_ERROR_FOV1;
-
- /* Clear FIFO1 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
- }
-
- /* Check End of transmission flag */
- if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
- {
- /* Check Transmit request completion status */
- tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
- tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
- tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
- if(tmp1 || tmp2 || tmp3)
- {
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
- tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
- tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
- /* Check Transmit success */
- if((tmp1) || (tmp2) || (tmp3))
- {
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
- }
- else /* Transmit failure */
- {
- /* Set CAN error code to TXFAIL error */
- errorcode |= HAL_CAN_ERROR_TXFAIL;
- }
-
- /* Clear transmission status flags (RQCPx and TXOKx) */
- SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
- CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
- }
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
- /* Check End of reception flag for FIFO0 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO0);
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
- /* Check End of reception flag for FIFO1 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO1);
- }
-
- /* Set error code in handle */
- hcan->ErrorCode |= errorcode;
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Warning Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EWG error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- /* No need for clear of Error Warning Flag as read-only */
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Passive Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EPV error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- /* No need for clear of Error Passive Flag as read-only */
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Bus-Off Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to BOF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- /* No need for clear of Bus-Off Flag as read-only */
- }
-
- tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Last error code Flag */
- if((!tmp1) && tmp2 && tmp3)
- {
- tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
- switch(tmp1)
- {
- case(CAN_ESR_LEC_0):
- /* Set CAN error code to STF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_STF;
- break;
- case(CAN_ESR_LEC_1):
- /* Set CAN error code to FOR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
- break;
- case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
- /* Set CAN error code to ACK error */
- hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
- break;
- case(CAN_ESR_LEC_2):
- /* Set CAN error code to BR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BR;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
- /* Set CAN error code to BD error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BD;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
- /* Set CAN error code to CRC error */
- hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
- break;
- default:
- break;
- }
-
- /* Clear Last error code Flag */
- CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
- }
-
- /* Call the Error call Back in case of Errors */
- if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
- {
- /* Clear ERRI Flag */
- hcan->Instance->MSR = CAN_MSR_ERRI;
- /* Set the CAN state ready to be able to start again the process */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- /* - Disable FIFO 0 message pending Interrupt */
- /* - Disable FIFO 0 Overrun Interrupt */
- /* - Disable FIFO 1 message pending Interrupt */
- /* - Disable FIFO 1 Overrun Interrupt */
- /* - Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_FMP0|
- CAN_IT_FOV0|
- CAN_IT_FMP1|
- CAN_IT_FOV1|
- CAN_IT_TME );
-
- /* Call Error callback function */
- HAL_CAN_ErrorCallback(hcan);
- }
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Error CAN callback.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Error functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to :
- (+) Check the CAN state.
- (+) Check CAN Errors detected during interrupt process
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the CAN state
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL state
- */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
-{
- /* Return CAN state */
- return hcan->State;
-}
-
-/**
- * @brief Return the CAN error code
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval CAN Error Code
- */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
- return hcan->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Private_Functions
- * @{
- */
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
-{
- /* Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
- }
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
-
- /* Transmission complete callback */
- HAL_CAN_TxCpltCallback(hcan);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- * @retval None
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- uint32_t tmp1 = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
- {
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
- }
- else
- {
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-
- /* Disable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
- /* Disable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- tmp1 = hcan->State;
- if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
- {
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
- }
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Receive complete callback */
- HAL_CAN_RxCpltCallback(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_cec.c b/lib/hal-stm32f1/source/stm32f1xx_hal_cec.c deleted file mode 100644 index 954ae156..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_cec.c +++ /dev/null @@ -1,694 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_cec.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief CEC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Definition Multimedia Interface
- * Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization function
- * + IO operation function
- * + Peripheral Control function
- *
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The CEC HAL driver can be used as follow:
-
- (#) Declare a CEC_HandleTypeDef handle structure.
- (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
- (##) Enable the CEC interface clock.
- (##) CEC pins configuration:
- (+++) Enable the clock for the CEC GPIOs.
- (+++) Configure these CEC pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
- and HAL_CEC_Receive_IT() APIs):
- (+++) Configure the CEC interrupt priority.
- (+++) Enable the NVIC CEC IRQ handle.
- (+++) The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
-
- (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
-
- (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- [..]
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_CEC_MspInit() API.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-#ifdef HAL_CEC_MODULE_ENABLED
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CEC CEC
- * @brief HAL CEC module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-#define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM )
-#define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF)
-#define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF)
-#define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
-#define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Functions CEC Exported Functions
- * @{
- */
-
-/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the CEC
- (+) The following parameters need to be configured:
- (++) TimingErrorFree
- (++) PeriodErrorFree
- (++) InitiatorAddress
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CEC mode according to the specified
- * parameters in the CEC_InitTypeDef and creates the associated handle .
- * @param hcec: CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
- assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
- assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
- assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
-
- if(hcec->gState == HAL_CEC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcec->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_CEC_MspInit(hcec);
- }
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- /* Write to CEC Control Register */
- MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
-
- /* Write to CEC Own Address Register */
- MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
-
- /* Configure the prescaler to generate the required 50 microseconds time base.*/
- MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U);
-
- /* Enable the following CEC Interrupt */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
-
- /* Enable the CEC Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->RxState = HAL_CEC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the CEC peripheral
- * @param hcec: CEC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
-{
- /* Check the CEC handle allocation */
- if(hcec == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CEC_MspDeInit(hcec);
-
- __HAL_RCC_CEC_FORCE_RESET();
- __HAL_RCC_CEC_RELEASE_RESET();
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->gState = HAL_CEC_STATE_RESET;
- hcec->RxState = HAL_CEC_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the Own Address of the CEC device
- * @param hcec: CEC handle
- * @param CEC_OwnAddress: The CEC own address.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
-{
- /* Check the parameters */
- assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
-
- if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
- {
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->gState = HAL_CEC_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
- {
- MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
- }
- else
- {
- CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA);
- }
-
- hcec->gState = HAL_CEC_STATE_READY;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief CEC MSP Init
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC MSP DeInit
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the CEC data transfers.
-
- (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
-
- (#) The communication is performed using Interrupts.
- These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated CEC IRQ when using Interrupt mode.
- The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_CEC_ErrorCallback() user callback will be executed when a communication
- error is detected
-
- (#) API's with Interrupt are :
- (+) HAL_CEC_Transmit_IT()
- (+) HAL_CEC_IRQHandler()
-
- (#) A set of User Callbacks are provided:
- (+) HAL_CEC_TxCpltCallback()
- (+) HAL_CEC_RxCpltCallback()
- (+) HAL_CEC_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send data in interrupt mode
- * @param hcec: CEC handle
- * @param InitiatorAddress: Initiator address
- * @param DestinationAddress: destination logical address
- * @param pData: pointer to input byte data buffer
- * @param Size: amount of data to be sent in bytes (without counting the header).
- * 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
-{
- /* if the IP isn't already busy and if there is no previous transmission
- already pending due to arbitration lost */
- if(hcec->gState == HAL_CEC_STATE_READY)
- {
- if((pData == NULL ) && (Size > 0U))
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
- assert_param(IS_CEC_ADDRESS(InitiatorAddress));
- assert_param(IS_CEC_MSGSIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hcec);
- hcec->pTxBuffPtr = pData;
- hcec->gState = HAL_CEC_STATE_BUSY_TX;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
-
- /* send header block */
- hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* case no data to be sent, sender is only pinging the system */
- if (Size != 0)
- {
- /* Set TX Start of Message (TXSOM) bit */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM);
- }
- else
- {
- /* Send a ping command */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM);
- }
- return HAL_OK;
-
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Get size of the received frame.
- * @param hcec: CEC handle
- * @retval Frame size
- */
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
-{
- return hcec->RxXferSize;
-}
-
-/**
- * @brief Change Rx Buffer.
- * @param hcec: CEC handle
- * @param Rxbuffer: Rx Buffer
- * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
- * @retval Frame size
- */
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
-{
- hcec->Init.RxBuffer = Rxbuffer;
-}
-
-/**
- * @brief This function handles CEC interrupt requests.
- * @param hcec: CEC handle
- * @retval None
- */
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
-{
- /* Save error status register for further error handling purposes */
- hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
-
- /* Transmit error */
- if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)
- {
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
-
- hcec->gState = HAL_CEC_STATE_READY;
- }
-
- /* Receive error */
- if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)
- {
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- hcec->RxXferSize = 0U;
- hcec->RxState = HAL_CEC_STATE_READY;
- }
-
- if((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U)
- {
- /* Error Call Back */
- HAL_CEC_ErrorCallback(hcec);
- }
-
- /* Transmit byte request or block transfer finished */
- if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)
- {
- CEC_Transmit_IT(hcec);
- }
-
- /* Receive byte or block transfer finished */
- if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)
- {
- if(hcec->RxXferSize == 0U)
- {
- /* reception is starting */
- hcec->RxState = HAL_CEC_STATE_BUSY_RX;
- }
- CEC_Receive_IT(hcec);
- }
-}
-
-
-/**
- * @brief Tx Transfer completed callback
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback
- * @param hcec: CEC handle
- * @param RxFrameSize: Size of frame
- * @retval None
- */
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- UNUSED(RxFrameSize);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief CEC error callbacks
- * @param hcec: CEC handle
- * @retval None
- */
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_CEC_ErrorCallback can be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
- * @brief CEC control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control function #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CEC.
- (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
-@endverbatim
- * @{
- */
-/**
- * @brief return the CEC state
- * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC module.
- * @retval HAL state
- */
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hcec->gState;
- temp2 = hcec->RxState;
-
- return (HAL_CEC_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-* @brief Return the CEC error code
-* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
- * the configuration information for the specified CEC.
-* @retval CEC Error Code
-*/
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
-{
- return hcec->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup CEC_Private_Functions
- * @{
- */
-
- /**
- * @brief Send data in interrupt mode
- * @param hcec: CEC handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_CEC_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
-{
- /* if the IP is already busy or if there is a previous transmission
- already pending due to arbitration loss */
- if((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
- {
- /* if all data have been sent */
- if(hcec->TxXferCount == 0U)
- {
- /* Acknowledge successful completion by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
-
- hcec->gState = HAL_CEC_STATE_READY;
-
- HAL_CEC_TxCpltCallback(hcec);
-
- return HAL_OK;
- }
- else
- {
- /* Reduce the number of bytes to transfer by one */
- hcec->TxXferCount--;
-
- /* Write data to TX buffer*/
- hcec->Instance->TXD = *hcec->pTxBuffPtr++;
-
- /* If this is the last byte of the ongoing transmission */
- if(hcec->TxXferCount == 0U)
- {
- /* Acknowledge byte request and signal end of message */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
- }
- else
- {
- /* Acknowledge byte request by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
- }
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive data in interrupt mode.
- * @param hcec: CEC handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_CEC_Receive_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
-{
- static uint32_t temp;
-
- if(hcec->RxState == HAL_CEC_STATE_BUSY_RX)
- {
- temp = hcec->Instance->CSR;
-
- /* Store received data */
- hcec->RxXferSize++;
- *hcec->Init.RxBuffer++ = hcec->Instance->RXD;
-
- /* Acknowledge received byte by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U);
-
- /* If the End Of Message is reached */
- if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
- {
- /* Interrupts are not disabled due to transmission still ongoing */
- hcec->RxState = HAL_CEC_STATE_READY;
-
- HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
-
-#endif /* HAL_CEC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_cortex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_cortex.c deleted file mode 100644 index 06e867b5..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_cortex.c +++ /dev/null @@ -1,523 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_cortex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief CORTEX HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CORTEX:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
-
- [..]
- *** How to configure Interrupts using CORTEX HAL driver ***
- ===========================================================
- [..]
- This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M3 exceptions are managed by CMSIS functions.
-
- (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
- function according to the following table.
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
- (#) please refer to programming manual for details in how to configure priority.
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
- The pending IRQ priority will be managed only by the sub priority.
-
- -@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest preemption priority
- (+@) Lowest sub priority
- (+@) Lowest hardware priority (IRQ number)
-
- [..]
- *** How to configure Systick using CORTEX HAL driver ***
- ========================================================
- [..]
- Setup SysTick Timer for time base.
-
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
- is a CMSIS function that:
- (++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
- (++) Resets the SysTick Counter register.
- (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
- (++) Enables the SysTick Interrupt.
- (++) Starts the SysTick Counter.
-
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
- inside the stm32f1xx_hal_cortex.h file.
-
- (+) You can change the SysTick IRQ priority by calling the
- HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
- call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
- (+) To adjust the SysTick time base, use the following formula:
-
- Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
- (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
- (++) Reload Value should not exceed 0xFFFFFF
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CORTEX CORTEX
- * @brief CORTEX HAL module driver
- * @{
- */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides the CORTEX HAL driver functions allowing to configure Interrupts
- Systick functionalities
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Sets the priority grouping field (preemption priority and subpriority)
- * using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
- * @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
- * @param PreemptPriority: The preemption priority for the IRQn channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
- * @brief Enables a device specific interrupt in the NVIC interrupt controller.
- * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
- * function should be called before.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
-}
-
-/**
- * @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Disable interrupt */
- NVIC_DisableIRQ(IRQn);
-}
-
-/**
- * @brief Initiates a system reset request to reset the MCU.
- * @retval None
- */
-void HAL_NVIC_SystemReset(void)
-{
- /* System Reset */
- NVIC_SystemReset();
-}
-
-/**
- * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- * Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- return SysTick_Config(TicksNumb);
-}
-/**
- * @}
- */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK, MPU) functionalities.
-
-
-@endverbatim
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-void HAL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
-
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU and clear the control register*/
- MPU->CTRL = 0U;
-}
-
-/**
- * @brief Enable the MPU.
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Ensure MPU setting take effects */
- __DSB();
- __ISB();
-}
-
-/**
- * @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
- * @retval None
- */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
- /* Check the parameters */
- assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
- assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
- /* Set the Region number */
- MPU->RNR = MPU_Init->Number;
-
- if ((MPU_Init->Enable) != RESET)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
- * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
- */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
- /* Get the PRIGROUP[10:8] field value */
- return NVIC_GetPriorityGrouping();
-}
-
-/**
- * @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @param PriorityGroup: the priority grouping bits length.
- * This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
- * 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
- * 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
- * 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
- * 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
- * 0 bits for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
- * @retval None
- */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
- NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
- * @brief Sets Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Set interrupt pending */
- NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC
- * and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if pending else 0 */
- return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
- * @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number.
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval None
- */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Clear pending interrupt */
- NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
- * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @retval status: - 0 Interrupt status is not pending.
- * - 1 Interrupt status is pending.
- */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Return 1 if active else 0 */
- return NVIC_GetActive(IRQn);
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
- if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
- {
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
- }
- else
- {
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
- }
-}
-
-/**
- * @brief This function handles SYSTICK interrupt request.
- * @retval None
- */
-void HAL_SYSTICK_IRQHandler(void)
-{
- HAL_SYSTICK_Callback();
-}
-
-/**
- * @brief SYSTICK callback.
- * @retval None
- */
-__weak void HAL_SYSTICK_Callback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SYSTICK_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_crc.c b/lib/hal-stm32f1/source/stm32f1xx_hal_crc.c deleted file mode 100644 index 2835997d..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_crc.c +++ /dev/null @@ -1,348 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_crc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief CRC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The CRC HAL driver can be used as follows:
-
- (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-
- (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
- a 32-bit data buffer using combination of the previous CRC value
- and the new one.
-
- (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
- a new 32-bit data buffer. This function resets the CRC computation
- unit before starting the computation to avoid getting wrong CRC values.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRC CRC
- * @brief CRC HAL module driver.
- * @{
- */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRC according to the specified parameters
- in the CRC_InitTypeDef and create the associated handle
- (+) DeInitialize the CRC peripheral
- (+) Initialize the CRC MSP
- (+) DeInitialize CRC MSP
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the CRC according to the specified
- * parameters in the CRC_InitTypeDef and creates the associated handle.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- if(hcrc->State == HAL_CRC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hcrc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_CRC_MspInit(hcrc);
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the CRC peripheral.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Check the CRC handle allocation */
- if(hcrc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_CRC_MspDeInit(hcrc);
-
- /* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */
- __HAL_CRC_DR_RESET(hcrc);
-
- /* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRC MSP.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @retval None
- */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the CRC MSP.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @retval None
- */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcrc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Compute the 32-bit CRC value of 32-bit data buffer,
- using combination of the previous CRC value and the new one.
- (+) Compute the 32-bit CRC value of 32-bit data buffer,
- independently of the previous CRC value.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Computes the 32-bit CRC of 32-bit data buffer using combination
- * of the previous CRC value and the new one.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed (defined in word, 4 bytes)
- * @retval 32-bit CRC
- */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-/**
- * @brief Computes the 32-bit CRC of 32-bit data buffer independently
- * of the previous CRC value.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @param pBuffer: Pointer to the buffer containing the data to be computed
- * @param BufferLength: Length of the buffer to be computed (defined in word, 4 bytes)
- * @retval 32-bit CRC
- */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC Calculation Unit */
- __HAL_CRC_DR_RESET(hcrc);
-
- /* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
- {
- hcrc->Instance->DR = pBuffer[index];
- }
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CRC state.
- * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @retval HAL state
- */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
- return hcrc->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_dac.c b/lib/hal-stm32f1/source/stm32f1xx_hal_dac.c deleted file mode 100644 index c1fa7754..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_dac.c +++ /dev/null @@ -1,939 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_dac.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Digital to Analog Converter (DAC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- *
- @verbatim
- ==============================================================================
- ##### DAC Peripheral features #####
- ==============================================================================
- [..]
- *** DAC Channels ***
- ====================
- [..]
- The device integrates two 12-bit Digital Analog Converters that can
- be used independently or simultaneously (dual mode):
- (#) DAC channel1 with DAC_OUT1 (PA4) as output
- (#) DAC channel2 with DAC_OUT2 (PA5) as output
-
- *** DAC Triggers ***
- ====================
- [..]
- Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
- and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
- [..]
- Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
- The used pin (GPIOx_PIN_9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
- For STM32F10x connectivity line devices and STM32F100x devices: TIM3
- For STM32F10x high-density and XL-density devices: TIM8
- For STM32F100x high-density value line devices: TIM15 as
- replacement of TIM5.
- (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
- (#) Software using DAC_TRIGGER_SOFTWARE
-
- *** DAC Buffer mode feature ***
- ===============================
- [..]
- Each DAC channel integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
- [..]
- (@) Refer to the device datasheet for more details about output
- impedance value with and without output buffer.
-
- *** DAC connect feature ***
- ===============================
- [..]
- Each DAC channel can be connected internally.
- To connect, use
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
-
- *** GPIO configurations guidelines ***
- =====================
- [..]
- When a DAC channel is used (ex channel1 on PA4) and the other is not
- (ex channel1 on PA5 is configured in Analog and disabled).
- Channel1 may disturb channel2 as coupling effect.
- Note that there is no coupling on channel2 as soon as channel2 is turned on.
- Coupling on adjacent channel could be avoided as follows:
- when unused PA5 is configured as INPUT PULL-UP or DOWN.
- PA5 is configured in ANALOG just before it is turned on.
-
- *** DAC wave generation feature ***
- ===================================
- [..]
- Both DAC channels can be used to generate
- (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
- (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
-
- *** DAC data format ***
- =======================
- [..]
- The DAC data format can be:
- (#) 8-bit right alignment using DAC_ALIGN_8B_R
- (#) 12-bit left alignment using DAC_ALIGN_12B_L
- (#) 12-bit right alignment using DAC_ALIGN_12B_R
-
- *** DAC data value to voltage correspondance ***
- ================================================
- [..]
- The analog output voltage on each DAC channel pin is determined
- by the following equation:
- [..]
- DAC_OUTx = VREF+ * DOR / 4095
- (+) with DOR is the Data Output Register
- [..]
- VEF+ is the input voltage reference (refer to the device datasheet)
- [..]
- e.g. To set DAC_OUT1 to 0.7V, use
- (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- *** DMA requests ***
- =====================
- [..]
- A DMA1 request can be generated when an external trigger (but not
- a software trigger) occurs if DMA1 requests are enabled using
- HAL_DAC_Start_DMA()
- [..]
- DMA requests are mapped as following:
- (#) DAC channel1 :
- For STM32F100x low-density, medium-density, high-density with DAC
- DMA remap:
- mapped on DMA1 channel3 which must be
- already configured
- For STM32F100x high-density without DAC DMA remap and other
- STM32F1 devices:
- mapped on DMA2 channel3 which must be
- already configured
- (#) DAC channel2 :
- For STM32F100x low-density, medium-density, high-density with DAC
- DMA remap:
- mapped on DMA1 channel4 which must be
- already configured
- For STM32F100x high-density without DAC DMA remap and other
- STM32F1 devices:
- mapped on DMA2 channel4 which must be
- already configured
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) DAC APB clock must be enabled to get write access to DAC
- registers using HAL_DAC_Init()
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
- (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
- (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
- (+) Stop the DAC peripheral using HAL_DAC_Stop()
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
- (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
- (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
- (+) For STM32F100x devices with specific feature: DMA underrun.
- In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
- HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
- HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
- add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
- (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
- *** DAC HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DAC HAL driver.
-
- (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
- (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
- (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
- (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
-
- [..]
- (@) You can refer to the DAC HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DAC DAC
- * @brief DAC driver modules
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions -------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
- * @{
- */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the DAC.
- (+) De-initialize the DAC.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- if(hdac->State == HAL_DAC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdac->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_DAC_MspInit(hdac);
- }
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Initialize the DAC state*/
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
- /* Check DAC handle */
- if(hdac == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_DAC_MspDeInit(hdac);
-
- /* Set DAC error code to none */
- hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the Peripharal */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
- {
- /* Enable the selected DAC software conversion */
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
- }
- }
- else
- {
- /* Check if software trigger enabled */
- if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
- {
- /* Enable the selected DAC software conversion*/
- SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
- }
- }
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the Peripheral */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enables DAC and starts conversion of channel.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function enables the interruption of DMA
- * underrun.
- * (refer to redefinition of this function in DAC extended file)
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData: The Source memory Buffer address.
- * @param Length: The length of data to be transferred from memory to DAC peripheral
- * @param Alignment: Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
- }
- else
- {
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
- /* Enable the selected DAC channel2 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Case of use of channel 2 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
- break;
- default:
- break;
- }
- }
-
- /* Enable the DMA channel */
- if(Channel == DAC_CHANNEL_1)
- {
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- }
- else
- {
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Enable the Peripharal */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Disables DAC and stop conversion of channel.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function disables the interruption of DMA
- * underrun.
- * (refer to redefinition of this function in DAC extended file)
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the selected DAC channel DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
-
- /* Disable the Peripharal */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Disable the DMA Channel */
- /* Channel1 is used */
- if (Channel == DAC_CHANNEL_1)
- {
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
- }
- else /* Channel2 is used for */
- {
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
- }
-
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update ADC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Returns the DAC channel data output register value */
- if(Channel == DAC_CHANNEL_1)
- {
- return hdac->Instance->DOR1;
- }
- else
- {
- return hdac->Instance->DOR2;
- }
-}
-
-/**
- * @brief Conversion complete callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
- uint32_t tmpreg1 = 0U;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Configure for the selected DAC channel: buffer output, trigger */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
-
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- /* Calculate CR register value depending on DAC_Channel */
- MODIFY_REG(hdac->Instance->CR,
- ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
- tmpreg1 << Channel);
-
- /* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param Alignment: Specifies the data alignment.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- __IO uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)hdac->Instance;
- if(Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
- }
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
- }
-
- /* Set the DAC channel selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DAC state.
- (+) Check the DAC Errors.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the DAC state
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval HAL state
- */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
- /* Return DAC state */
- return hdac->State;
-}
-
-
-/**
- * @brief Return the DAC error code
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval DAC Error Code
- */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
- return hdac->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DAC_ConvCpltCallbackCh1(hdac);
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DAC_ErrorCallbackCh1(hdac);
-
- hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_dac_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_dac_ex.c deleted file mode 100644 index 61a22194..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_dac_ex.c +++ /dev/null @@ -1,669 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_dac_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of DAC extension peripheral:
- * + Extended features functions
- *
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
- Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
- HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
- (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
- (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DACEx DACEx
- * @brief DACEx driver module
- * @{
- */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
- * @{
- */
-
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
- (+) Get result of dual mode conversion.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval The selected DAC channel data output value.
- */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
- uint32_t tmp = 0U;
-
- tmp |= hdac->Instance->DOR1;
-
- tmp |= hdac->Instance->DOR2 << 16U;
-
- /* Returns the DAC channel data output register value */
- return tmp;
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * DAC_CHANNEL_1 / DAC_CHANNEL_2
- * @param Amplitude: Select max triangle amplitude.
- * This parameter can be one of the following values:
- * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
- * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
- * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
- * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
- * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
- * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
- * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
- * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
- * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
- * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
- * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
- * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * DAC_CHANNEL_1 / DAC_CHANNEL_2
- * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
- * This parameter can be one of the following values:
- * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
- * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Alignment: Specifies the data alignment for dual channel DAC.
- * This parameter can be one of the following values:
- * DAC_ALIGN_8B_R: 8bit right data alignment selected
- * DAC_ALIGN_12B_L: 12bit left data alignment selected
- * DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
- uint32_t data = 0U, tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(Alignment));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (Alignment == DAC_ALIGN_8B_R)
- {
- data = ((uint32_t)Data2 << 8U) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16U) | Data1;
- }
-
- tmp = (uint32_t)hdac->Instance;
- tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Conversion complete callback in non blocking mode for Channel2
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
- */
-}
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/**
- * @brief DMA underrun DAC callback for channel1.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function uses the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for channel2.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function uses the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdac);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
- */
-}
-#endif /* STM32F100xB) || defined (STM32F100xE) */
-
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/**
- * @brief Enables DAC and starts conversion of channel.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function enables the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData: The destination peripheral Buffer address.
- * @param Length: The length of data to be transferred from memory to DAC peripheral
- * @param Alignment: Specifies the data alignment for DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
- assert_param(IS_DAC_ALIGN(Alignment));
-
- /* Process locked */
- __HAL_LOCK(hdac);
-
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_BUSY;
-
- if(Channel == DAC_CHANNEL_1)
- {
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Enable the selected DAC channel1 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Case of use of channel 1 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R1 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
- break;
- default:
- break;
- }
- }
- else
- {
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
- /* Enable the selected DAC channel2 DMA request */
- SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Case of use of channel 2 */
- switch(Alignment)
- {
- case DAC_ALIGN_12B_R:
- /* Get DHR12R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
- break;
- case DAC_ALIGN_12B_L:
- /* Get DHR12L2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
- break;
- case DAC_ALIGN_8B_R:
- /* Get DHR8R2 address */
- tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
- break;
- default:
- break;
- }
- }
-
- /* Enable the DMA channel */
- if(Channel == DAC_CHANNEL_1)
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- }
- else
- {
- /* Enable the DAC DMA underrun interrupt */
- __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
- }
-
- /* Enable the Peripharal */
- __HAL_DAC_ENABLE(hdac, Channel);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdac);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* STM32F100xB) || defined (STM32F100xE) */
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/**
- * @brief Disables DAC and stop conversion of channel.
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function disables the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(Channel));
-
- /* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-
- /* Disable the Peripharal */
- __HAL_DAC_DISABLE(hdac, Channel);
-
- /* Disable the DMA Channel */
- /* Channel1 is used */
- if(Channel == DAC_CHANNEL_1)
- {
- /* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
- }
- else /* Channel2 is used for */
- {
- /* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
-
- /* Disable the DAC DMA underrun interrupt */
- __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
- }
-
- /* Check if DMA Channel effectively disabled */
- if(status != HAL_OK)
- {
- /* Update ADC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
-
- /* Return function status */
- return status;
-}
-#endif /* STM32F100xB) || defined (STM32F100xE) */
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/**
- * @brief Handles DAC interrupt request
- * Note: For STM32F100x devices with specific feature: DMA underrun.
- * On these devices, this function uses the interruption of DMA
- * underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
- {
- /* Check underrun flag of DAC channel 1 */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to chanel1 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
- }
- }
-
- if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
- {
- /* Check underrun flag of DAC channel 2 */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
-
- /* Set DAC error code to channel2 DMA underrun error */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-
- /* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
- /* Error callback */
- HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
- }
- }
-}
-#endif /* STM32F100xB || STM32F100xE */
-
-
-/**
- * @}
- */
-
-/** @defgroup DACEx_Private_Functions DACEx Private Functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DACEx_ConvCpltCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DACEx_ErrorCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_dma.c b/lib/hal-stm32f1/source/stm32f1xx_hal_dma.c deleted file mode 100644 index 8dae62ca..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_dma.c +++ /dev/null @@ -1,905 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief DMA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable and configure the peripheral to be connected to the DMA Channel
- (except for internal SRAM / FLASH memories: no initialization is
- necessary). Please refer to the Reference manual for connection between peripherals
- and DMA requests.
-
- (#) For a given Channel, program the required configuration through the following parameters:
- Channel request, Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
- using HAL_DMA_Init() function.
-
- (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
- detection.
-
- (#) Use HAL_DMA_Abort() function to abort the current transfer
-
- -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
- (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e. a member of DMA handle structure).
-
- *** DMA HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in DMA HAL driver.
-
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
-
- [..]
- (@) You can refer to the DMA HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMA DMA
- * @brief DMA HAL module driver
- * @{
- */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize the DMA Channel source
- and destination addresses, incrementation and data sizes, transfer direction,
- circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
- [..]
- The HAL_DMA_Init() function follows the DMA configuration procedures as described in
- reference manual.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the DMA according to the specified
- * parameters in the DMA_InitTypeDef and initialize the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp = 0U;
-
- /* Check the DMA handle allocation */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
- assert_param(IS_DMA_MODE(hdma->Init.Mode));
- assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
- /* calculation of the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-#else
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Get the CR register value */
- tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
- DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
- DMA_CCR_DIR));
-
- /* Prepare the DMA Channel configuration */
- tmp |= hdma->Init.Direction |
- hdma->Init.PeriphInc | hdma->Init.MemInc |
- hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
- hdma->Init.Mode | hdma->Init.Priority;
-
- /* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
-
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
- /* Initialise the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the DMA peripheral.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
- /* Check the DMA handle allocation */
- if(hdma == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-
- /* Disable the selected DMA Channelx */
- __HAL_DMA_DISABLE(hdma);
-
- /* Reset DMA Channel control register */
- hdma->Instance->CCR = 0U;
-
- /* Reset DMA Channel Number of Data to Transfer register */
- hdma->Instance->CNDTR = 0U;
-
- /* Reset DMA Channel peripheral address register */
- hdma->Instance->CPAR = 0U;
-
- /* Reset DMA Channel memory address register */
- hdma->Instance->CMAR = 0U;
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
- /* calculation of the channel index */
- if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
- {
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
- }
- else
- {
- /* DMA2 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA2;
- }
-#else
- /* DMA1 */
- hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
- hdma->DmaBaseAddress = DMA1;
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
-
- /* Initialize the error code */
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the DMA state */
- hdma->State = HAL_DMA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief Input and Output operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
- Start DMA transfer with interrupt
- (+) Abort DMA transfer
- (+) Poll for transfer complete
- (+) Handle DMA interrupt request
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
- hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length & clear flags*/
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete interrupt */
- /* Enable the transfer Error interrupt */
- if(NULL != hdma->XferHalfCpltCallback)
- {
- /* Enable the Half transfer complete interrupt as well */
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- }
- else
- {
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
- }
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Remain BUSY */
- status = HAL_BUSY;
- }
- return status;
-}
-
-/**
- * @brief Abort the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-
- status = HAL_ERROR;
- }
- else
- {
- /* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- /* Call User Abort callback */
- if(hdma->XferAbortCallback != NULL)
- {
- hdma->XferAbortCallback(hdma);
- }
- }
- return status;
-}
-
-/**
- * @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CompleteLevel: Specifies the DMA level complete.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
- uint32_t temp;
- uint32_t tickstart = 0U;
-
- if(HAL_DMA_STATE_BUSY != hdma->State)
- {
- /* no transfer ongoing */
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- __HAL_UNLOCK(hdma);
- return HAL_ERROR;
- }
-
- /* Polling mode not supported in circular mode */
- if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
- return HAL_ERROR;
- }
-
- /* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
- }
- else
- {
- /* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
- {
- if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_ERROR;
- }
- }
- }
-
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
- {
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers are complete) */
- hdma->State = HAL_DMA_STATE_READY;
- }
- else
- {
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handles DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- uint32_t flag_it = hdma->DmaBaseAddress->ISR;
- uint32_t source_it = hdma->Instance->CCR;
-
- /* Half Transfer Complete Interrupt management ******************************/
- if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* DMA peripheral state is not updated in Half Transfer */
- /* but in Transfer Complete case */
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
-
- /* Transfer Complete Interrupt management ***********************************/
- else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
- {
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- /* Disable the transfer complete and error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
- }
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
- }
-
- /* Transfer Error Interrupt management **************************************/
- else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
- {
- /* When a DMA transfer error occurs */
- /* A hardware clear of its EN bits is performed */
- /* Disable ALL DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Update error code */
- hdma->ErrorCode = HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- return;
-}
-
-/**
- * @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID: User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback: pointer to private callbacsk function which has pointer to
- * a DMA_HandleTypeDef structure as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = pCallback;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = pCallback;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param CallbackID: User Callback identifer
- * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process locked */
- __HAL_LOCK(hdma);
-
- if(HAL_DMA_STATE_READY == hdma->State)
- {
- switch (CallbackID)
- {
- case HAL_DMA_XFER_CPLT_CB_ID:
- hdma->XferCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_HALFCPLT_CB_ID:
- hdma->XferHalfCpltCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ERROR_CB_ID:
- hdma->XferErrorCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ABORT_CB_ID:
- hdma->XferAbortCallback = NULL;
- break;
-
- case HAL_DMA_XFER_ALL_CB_ID:
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
- break;
-
- default:
- status = HAL_ERROR;
- break;
- }
- }
- else
- {
- status = HAL_ERROR;
- }
-
- /* Release Lock */
- __HAL_UNLOCK(hdma);
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Check the DMA state
- (+) Get error code
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the DMA hande state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval HAL state
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
- /* Return DMA handle state */
- return hdma->State;
-}
-
-/**
- * @brief Return the DMA error code.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval DMA Error Code
- */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
- return hdma->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Private_Functions
- * @{
- */
-
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
-
- /* Configure DMA Channel data length */
- hdma->Instance->CNDTR = DataLength;
-
- /* Memory to Peripheral */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Channel destination address */
- hdma->Instance->CPAR = DstAddress;
-
- /* Configure DMA Channel source address */
- hdma->Instance->CMAR = SrcAddress;
- }
- /* Peripheral to Memory */
- else
- {
- /* Configure DMA Channel source address */
- hdma->Instance->CPAR = SrcAddress;
-
- /* Configure DMA Channel destination address */
- hdma->Instance->CMAR = DstAddress;
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_eth.c b/lib/hal-stm32f1/source/stm32f1xx_hal_eth.c deleted file mode 100644 index 5f41a88e..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_eth.c +++ /dev/null @@ -1,2043 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_eth.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief ETH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Ethernet (ETH) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#)Declare a ETH_HandleTypeDef handle structure, for example:
- ETH_HandleTypeDef heth;
-
- (#)Fill parameters of Init structure in heth handle
-
- (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
-
- (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
- (##) Enable the Ethernet interface clock using
- (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
- (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
- (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
-
- (##) Initialize the related GPIO clocks
- (##) Configure Ethernet pin-out
- (##) Configure Ethernet NVIC interrupt (IT mode)
-
- (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
- (##) HAL_ETH_DMATxDescListInit(); for Transmission process
- (##) HAL_ETH_DMARxDescListInit(); for Reception process
-
- (#)Enable MAC and DMA transmission and reception:
- (##) HAL_ETH_Start();
-
- (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
- the frame to MAC TX FIFO:
- (##) HAL_ETH_TransmitFrame();
-
- (#)Poll for a received frame in ETH RX DMA Descriptors and get received
- frame parameters
- (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
-
- (#) Get a received frame when an ETH RX interrupt occurs:
- (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
-
- (#) Communicate with external PHY device:
- (##) Read a specific register from the PHY
- HAL_ETH_ReadPHYRegister();
- (##) Write data to a specific RHY register:
- HAL_ETH_WritePHYRegister();
-
- (#) Configure the Ethernet MAC after ETH peripheral initialization
- HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
-
- (#) Configure the Ethernet DMA after ETH peripheral initialization
- HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
-
- -@- The PTP protocol and the DMA descriptors ring mode are not supported
- in this driver
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-#if defined (STM32F107xC)
-
-/** @defgroup ETH ETH
- * @brief ETH HAL module driver
- * @{
- */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ETH_Private_Constants ETH Private Constants
- * @{
- */
-#define ETH_TIMEOUT_SWRESET 500U
-#define ETH_TIMEOUT_LINKED_STATE 5000U
-#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
-
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ETH_Private_Functions ETH Private Functions
- * @{
- */
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
-static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
-static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
-static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
-static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
-static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
-static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
-static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
-static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
-static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
-static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
-static void ETH_Delay(uint32_t mdelay);
-
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ETH_Exported_Functions ETH Exported Functions
- * @{
- */
-
-/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the Ethernet peripheral
- (+) De-initialize the Ethernet peripheral
-
- @endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the Ethernet MAC and DMA according to default
- * parameters.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
-{
- uint32_t tmpreg1 = 0U, phyreg = 0U;
- uint32_t hclk = 60000000U;
- uint32_t tickstart = 0U;
- uint32_t err = ETH_SUCCESS;
-
- /* Check the ETH peripheral state */
- if(heth == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check parameters */
- assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
- assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
- assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
- assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
-
- if(heth->State == HAL_ETH_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- heth->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, NVIC. */
- HAL_ETH_MspInit(heth);
- }
-
- /* Select MII or RMII Mode*/
- AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
- AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface;
-
- /* Ethernet Software reset */
- /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
- /* After reset all the registers holds their respective reset values */
- (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for software reset */
- while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
- {
- heth->State= HAL_ETH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
- not available, please check your external PHY or the IO configuration */
- return HAL_TIMEOUT;
- }
- }
-
- /*-------------------------------- MAC Initialization ----------------------*/
- /* Get the ETHERNET MACMIIAR value */
- tmpreg1 = (heth->Instance)->MACMIIAR;
- /* Clear CSR Clock Range CR[2:0] bits */
- tmpreg1 &= ETH_MACMIIAR_CR_MASK;
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- /* Set CR bits depending on hclk value */
- if((hclk >= 20000000U)&&(hclk < 35000000U))
- {
- /* CSR Clock Range between 20-35 MHz */
- tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
- }
- else if((hclk >= 35000000U)&&(hclk < 60000000U))
- {
- /* CSR Clock Range between 35-60 MHz */
- tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
- }
- else
- {
- /* CSR Clock Range between 60-72 MHz */
- tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
- }
-
- /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
- (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
-
- /*-------------------- PHY initialization and configuration ----------------*/
- /* Put the PHY in reset mode */
- if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- /* Set the ETH peripheral state to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return HAL_ERROR */
- return HAL_ERROR;
- }
-
- /* Delay to assure PHY reset */
- HAL_Delay(PHY_RESET_DELAY);
-
- if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* We wait for linked status */
- do
- {
- HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
-
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_TIMEOUT;
- }
- } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
-
-
- /* Enable Auto-Negotiation */
- if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- /* Set the ETH peripheral state to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return HAL_ERROR */
- return HAL_ERROR;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the auto-negotiation will be completed */
- do
- {
- HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
-
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_TIMEOUT;
- }
-
- } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
-
- /* Read the result of the auto-negotiation */
- if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- /* Set the ETH peripheral state to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return HAL_ERROR */
- return HAL_ERROR;
- }
-
- /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
- if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
- {
- /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
- (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
- }
- else
- {
- /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
- (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
- }
- /* Configure the MAC with the speed fixed by the auto-negotiation process */
- if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
- {
- /* Set Ethernet speed to 10M following the auto-negotiation */
- (heth->Init).Speed = ETH_SPEED_10M;
- }
- else
- {
- /* Set Ethernet speed to 100M following the auto-negotiation */
- (heth->Init).Speed = ETH_SPEED_100M;
- }
- }
- else /* AutoNegotiation Disable */
- {
- /* Check parameters */
- assert_param(IS_ETH_SPEED(heth->Init.Speed));
- assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
-
- /* Set MAC Speed and Duplex Mode */
- if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
- (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
- {
- /* In case of write timeout */
- err = ETH_ERROR;
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- /* Set the ETH peripheral state to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return HAL_ERROR */
- return HAL_ERROR;
- }
-
- /* Delay to assure PHY configuration */
- HAL_Delay(PHY_CONFIG_DELAY);
- }
-
- /* Config MAC and DMA */
- ETH_MACDMAConfig(heth, err);
-
- /* Set ETH HAL State to Ready */
- heth->State= HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the ETH peripheral.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
-{
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
- HAL_ETH_MspDeInit(heth);
-
- /* Set ETH HAL state to Disabled */
- heth->State= HAL_ETH_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DMA Tx descriptors in chain mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param DMATxDescTab: Pointer to the first Tx desc list
- * @param TxBuff: Pointer to the first TxBuffer list
- * @param TxBuffCount: Number of the used Tx desc in the list
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
-{
- uint32_t i = 0U;
- ETH_DMADescTypeDef *dmatxdesc;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
- heth->TxDesc = DMATxDescTab;
-
- /* Fill each DMATxDesc descriptor with the right values */
- for(i=0U; i < TxBuffCount; i++)
- {
- /* Get the pointer on the ith member of the Tx Desc list */
- dmatxdesc = DMATxDescTab + i;
-
- /* Set Second Address Chained bit */
- dmatxdesc->Status = ETH_DMATXDESC_TCH;
-
- /* Set Buffer1 address pointer */
- dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
-
- if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
- {
- /* Set the DMA Tx descriptors checksum insertion */
- dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
- }
-
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */
- if(i < (TxBuffCount-1U))
- {
- /* Set next descriptor address register with next descriptor base address */
- dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
- }
- else
- {
- /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
- dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
- }
- }
-
- /* Set Transmit Descriptor List Address Register */
- (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
-
- /* Set ETH HAL State to Ready */
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the DMA Rx descriptors in chain mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param DMARxDescTab: Pointer to the first Rx desc list
- * @param RxBuff: Pointer to the first RxBuffer list
- * @param RxBuffCount: Number of the used Rx desc in the list
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
-{
- uint32_t i = 0U;
- ETH_DMADescTypeDef *DMARxDesc;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
- heth->RxDesc = DMARxDescTab;
-
- /* Fill each DMARxDesc descriptor with the right values */
- for(i=0U; i < RxBuffCount; i++)
- {
- /* Get the pointer on the ith member of the Rx Desc list */
- DMARxDesc = DMARxDescTab+i;
-
- /* Set Own bit of the Rx descriptor Status */
- DMARxDesc->Status = ETH_DMARXDESC_OWN;
-
- /* Set Buffer1 size and Second Address Chained bit */
- DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
-
- /* Set Buffer1 address pointer */
- DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
-
- if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
- {
- /* Enable Ethernet DMA Rx Descriptor interrupt */
- DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
- }
-
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */
- if(i < (RxBuffCount-1U))
- {
- /* Set next descriptor address register with next descriptor base address */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
- }
- else
- {
- /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
- }
- }
-
- /* Set Receive Descriptor List Address Register */
- (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
-
- /* Set ETH HAL State to Ready */
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
- @verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Transmit a frame
- HAL_ETH_TransmitFrame();
- (+) Receive a frame
- HAL_ETH_GetReceivedFrame();
- HAL_ETH_GetReceivedFrame_IT();
- (+) Read from an External PHY register
- HAL_ETH_ReadPHYRegister();
- (+) Write to an External PHY register
- HAL_ETH_WritePHYRegister();
-
- @endverbatim
-
- * @{
- */
-
-/**
- * @brief Sends an Ethernet frame.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param FrameLength: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
-{
- uint32_t bufcount = 0U, size = 0U, i = 0U;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- if (FrameLength == 0U)
- {
- /* Set ETH HAL state to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_ERROR;
- }
-
- /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
- if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
- {
- /* OWN bit set */
- heth->State = HAL_ETH_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_ERROR;
- }
-
- /* Get the number of needed Tx buffers for the current frame */
- if (FrameLength > ETH_TX_BUF_SIZE)
- {
- bufcount = FrameLength/ETH_TX_BUF_SIZE;
- if (FrameLength % ETH_TX_BUF_SIZE)
- {
- bufcount++;
- }
- }
- else
- {
- bufcount = 1U;
- }
- if (bufcount == 1U)
- {
- /* Set LAST and FIRST segment */
- heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
- /* Set frame size */
- heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
- /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
- heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
- /* Point to next descriptor */
- heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
- }
- else
- {
- for (i=0U; i< bufcount; i++)
- {
- /* Clear FIRST and LAST segment bits */
- heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
-
- if (i == 0U)
- {
- /* Setting the first segment bit */
- heth->TxDesc->Status |= ETH_DMATXDESC_FS;
- }
-
- /* Program size */
- heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
-
- if (i == (bufcount-1U))
- {
- /* Setting the last segment bit */
- heth->TxDesc->Status |= ETH_DMATXDESC_LS;
- size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
- heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
- }
-
- /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
- heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
- /* point to next descriptor */
- heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
- }
- }
-
- /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
- if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
- {
- /* Clear TBUS ETHERNET DMA flag */
- (heth->Instance)->DMASR = ETH_DMASR_TBUS;
- /* Resume DMA transmission*/
- (heth->Instance)->DMATPDR = 0U;
- }
-
- /* Set ETH HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Checks for received frames.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
-{
- uint32_t framelength = 0U;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Check the ETH state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Check if segment is not owned by DMA */
- /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
- if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
- {
- /* Check if last segment */
- if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
- {
- /* increment segment count */
- (heth->RxFrameInfos).SegCount++;
-
- /* Check if last segment is first segment: one segment contains the frame */
- if ((heth->RxFrameInfos).SegCount == 1U)
- {
- (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
- }
-
- heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
-
- /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
- framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
- heth->RxFrameInfos.length = framelength;
-
- /* Get the address of the buffer start address */
- heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
- /* point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
- }
- /* Check if first segment */
- else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
- {
- (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
- (heth->RxFrameInfos).LSRxDesc = NULL;
- (heth->RxFrameInfos).SegCount = 1U;
- /* Point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
- }
- /* Check if intermediate segment */
- else
- {
- (heth->RxFrameInfos).SegCount++;
- /* Point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
- }
- }
-
- /* Set ETH HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Gets the Received frame in interrupt mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
-{
- uint32_t descriptorscancounter = 0U;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set ETH HAL State to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Scan descriptors owned by CPU */
- while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
- {
- /* Just for security */
- descriptorscancounter++;
-
- /* Check if first segment in frame */
- /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
- if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
- {
- heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
- heth->RxFrameInfos.SegCount = 1U;
- /* Point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
- }
- /* Check if intermediate segment */
- /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
- else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
- {
- /* Increment segment count */
- (heth->RxFrameInfos.SegCount)++;
- /* Point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
- }
- /* Should be last segment */
- else
- {
- /* Last segment */
- heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
-
- /* Increment segment count */
- (heth->RxFrameInfos.SegCount)++;
-
- /* Check if last segment is first segment: one segment contains the frame */
- if ((heth->RxFrameInfos.SegCount) == 1U)
- {
- heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
- }
-
- /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
- heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
-
- /* Get the address of the buffer start address */
- heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
-
- /* Point to next descriptor */
- heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
- }
- }
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief This function handles ETH interrupt request.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
-{
- /* Frame received */
- if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
- {
- /* Receive complete callback */
- HAL_ETH_RxCpltCallback(heth);
-
- /* Clear the Eth DMA Rx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- }
- /* Frame transmitted */
- else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
- {
- /* Transfer complete callback */
- HAL_ETH_TxCpltCallback(heth);
-
- /* Clear the Eth DMA Tx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
- }
-
- /* Clear the interrupt flags */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
-
- /* ETH DMA Error */
- if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
- {
- /* Ethernet Error callback */
- HAL_ETH_ErrorCallback(heth);
-
- /* Clear the interrupt flags */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
-
- /* Set HAL State to Ready */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
- }
-}
-
-/**
- * @brief Tx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Ethernet transfer error callbacks
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Reads a PHY register
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
- * This parameter can be one of the following values:
- * PHY_BCR: Transceiver Basic Control Register,
- * PHY_BSR: Transceiver Basic Status Register.
- * More PHY register could be read depending on the used PHY
- * @param RegValue: PHY register value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
-{
- uint32_t tmpreg1 = 0U;
- uint32_t tickstart = 0U;
-
- /* Check parameters */
- assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
-
- /* Check the ETH peripheral state */
- if(heth->State == HAL_ETH_STATE_BUSY_RD)
- {
- return HAL_BUSY;
- }
- /* Set ETH HAL State to BUSY_RD */
- heth->State = HAL_ETH_STATE_BUSY_RD;
-
- /* Get the ETHERNET MACMIIAR value */
- tmpreg1 = heth->Instance->MACMIIAR;
-
- /* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-
- /* Prepare the MII address register value */
- tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
- tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
-
- /* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg1;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check for the Busy flag */
- while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
- {
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_TIMEOUT;
- }
-
- tmpreg1 = heth->Instance->MACMIIAR;
- }
-
- /* Get MACMIIDR value */
- *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
-
- /* Set ETH HAL State to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Writes to a PHY register.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
- * This parameter can be one of the following values:
- * PHY_BCR: Transceiver Control Register.
- * More PHY register could be written depending on the used PHY
- * @param RegValue: the value to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
-{
- uint32_t tmpreg1 = 0U;
- uint32_t tickstart = 0U;
-
- /* Check parameters */
- assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
-
- /* Check the ETH peripheral state */
- if(heth->State == HAL_ETH_STATE_BUSY_WR)
- {
- return HAL_BUSY;
- }
- /* Set ETH HAL State to BUSY_WR */
- heth->State = HAL_ETH_STATE_BUSY_WR;
-
- /* Get the ETHERNET MACMIIAR value */
- tmpreg1 = heth->Instance->MACMIIAR;
-
- /* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-
- /* Prepare the MII register address value */
- tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
- tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
-
- /* Give the value to the MII data register */
- heth->Instance->MACMIIDR = (uint16_t)RegValue;
-
- /* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg1;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check for the Busy flag */
- while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
- {
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- return HAL_TIMEOUT;
- }
-
- tmpreg1 = heth->Instance->MACMIIAR;
- }
-
- /* Set ETH HAL State to READY */
- heth->State = HAL_ETH_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Enable MAC and DMA transmission and reception.
- HAL_ETH_Start();
- (+) Disable MAC and DMA transmission and reception.
- HAL_ETH_Stop();
- (+) Set the MAC configuration in runtime mode
- HAL_ETH_ConfigMAC();
- (+) Set the DMA configuration in runtime mode
- HAL_ETH_ConfigDMA();
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Enables Ethernet MAC and DMA reception/transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
-{
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Enable transmit state machine of the MAC for transmission on the MII */
- ETH_MACTransmissionEnable(heth);
-
- /* Enable receive state machine of the MAC for reception from the MII */
- ETH_MACReceptionEnable(heth);
-
- /* Flush Transmit FIFO */
- ETH_FlushTransmitFIFO(heth);
-
- /* Start DMA transmission */
- ETH_DMATransmissionEnable(heth);
-
- /* Start DMA reception */
- ETH_DMAReceptionEnable(heth);
-
- /* Set the ETH state to READY*/
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop Ethernet MAC and DMA reception/transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
-{
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State = HAL_ETH_STATE_BUSY;
-
- /* Stop DMA transmission */
- ETH_DMATransmissionDisable(heth);
-
- /* Stop DMA reception */
- ETH_DMAReceptionDisable(heth);
-
- /* Disable receive state machine of the MAC for reception from the MII */
- ETH_MACReceptionDisable(heth);
-
- /* Flush Transmit FIFO */
- ETH_FlushTransmitFIFO(heth);
-
- /* Disable transmit state machine of the MAC for transmission on the MII */
- ETH_MACTransmissionDisable(heth);
-
- /* Set the ETH state*/
- heth->State = HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Set ETH MAC Configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param macconf: MAC Configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
-{
- uint32_t tmpreg1 = 0U;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State= HAL_ETH_STATE_BUSY;
-
- assert_param(IS_ETH_SPEED(heth->Init.Speed));
- assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
-
- if (macconf != NULL)
- {
- /* Check the parameters */
- assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
- assert_param(IS_ETH_JABBER(macconf->Jabber));
- assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
- assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
- assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
- assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
- assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
- assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
- assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
- assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
- assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
- assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
- assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
- assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
- assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
- assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
- assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
- assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
- assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
- assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
- assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
- assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
- assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
- assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
- assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
- assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
- assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
-
- /*------------------------ ETHERNET MACCR Configuration --------------------*/
- /* Get the ETHERNET MACCR value */
- tmpreg1 = (heth->Instance)->MACCR;
- /* Clear WD, PCE, PS, TE and RE bits */
- tmpreg1 &= ETH_MACCR_CLEAR_MASK;
-
- tmpreg1 |= (uint32_t)(macconf->Watchdog |
- macconf->Jabber |
- macconf->InterFrameGap |
- macconf->CarrierSense |
- (heth->Init).Speed |
- macconf->ReceiveOwn |
- macconf->LoopbackMode |
- (heth->Init).DuplexMode |
- macconf->ChecksumOffload |
- macconf->RetryTransmission |
- macconf->AutomaticPadCRCStrip |
- macconf->BackOffLimit |
- macconf->DeferralCheck);
-
- /* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account :
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-
- /*----------------------- ETHERNET MACFFR Configuration --------------------*/
- /* Write to ETHERNET MACFFR */
- (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
- macconf->SourceAddrFilter |
- macconf->PassControlFrames |
- macconf->BroadcastFramesReception |
- macconf->DestinationAddrFilter |
- macconf->PromiscuousMode |
- macconf->MulticastFramesFilter |
- macconf->UnicastFramesFilter);
-
- /* Wait until the write operation will be taken into account :
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACFFR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg1;
-
- /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
- /* Write to ETHERNET MACHTHR */
- (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
-
- /* Write to ETHERNET MACHTLR */
- (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
- /*----------------------- ETHERNET MACFCR Configuration --------------------*/
-
- /* Get the ETHERNET MACFCR value */
- tmpreg1 = (heth->Instance)->MACFCR;
- /* Clear xx bits */
- tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
-
- tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
- macconf->ZeroQuantaPause |
- macconf->PauseLowThreshold |
- macconf->UnicastPauseFrameDetect |
- macconf->ReceiveFlowControl |
- macconf->TransmitFlowControl);
-
- /* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account :
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACFCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg1;
-
- /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
- (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
- macconf->VLANTagIdentifier);
-
- /* Wait until the write operation will be taken into account :
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACVLANTR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg1;
- }
- else /* macconf == NULL : here we just configure Speed and Duplex mode */
- {
- /*------------------------ ETHERNET MACCR Configuration --------------------*/
- /* Get the ETHERNET MACCR value */
- tmpreg1 = (heth->Instance)->MACCR;
-
- /* Clear FES and DM bits */
- tmpreg1 &= ~(0x00004800U);
-
- tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
-
- /* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
- }
-
- /* Set the ETH state to Ready */
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets ETH DMA Configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param dmaconf: DMA Configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
-{
- uint32_t tmpreg1 = 0U;
-
- /* Process Locked */
- __HAL_LOCK(heth);
-
- /* Set the ETH peripheral state to BUSY */
- heth->State= HAL_ETH_STATE_BUSY;
-
- /* Check parameters */
- assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
- assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
- assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
- assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
- assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
- assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
- assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
- assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
- assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
- assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
- assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
- assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
- assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
- assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
- assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
-
- /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
- /* Get the ETHERNET DMAOMR value */
- tmpreg1 = (heth->Instance)->DMAOMR;
- /* Clear xx bits */
- tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
-
- tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
- dmaconf->ReceiveStoreForward |
- dmaconf->FlushReceivedFrame |
- dmaconf->TransmitStoreForward |
- dmaconf->TransmitThresholdControl |
- dmaconf->ForwardErrorFrames |
- dmaconf->ForwardUndersizedGoodFrames |
- dmaconf->ReceiveThresholdControl |
- dmaconf->SecondFrameOperate);
-
- /* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->DMAOMR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg1;
-
- /*----------------------- ETHERNET DMABMR Configuration --------------------*/
- (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
- dmaconf->FixedBurst |
- dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
- dmaconf->TxDMABurstLength |
- (dmaconf->DescriptorSkipLength << 2U) |
- dmaconf->DMAArbitration |
- ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->DMABMR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg1;
-
- /* Set the ETH state to Ready */
- heth->State= HAL_ETH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(heth);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
- @verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
- (+) Get the ETH handle state:
- HAL_ETH_GetState();
-
-
- @endverbatim
- * @{
- */
-
-/**
- * @brief Return the ETH HAL state
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval HAL state
- */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
-{
- /* Return ETH state */
- return heth->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup ETH_Private_Functions
- * @{
- */
-
-/**
- * @brief Configures Ethernet MAC and DMA with default parameters.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param err: Ethernet Init error
- * @retval HAL status
- */
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
-{
- ETH_MACInitTypeDef macinit;
- ETH_DMAInitTypeDef dmainit;
- uint32_t tmpreg1 = 0U;
-
- if (err != ETH_SUCCESS) /* Auto-negotiation failed */
- {
- /* Set Ethernet duplex mode to Full-duplex */
- (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
-
- /* Set Ethernet speed to 100M */
- (heth->Init).Speed = ETH_SPEED_100M;
- }
-
- /* Ethernet MAC default initialization **************************************/
- macinit.Watchdog = ETH_WATCHDOG_ENABLE;
- macinit.Jabber = ETH_JABBER_ENABLE;
- macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
- macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
- macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
- macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
- if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
- {
- macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
- }
- else
- {
- macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
- }
- macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
- macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
- macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
- macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
- macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
- macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
- macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
- macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
- macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
- macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
- macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
- macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
- macinit.HashTableHigh = 0x0U;
- macinit.HashTableLow = 0x0U;
- macinit.PauseTime = 0x0U;
- macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
- macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
- macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
- macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
- macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
- macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
- macinit.VLANTagIdentifier = 0x0U;
-
- /*------------------------ ETHERNET MACCR Configuration --------------------*/
- /* Get the ETHERNET MACCR value */
- tmpreg1 = (heth->Instance)->MACCR;
- /* Clear WD, PCE, PS, TE and RE bits */
- tmpreg1 &= ETH_MACCR_CLEAR_MASK;
- /* Set the WD bit according to ETH Watchdog value */
- /* Set the JD: bit according to ETH Jabber value */
- /* Set the IFG bit according to ETH InterFrameGap value */
- /* Set the DCRS bit according to ETH CarrierSense value */
- /* Set the FES bit according to ETH Speed value */
- /* Set the DO bit according to ETH ReceiveOwn value */
- /* Set the LM bit according to ETH LoopbackMode value */
- /* Set the DM bit according to ETH Mode value */
- /* Set the IPCO bit according to ETH ChecksumOffload value */
- /* Set the DR bit according to ETH RetryTransmission value */
- /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
- /* Set the BL bit according to ETH BackOffLimit value */
- /* Set the DC bit according to ETH DeferralCheck value */
- tmpreg1 |= (uint32_t)(macinit.Watchdog |
- macinit.Jabber |
- macinit.InterFrameGap |
- macinit.CarrierSense |
- (heth->Init).Speed |
- macinit.ReceiveOwn |
- macinit.LoopbackMode |
- (heth->Init).DuplexMode |
- macinit.ChecksumOffload |
- macinit.RetryTransmission |
- macinit.AutomaticPadCRCStrip |
- macinit.BackOffLimit |
- macinit.DeferralCheck);
-
- /* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-
- /*----------------------- ETHERNET MACFFR Configuration --------------------*/
- /* Set the RA bit according to ETH ReceiveAll value */
- /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
- /* Set the PCF bit according to ETH PassControlFrames value */
- /* Set the DBF bit according to ETH BroadcastFramesReception value */
- /* Set the DAIF bit according to ETH DestinationAddrFilter value */
- /* Set the PR bit according to ETH PromiscuousMode value */
- /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
- /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
- /* Write to ETHERNET MACFFR */
- (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
- macinit.SourceAddrFilter |
- macinit.PassControlFrames |
- macinit.BroadcastFramesReception |
- macinit.DestinationAddrFilter |
- macinit.PromiscuousMode |
- macinit.MulticastFramesFilter |
- macinit.UnicastFramesFilter);
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACFFR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg1;
-
- /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
- /* Write to ETHERNET MACHTHR */
- (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
-
- /* Write to ETHERNET MACHTLR */
- (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
- /*----------------------- ETHERNET MACFCR Configuration -------------------*/
-
- /* Get the ETHERNET MACFCR value */
- tmpreg1 = (heth->Instance)->MACFCR;
- /* Clear xx bits */
- tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
-
- /* Set the PT bit according to ETH PauseTime value */
- /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
- /* Set the PLT bit according to ETH PauseLowThreshold value */
- /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
- /* Set the RFE bit according to ETH ReceiveFlowControl value */
- /* Set the TFE bit according to ETH TransmitFlowControl value */
- tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
- macinit.ZeroQuantaPause |
- macinit.PauseLowThreshold |
- macinit.UnicastPauseFrameDetect |
- macinit.ReceiveFlowControl |
- macinit.TransmitFlowControl);
-
- /* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACFCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg1;
-
- /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
- /* Set the ETV bit according to ETH VLANTagComparison value */
- /* Set the VL bit according to ETH VLANTagIdentifier value */
- (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
- macinit.VLANTagIdentifier);
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACVLANTR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg1;
-
- /* Ethernet DMA default initialization ************************************/
- dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
- dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
- dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
- dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
- dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
- dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
- dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
- dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
- dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
- dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
- dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
- dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
- dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
- dmainit.DescriptorSkipLength = 0x0U;
- dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
-
- /* Get the ETHERNET DMAOMR value */
- tmpreg1 = (heth->Instance)->DMAOMR;
- /* Clear xx bits */
- tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
-
- /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
- /* Set the RSF bit according to ETH ReceiveStoreForward value */
- /* Set the DFF bit according to ETH FlushReceivedFrame value */
- /* Set the TSF bit according to ETH TransmitStoreForward value */
- /* Set the TTC bit according to ETH TransmitThresholdControl value */
- /* Set the FEF bit according to ETH ForwardErrorFrames value */
- /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
- /* Set the RTC bit according to ETH ReceiveThresholdControl value */
- /* Set the OSF bit according to ETH SecondFrameOperate value */
- tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
- dmainit.ReceiveStoreForward |
- dmainit.FlushReceivedFrame |
- dmainit.TransmitStoreForward |
- dmainit.TransmitThresholdControl |
- dmainit.ForwardErrorFrames |
- dmainit.ForwardUndersizedGoodFrames |
- dmainit.ReceiveThresholdControl |
- dmainit.SecondFrameOperate);
-
- /* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->DMAOMR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg1;
-
- /*----------------------- ETHERNET DMABMR Configuration ------------------*/
- /* Set the AAL bit according to ETH AddressAlignedBeats value */
- /* Set the FB bit according to ETH FixedBurst value */
- /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
- /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
- /* Set the DSL bit according to ETH DesciptorSkipLength value */
- /* Set the PR and DA bits according to ETH DMAArbitration value */
- (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
- dmainit.FixedBurst |
- dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
- dmainit.TxDMABurstLength |
- (dmainit.DescriptorSkipLength << 2U) |
- dmainit.DMAArbitration |
- ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->DMABMR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg1;
-
- if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
- {
- /* Enable the Ethernet Rx Interrupt */
- __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
- }
-
- /* Initialize MAC address in ethernet MAC */
- ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
-}
-
-/**
- * @brief Configures the selected MAC address.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param MacAddr: The MAC address to configure
- * This parameter can be one of the following values:
- * @arg ETH_MAC_Address0: MAC Address0
- * @arg ETH_MAC_Address1: MAC Address1
- * @arg ETH_MAC_Address2: MAC Address2
- * @arg ETH_MAC_Address3: MAC Address3
- * @param Addr: Pointer to MAC address buffer data (6 bytes)
- * @retval HAL status
- */
-static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
-{
- uint32_t tmpreg1;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
-
- /* Check the parameters */
- assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
-
- /* Calculate the selected MAC address high register */
- tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
- /* Load the selected MAC address high register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
- /* Calculate the selected MAC address low register */
- tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
-
- /* Load the selected MAC address low register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
-}
-
-/**
- * @brief Enables the MAC transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
-{
- __IO uint32_t tmpreg1 = 0U;
-
- /* Enable the MAC transmission */
- (heth->Instance)->MACCR |= ETH_MACCR_TE;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- ETH_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-}
-
-/**
- * @brief Disables the MAC transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
-{
- __IO uint32_t tmpreg1 = 0U;
-
- /* Disable the MAC transmission */
- (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- ETH_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-}
-
-/**
- * @brief Enables the MAC reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
-{
- __IO uint32_t tmpreg1 = 0U;
-
- /* Enable the MAC reception */
- (heth->Instance)->MACCR |= ETH_MACCR_RE;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- ETH_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-}
-
-/**
- * @brief Disables the MAC reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
-{
- __IO uint32_t tmpreg1 = 0U;
-
- /* Disable the MAC reception */
- (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->MACCR;
- ETH_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg1;
-}
-
-/**
- * @brief Enables the DMA transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
-{
- /* Enable the DMA transmission */
- (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
-}
-
-/**
- * @brief Disables the DMA transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
-{
- /* Disable the DMA transmission */
- (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
-}
-
-/**
- * @brief Enables the DMA reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
-{
- /* Enable the DMA reception */
- (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
-}
-
-/**
- * @brief Disables the DMA reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
-{
- /* Disable the DMA reception */
- (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
-}
-
-/**
- * @brief Clears the ETHERNET transmit FIFO.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
-{
- __IO uint32_t tmpreg1 = 0U;
-
- /* Set the Flush Transmit FIFO bit */
- (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
-
- /* Wait until the write operation will be taken into account:
- at least four TX_CLK/RX_CLK clock cycles */
- tmpreg1 = (heth->Instance)->DMAOMR;
- ETH_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg1;
-}
-
-/**
- * @brief This function provides delay (in milliseconds) based on CPU cycles method.
- * @param mdelay: specifies the delay time length, in milliseconds.
- * @retval None
- */
-static void ETH_Delay(uint32_t mdelay)
-{
- __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
- do
- {
- __NOP();
- }
- while (Delay --);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_ETH_MODULE_ENABLED */
-/**
- * @}
- */
-
-#endif /* STM32F107xC */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_flash.c b/lib/hal-stm32f1/source/stm32f1xx_hal_flash.c deleted file mode 100644 index 23c00164..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_flash.c +++ /dev/null @@ -1,980 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief FLASH HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the internal FLASH memory:
- * + Program operations functions
- * + Memory Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### FLASH peripheral features #####
- ==============================================================================
- [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
- to the Flash memory. It implements the erase and program Flash memory operations
- and the read and write protection mechanisms.
-
- [..] The Flash memory interface accelerates code execution with a system of instruction
- prefetch.
-
- [..] The FLASH main features are:
- (+) Flash memory read operations
- (+) Flash memory program/erase operations
- (+) Read / write protections
- (+) Prefetch on I-Code
- (+) Option Bytes programming
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver provides functions and macros to configure and program the FLASH
- memory of all STM32F1xx devices.
-
- (#) FLASH Memory I/O Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the FLASH interface
- (++) Erase function: Erase page, erase all pages
- (++) Program functions: half word, word and doubleword
- (#) FLASH Option Bytes Programming functions: this group includes all needed
- functions to manage the Option Bytes:
- (++) Lock and Unlock the Option Bytes
- (++) Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user Option Bytes
- (++) Launch the Option Bytes loader
- (++) Erase Option Bytes
- (++) Program the data Option Bytes
- (++) Get the Write protection.
- (++) Get the user option bytes.
-
- (#) Interrupts and flags management functions : this group
- includes all needed functions to:
- (++) Handle FLASH interrupts
- (++) Wait for last FLASH operation according to its status
- (++) Get error flag status
-
- [..] In addition to these function, this driver includes a set of macros allowing
- to handle the following operations:
-
- (+) Set/Get the latency
- (+) Enable/Disable the prefetch buffer
- (+) Enable/Disable the half cycle access
- (+) Enable/Disable the FLASH interrupts
- (+) Monitor the FLASH flags status
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
- * @brief FLASH HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro ---------------------------- ---------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void FLASH_SetErrorCode(void);
-extern void FLASH_PageErase(uint32_t PageAddress);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
- * @{
- */
-
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
-@verbatim
-@endverbatim
- * @{
- */
-
-/**
- * @brief Program halfword, word or double word at a specified address
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @note FLASH should be previously erased before new programmation (only exception to this
- * is when 0x0000 is programmed)
- *
- * @param TypeProgram: Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint8_t index = 0;
- uint8_t nbiterations = 0;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_BANK2_END */
-
- if(status == HAL_OK)
- {
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- /* Program halfword (16-bit) at a specified address. */
- nbiterations = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- /* Program word (32-bit = 2*16-bit) at a specified address. */
- nbiterations = 2U;
- }
- else
- {
- /* Program double word (64-bit = 4*16-bit) at a specified address. */
- nbiterations = 4U;
- }
-
- for (index = 0U; index < nbiterations; index++)
- {
- FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
- }
-#endif /* FLASH_BANK2_END */
- /* In case of error, stop programation procedure */
- if (status != HAL_OK)
- {
- break;
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Program halfword, word or double word at a specified address with interrupt enabled.
- * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
- *
- * @note If an erase and a program operations are requested simultaneously,
- * the erase operation is performed before the program one.
- *
- * @param TypeProgram: Indicate the way to program at a specified address.
- * This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-#if defined(FLASH_BANK2_END)
- /* If procedure already ongoing, reject the next one */
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- return HAL_ERROR;
- }
-
- if(Address <= FLASH_BANK1_END)
- {
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
-
- }else
- {
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
- }
-#else
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-#endif /* FLASH_BANK2_END */
-
- pFlash.Address = Address;
- pFlash.Data = Data;
-
- if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
- /* Program halfword (16-bit) at a specified address. */
- pFlash.DataRemaining = 1U;
- }
- else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
- /* Program word (32-bit : 2*16-bit) at a specified address. */
- pFlash.DataRemaining = 2U;
- }
- else
- {
- pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
- /* Program double word (64-bit : 4*16-bit) at a specified address. */
- pFlash.DataRemaining = 4U;
- }
-
- /* Program halfword (16-bit) at a specified address. */
- FLASH_Program_HalfWord(Address, (uint16_t)Data);
-
- return status;
-}
-
-/**
- * @brief This function handles FLASH interrupt request.
- * @retval None
- */
-void HAL_FLASH_IRQHandler(void)
-{
- uint32_t addresstmp = 0U;
-
- /* Check FLASH operation error flags */
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
- (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
-#endif /* FLASH_BANK2_END */
- {
- /* Return the faulty address */
- addresstmp = pFlash.Address;
- /* Reset address */
- pFlash.Address = 0xFFFFFFFFU;
-
- /* Save the Error code */
- FLASH_SetErrorCode();
-
- /* FLASH error interrupt user callback */
- HAL_FLASH_OperationErrorCallback(addresstmp);
-
- /* Stop the procedure ongoing */
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-
- /* Check FLASH End of Operation flag */
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-#endif /* FLASH_BANK2_END */
-
- /* Process can continue only if no error detected */
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still pages to erase */
- if(pFlash.DataRemaining != 0U)
- {
- addresstmp = pFlash.Address;
- /*Indicate user which sector has been erased */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
-
- /*Increment sector number*/
- addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
- pFlash.Address = addresstmp;
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /* No more pages to Erase, user callback can be called. */
- /* Reset Sector and stop Erase pages procedure */
- pFlash.Address = addresstmp = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(addresstmp);
- }
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /* Operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
-
-#if defined(FLASH_BANK2_END)
- /* Stop Mass Erase procedure if no pending mass erase on other bank */
- if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
- {
-#endif /* FLASH_BANK2_END */
- /* MassErase ended. Return the selected bank */
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0U);
-
- /* Stop Mass Erase procedure*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0U)
- {
- /* Increment address to 16-bit */
- pFlash.Address += 2U;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16U);
-
- /* Operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /* Program ended. Return the selected address */
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
- }
- else
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
- }
-
- /* Reset Address and stop Program procedure */
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- }
- }
-
-#if defined(FLASH_BANK2_END)
- /* Check FLASH End of Operation flag */
- if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
-
- /* Process can continue only if no error detected */
- if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still pages to erase*/
- if(pFlash.DataRemaining != 0U)
- {
- /* Indicate user which page address has been erased*/
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-
- /* Increment page address to next page */
- pFlash.Address += FLASH_PAGE_SIZE;
- addresstmp = pFlash.Address;
-
- /* Operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
-
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /*No more pages to Erase*/
-
- /*Reset Address and stop Erase pages procedure*/
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
- /* Operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
-
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
- {
- /* MassErase ended. Return the selected bank*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0U);
-
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0U)
- {
- /* Increment address to 16-bit */
- pFlash.Address += 2U;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16U);
-
- /* Operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
-
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /*Program ended. Return the selected address*/
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- }
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);
- }
- else
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);
- }
-
- /* Reset Address and stop Program procedure*/
- pFlash.Address = 0xFFFFFFFFU;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- }
- }
- }
-#endif
-
- if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
- {
-#if defined(FLASH_BANK2_END)
- /* Operation is completed, disable the PG, PER and MER Bits for both bank */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
- CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
-
- /* Disable End of FLASH Operation and Error source interrupts for both banks */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
-#else
- /* Operation is completed, disable the PG, PER and MER Bits */
- CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
-
- /* Disable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-#endif /* FLASH_BANK2_END */
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- }
-}
-
-/**
- * @brief FLASH end of operation interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief FLASH operation error interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: No return value expected
- * - Pages Erase: Address of the page which returned an error
- * - Program: Address which was selected for data program
- * @retval none
- */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(ReturnValue);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- memory operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlock the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
- if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
- {
- /* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
-#if defined(FLASH_BANK2_END)
- if (HAL_IS_BIT_SET(FLASH->CR2, FLASH_CR2_LOCK))
- {
- /* Authorize the FLASH BANK2 Registers access */
- WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
- WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
-#endif /* FLASH_BANK2_END */
- return HAL_OK;
-}
-
-/**
- * @brief Locks the FLASH control register access
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH Registers access */
- SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-
-#if defined(FLASH_BANK2_END)
- /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
- SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
-
-#endif /* FLASH_BANK2_END */
- return HAL_OK;
-}
-
-/**
- * @brief Unlock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
- if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
- {
- /* Authorizes the Option Byte register programming */
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
- WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
- }
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Lock the FLASH Option Control Registers access.
- * @retval HAL Status
- */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
- /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @note This function will reset automatically the MCU.
- * @retval None
- */
-void HAL_FLASH_OB_Launch(void)
-{
- /* Initiates a system reset request to launch the option byte loading */
- HAL_NVIC_SystemReset();
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
- * @brief Peripheral errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Errors functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time errors of the FLASH peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode The returned value can be:
- * @ref FLASH_Error_Codes
- */
-uint32_t HAL_FLASH_GetError(void)
-{
- return pFlash.ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Program a half-word (16-bit) at a specified address.
- * @param Address specify the address to be programmed.
- * @param Data specify the data to be programmed.
- * @retval None
- */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(Address <= FLASH_BANK1_END)
- {
-#endif /* FLASH_BANK2_END */
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-#if defined(FLASH_BANK2_END)
- }
- else
- {
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR2, FLASH_CR2_PG);
- }
-#endif /* FLASH_BANK2_END */
-
- /* Write data in the address */
- *(__IO uint16_t*)Address = Data;
-}
-
-/**
- * @brief Wait for a FLASH operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
- __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
- {
- /*Save the error code*/
- FLASH_SetErrorCode();
- return HAL_ERROR;
- }
-
- /* There is no error flag set */
- return HAL_OK;
-}
-
-#if defined(FLASH_BANK2_END)
-/**
- * @brief Wait for a FLASH BANK2 operation to complete.
- * @param Timeout maximum flash operation timeout
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
-{
- /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
- Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
- flag will be set */
-
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Check FLASH End of Operation flag */
- if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
- {
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
- }
-
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
- {
- /*Save the error code*/
- FLASH_SetErrorCode();
- return HAL_ERROR;
- }
-
- /* If there is an error flag set */
- return HAL_OK;
-
-}
-#endif /* FLASH_BANK2_END */
-
-/**
- * @brief Set the specific FLASH error flag.
- * @retval None
- */
-static void FLASH_SetErrorCode(void)
-{
- uint32_t flags = 0U;
-
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
-#endif /* FLASH_BANK2_END */
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-#if defined(FLASH_BANK2_END)
- flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
-#else
- flags |= FLASH_FLAG_WRPERR;
-#endif /* FLASH_BANK2_END */
- }
-#if defined(FLASH_BANK2_END)
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
-#else
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
-#endif /* FLASH_BANK2_END */
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
-#if defined(FLASH_BANK2_END)
- flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
-#else
- flags |= FLASH_FLAG_PGERR;
-#endif /* FLASH_BANK2_END */
- }
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
- }
-
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(flags);
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_flash_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_flash_ex.c deleted file mode 100644 index e075711b..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_flash_ex.c +++ /dev/null @@ -1,1145 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief Extended FLASH HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * + Extended Initialization/de-initialization functions
- * + Extended I/O operation functions
- * + Extended Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### Flash peripheral extended features #####
- ==============================================================================
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the FLASH memory
- of all STM32F1xxx devices. It includes
-
- (++) Set/Reset the write protection
- (++) Program the user Option Bytes
- (++) Get the Read protection Level
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @addtogroup FLASH
- * @{
- */
-/** @addtogroup FLASH_Private_Variables
- * @{
- */
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx FLASHEx
- * @brief FLASH HAL Extension module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
- * @{
- */
-#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
-#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
-#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
-/* Erase operations */
-static void FLASH_MassErase(uint32_t Banks);
-void FLASH_PageErase(uint32_t PageAddress);
-
-/* Option bytes control */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
-static uint32_t FLASH_OB_GetWRP(void);
-static uint32_t FLASH_OB_GetRDP(void);
-static uint8_t FLASH_OB_GetUser(void);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
- * @{
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
- * @brief FLASH Memory Erasing functions
- *
-@verbatim
- ==============================================================================
- ##### FLASH Erasing Programming functions #####
- ==============================================================================
-
- [..] The FLASH Memory Erasing functions, includes the following functions:
- (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
- (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
- is called with parameter 0xFFFFFFFF
-
- [..] Any operation of erase should follow these steps:
- (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
- program memory access.
- (#) Call the desired function to erase page.
- (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
- (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @param[out] PageError pointer to variable that
- * contains the configuration information on faulty page in case of error
- * (0xFFFFFFFF means that all the pages have been correctly erased)
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t address = 0U;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
-#if defined(FLASH_BANK2_END)
- if (pEraseInit->Banks == FLASH_BANK_BOTH)
- {
- /* Mass Erase requested for Bank1 and Bank2 */
- /* Wait for last operation to be completed */
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_BOTH);
-
- /* Wait for last operation to be completed */
- if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
- (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
- {
- status = HAL_OK;
- }
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
- }
- }
- else if (pEraseInit->Banks == FLASH_BANK_2)
- {
- /* Mass Erase requested for Bank2 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_2);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
- }
- }
- else
-#endif /* FLASH_BANK2_END */
- {
- /* Mass Erase requested for Bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Mass erase to be done*/
- FLASH_MassErase(FLASH_BANK_1);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- }
- }
- }
- else
- {
- /* Page Erase is requested */
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
-#if defined(FLASH_BANK2_END)
- /* Page Erase requested on address located on bank2 */
- if(pEraseInit->PageAddress > FLASH_BANK1_END)
- {
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- /* Erase by page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
- address += FLASH_PAGE_SIZE)
- {
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
- }
- }
- }
- }
- else
-#endif /* FLASH_BANK2_END */
- {
- /* Page Erase requested on address located on bank1 */
- /* Wait for last operation to be completed */
- if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
- {
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFFU;
-
- /* Erase page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
- address += FLASH_PAGE_SIZE)
- {
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- if (status != HAL_OK)
- {
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
- }
- }
- }
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
- * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
- * must be called before.
- * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
- * (recommended to protect the FLASH memory against possible unwanted operation)
- * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
- * contains the configuration information for the erasing.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* If procedure already ongoing, reject the next one */
- if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-
-#if defined(FLASH_BANK2_END)
- /* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
-
-#endif
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
- FLASH_MassErase(pEraseInit->Banks);
- }
- else
- {
- /* Erase by page to be done*/
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
- pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
- pFlash.DataRemaining = pEraseInit->NbPages;
- pFlash.Address = pEraseInit->PageAddress;
-
- /*Erase 1st page and wait for IT*/
- FLASH_PageErase(pEraseInit->PageAddress);
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ==============================================================================
- ##### Option Bytes Programming functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the FLASH
- option bytes operations.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
- * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
-{
- uint8_t rdptmp = OB_RDP_LEVEL_0;
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Get the actual read protection Option Byte value */
- rdptmp = FLASH_OB_GetRDP();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Restore the last read protection Option Byte value */
- status = FLASH_OB_RDP_LevelConfig(rdptmp);
- }
- }
-
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Program option bytes
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- *
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval HAL_StatusTypeDef HAL Status
- */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Process Locked */
- __HAL_LOCK(&pFlash);
-
- /* Check the parameters */
- assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
- /* Write protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
- {
- assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
- {
- /* Enable of Write protection on the selected page */
- status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
- }
- else
- {
- /* Disable of Write protection on the selected page */
- status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
- }
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Read protection configuration */
- if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
- {
- status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* USER configuration */
- if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
- {
- status = FLASH_OB_UserConfig(pOBInit->USERConfig);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* DATA configuration*/
- if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
- {
- status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
- if (status != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
- return status;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(&pFlash);
-
- return status;
-}
-
-/**
- * @brief Get the Option byte configuration
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
- * contains the configuration information for the programming.
- *
- * @retval None
- */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
- pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
-
- /*Get WRP*/
- pOBInit->WRPPage = FLASH_OB_GetWRP();
-
- /*Get RDP Level*/
- pOBInit->RDPLevel = FLASH_OB_GetRDP();
-
- /*Get USER*/
- pOBInit->USERConfig = FLASH_OB_GetUser();
-}
-
-/**
- * @brief Get the Option byte user data
- * @param DATAAdress Address of the option byte DATA
- * This parameter can be one of the following values:
- * @arg @ref OB_DATA_ADDRESS_DATA0
- * @arg @ref OB_DATA_ADDRESS_DATA1
- * @retval Value programmed in USER data
- */
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
-{
- uint32_t value = 0;
-
- if (DATAAdress == OB_DATA_ADDRESS_DATA0)
- {
- /* Get value programmed in OB USER Data0 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
- }
- else
- {
- /* Get value programmed in OB USER Data1 */
- value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
- }
-
- return value;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Full erase of FLASH memory Bank
- * @param Banks Banks to be erased
- * This parameter can be one of the following values:
- * @arg @ref FLASH_BANK_1 Bank1 to be erased
- @if STM32F101xG
- * @arg @ref FLASH_BANK_2 Bank2 to be erased
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
- @endif
- @if STM32F103xG
- * @arg @ref FLASH_BANK_2 Bank2 to be erased
- * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
- @endif
- *
- * @retval None
- */
-static void FLASH_MassErase(uint32_t Banks)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_BANK(Banks));
-
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(Banks == FLASH_BANK_BOTH)
- {
- /* bank1 & bank2 will be erased*/
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else if(Banks == FLASH_BANK_2)
- {
- /*Only bank2 will be erased*/
- SET_BIT(FLASH->CR2, FLASH_CR2_MER);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else
- {
-#endif /* FLASH_BANK2_END */
-#if !defined(FLASH_BANK2_END)
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Banks);
-#endif /* FLASH_BANK2_END */
- /* Only bank1 will be erased*/
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
-}
-
-/**
- * @brief Enable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write protected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
-#if defined(FLASH_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
-#endif /* FLASH_WRP1_WRP1 */
-#if defined(FLASH_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
-#endif /* FLASH_WRP2_WRP2 */
-#if defined(FLASH_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
-#endif /* FLASH_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be protected ******/
- WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#elif defined(OB_WRP_PAGES0TO31MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
-#endif /* OB_WRP_PAGES64TO95MASK */
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#endif /* OB_WRP_PAGES96TO127MASK */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- /* Enable write protection */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 &= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP0_WRP0 */
-
-#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 &= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP1_WRP1 */
-
-#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 &= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP2_WRP2 */
-
-#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 &= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Disable the write protection of the desired pages
- * @note An option byte erase is done automatically in this function.
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WriteProtectPage specifies the page(s) to be write unprotected.
- * The value of this parameter depend on device used within the same series
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
-{
- HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
-#if defined(FLASH_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
-#endif /* FLASH_WRP1_WRP1 */
-#if defined(FLASH_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
-#endif /* FLASH_WRP2_WRP2 */
-#if defined(FLASH_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
-#endif /* FLASH_WRP3_WRP3 */
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(WriteProtectPage));
-
- /* Get current write protected pages and the new pages to be unprotected ******/
- WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
-
-#if defined(OB_WRP_PAGES0TO15MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
-#elif defined(OB_WRP_PAGES0TO31MASK)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#endif /* OB_WRP_PAGES0TO31MASK */
-
-#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
-#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
-#endif /* OB_WRP_PAGES32TO63MASK */
-
-#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
-#endif /* OB_WRP_PAGES64TO95MASK */
-#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
-#endif /* OB_WRP_PAGES32TO47MASK */
-
-#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
-#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
-#endif /* OB_WRP_PAGES96TO127MASK */
-
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* To be able to write again option byte, need to perform a option byte erase */
- status = HAL_FLASHEx_OBErase();
- if (status == HAL_OK)
- {
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFFU)
- {
- OB->WRP0 |= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP0_WRP0 */
-
-#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFFU))
- {
- OB->WRP1 |= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP1_WRP1 */
-
-#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFFU))
- {
- OB->WRP2 |= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP2_WRP2 */
-
-#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFFU))
- {
- OB->WRP3 |= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- }
-#endif /* FLASH_WRP3_WRP3 */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
- return status;
-}
-
-/**
- * @brief Set the read protection level.
- * @param ReadProtectLevel specifies the read protection level.
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* If the previous operation is completed, proceed to erase the option bytes */
- SET_BIT(FLASH->CR, FLASH_CR_OPTER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the OPTER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
-
- if(status == HAL_OK)
- {
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
- WRITE_REG(OB->RDP, ReadProtectLevel);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- }
-
- return status;
-}
-
-/**
- * @brief Program the FLASH User Option Byte.
- * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
- * And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
- assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
- assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
-#if defined(FLASH_BANK2_END)
- assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
-#endif /* FLASH_BANK2_END */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(FLASH_BANK2_END)
- OB->USER = (UserConfig | 0xF0U);
-#else
- OB->USER = (UserConfig | 0x88U);
-#endif /* FLASH_BANK2_END */
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
-
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
- * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
- * (system reset will occur)
- * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param Address specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data specifies the data to be programmed.
- * @retval HAL status
- */
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
-{
- HAL_StatusTypeDef status = HAL_ERROR;
-
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
- /* Enables the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- /* If the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- * @retval The FLASH Write Protection Option Bytes value
- */
-static uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(READ_REG(FLASH->WRPR));
-}
-
-/**
- * @brief Returns the FLASH Read Protection level.
- * @retval FLASH RDP level
- * This parameter can be one of the following values:
- * @arg @ref OB_RDP_LEVEL_0 No protection
- * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
- */
-static uint32_t FLASH_OB_GetRDP(void)
-{
- uint32_t readstatus = OB_RDP_LEVEL_0;
- uint32_t tmp_reg = 0U;
-
- /* Read RDP level bits */
- tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
-
- if (tmp_reg == FLASH_OBR_RDPRT)
- {
- readstatus = OB_RDP_LEVEL_1;
- }
- else
- {
- readstatus = OB_RDP_LEVEL_0;
- }
-
- return readstatus;
-}
-
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
- * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
- * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
- */
-static uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-
-/**
- * @brief Erase the specified FLASH memory page
- * @param PageAddress FLASH page to erase
- * The value of this parameter depend on device used within the same series
- *
- * @retval None
- */
-void FLASH_PageErase(uint32_t PageAddress)
-{
- /* Clean the error context */
- pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-
-#if defined(FLASH_BANK2_END)
- if(PageAddress > FLASH_BANK1_END)
- {
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR2, FLASH_CR2_PER);
- WRITE_REG(FLASH->AR2, PageAddress);
- SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
- }
- else
- {
-#endif /* FLASH_BANK2_END */
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- WRITE_REG(FLASH->AR, PageAddress);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-#if defined(FLASH_BANK2_END)
- }
-#endif /* FLASH_BANK2_END */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_gpio.c b/lib/hal-stm32f1/source/stm32f1xx_hal_gpio.c deleted file mode 100644 index 043474a2..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_gpio.c +++ /dev/null @@ -1,597 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral features #####
- ==============================================================================
- [..]
- Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
- port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
- in several modes:
- (+) Input mode
- (+) Analog mode
- (+) Output mode
- (+) Alternate function mode
- (+) External interrupt/event lines
-
- [..]
- During and just after reset, the alternate functions and external interrupt
- lines are not active and the I/O ports are configured in input floating mode.
-
- [..]
- All GPIO pins have weak internal pull-up and pull-down resistors, which can be
- activated or not.
-
- [..]
- In Output or Alternate mode, each IO can be configured on open-drain or push-pull
- type and the IO speed can be selected depending on the VDD value.
-
- [..]
- All ports have external interrupt/event capability. To use external interrupt
- lines, the port must be configured in input mode. All available GPIO pins are
- connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
- [..]
- The external interrupt/event controller consists of up to 20 edge detectors in connectivity
- line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
- Each input line can be independently configured to select the type (event or interrupt) and
- the corresponding trigger event (rising or falling or both). Each line can also masked
- independently. A pending register maintains the status line of the interrupt requests
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
-
- (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
- (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
- (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
- structure.
- (++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure
- (++) Analog mode is required when a pin is to be used as ADC channel
- or DAC output.
- (++) In case of external interrupt/event selection the "Mode" member from
- GPIO_InitTypeDef structure select the type (interrupt or event) and
- the corresponding trigger event (rising or falling or both).
-
- (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
- mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
- HAL_NVIC_EnableIRQ().
-
- (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-
- (#) To set/reset the level of a pin configured in output mode use
- HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-
- (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
- (#) During and just after reset, the alternate functions are not
- active and the GPIO pins are configured in input floating mode (except JTAG
- pins).
-
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
- priority over the GPIO function.
-
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
- The HSE has priority over the GPIO function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIO GPIO
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE 0x00000003U
-#define EXTI_MODE 0x10000000U
-#define GPIO_MODE_IT 0x00010000U
-#define GPIO_MODE_EVT 0x00020000U
-#define RISING_EDGE 0x00100000U
-#define FALLING_EDGE 0x00200000U
-#define GPIO_OUTPUT_TYPE 0x00000010U
-
-#define GPIO_NUMBER 16U
-
-/* Definitions for bit manipulation of CRL and CRH register */
-#define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */
-#define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */
-#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */
-#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */
-#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */
-#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */
-#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */
-#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */
-
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to initialize and de-initialize the GPIOs
- to be ready for use.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- uint32_t position;
- uint32_t ioposition = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t temp = 0x00U;
- uint32_t config = 0x00U;
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
- /* Configure the port pins */
- for (position = 0U; position < GPIO_NUMBER; position++)
- {
- /* Get the IO position */
- ioposition = (0x01U << position);
-
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
- if (iocurrent == ioposition)
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-
- /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
- switch (GPIO_Init->Mode)
- {
- /* If we are configuring the pin in OUTPUT push-pull mode */
- case GPIO_MODE_OUTPUT_PP:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
- break;
-
- /* If we are configuring the pin in OUTPUT open-drain mode */
- case GPIO_MODE_OUTPUT_OD:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
- break;
-
- /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
- case GPIO_MODE_AF_PP:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
- break;
-
- /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
- case GPIO_MODE_AF_OD:
- /* Check the GPIO speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
- break;
-
- /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
- case GPIO_MODE_INPUT:
- case GPIO_MODE_IT_RISING:
- case GPIO_MODE_IT_FALLING:
- case GPIO_MODE_IT_RISING_FALLING:
- case GPIO_MODE_EVT_RISING:
- case GPIO_MODE_EVT_FALLING:
- case GPIO_MODE_EVT_RISING_FALLING:
- /* Check the GPIO pull parameter */
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
- if(GPIO_Init->Pull == GPIO_NOPULL)
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
- }
- else if(GPIO_Init->Pull == GPIO_PULLUP)
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
-
- /* Set the corresponding ODR bit */
- GPIOx->BSRR = ioposition;
- }
- else /* GPIO_PULLDOWN */
- {
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
-
- /* Reset the corresponding ODR bit */
- GPIOx->BRR = ioposition;
- }
- break;
-
- /* If we are configuring the pin in INPUT analog mode */
- case GPIO_MODE_ANALOG:
- config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
- break;
-
- /* Parameters are checked with assert_param */
- default:
- break;
- }
-
- /* Check if the current bit belongs to first half or last half of the pin count number
- in order to address CRH or CRL register*/
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
-
- /* Apply the new configuration of the pin to the register */
- MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- {
- /* Enable AFIO Clock */
- __HAL_RCC_AFIO_CLK_ENABLE();
- temp = AFIO->EXTICR[position >> 2U];
- CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
- SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
- AFIO->EXTICR[position >> 2U] = temp;
-
-
- /* Configure the interrupt mask */
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- SET_BIT(EXTI->IMR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->IMR, iocurrent);
- }
-
- /* Configure the event mask */
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- SET_BIT(EXTI->EMR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->EMR, iocurrent);
- }
-
- /* Enable or disable the rising trigger */
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- {
- SET_BIT(EXTI->RTSR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->RTSR, iocurrent);
- }
-
- /* Enable or disable the falling trigger */
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- {
- SET_BIT(EXTI->FTSR, iocurrent);
- }
- else
- {
- CLEAR_BIT(EXTI->FTSR, iocurrent);
- }
- }
- }
- }
-}
-
-/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @retval None
- */
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
-{
- uint32_t position = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t tmp = 0x00U;
- __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset = 0U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Configure the port pins */
- while ((GPIO_Pin >> position) != 0U)
- {
- /* Get current io position */
- iocurrent = (GPIO_Pin) & (1U << position);
-
- if (iocurrent)
- {
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Check if the current bit belongs to first half or last half of the pin count number
- in order to address CRH or CRL register */
- configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
-
- /* CRL/CRH default value is floating input(0x04) shifted to correct position */
- MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
-
- /* ODR default value is 0 */
- CLEAR_BIT(GPIOx->ODR, iocurrent);
-
- /*------------------------- EXTI Mode Configuration --------------------*/
- /* Clear the External Interrupt or Event for the current IO */
-
- tmp = AFIO->EXTICR[position >> 2U];
- tmp &= 0x0FU << (4U * (position & 0x03U));
- if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
- {
- tmp = 0x0FU << (4U * (position & 0x03U));
- CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
-
- /* Clear EXTI line configuration */
- CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
- }
- }
-
- position++;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the GPIOs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to read.
- * This parameter can be GPIO_PIN_x where x can be (0..15).
- * @retval The input port pin value.
- */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIO_PinState bitstatus;
-
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
- {
- bitstatus = GPIO_PIN_SET;
- }
- else
- {
- bitstatus = GPIO_PIN_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- *
- * @note This function uses GPIOx_BSRR register to allow atomic read/modify
- * accesses. In this way, there is no risk of an IRQ occurring between
- * the read and the modify access.
- *
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @param PinState: specifies the value to be written to the selected bit.
- * This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_BIT_RESET: to clear the port pin
- * @arg GPIO_BIT_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
- }
-}
-
-/**
- * @brief Toggles the specified GPIO pin
- * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
- * @param GPIO_Pin: Specifies the pins to be toggled.
- * @retval None
- */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-* @brief Locks GPIO Pins configuration registers.
-* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
-* has been applied on a port bit, it is no longer possible to modify the value of the port bit until
-* the next reset.
-* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
-* @param GPIO_Pin: specifies the port bit to be locked.
-* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-* @retval None
-*/
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- /* Apply lock key write sequence */
- SET_BIT(tmp, GPIO_Pin);
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
- tmp = GPIOx->LCKR;
-
- if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin: Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- }
-}
-
-/**
- * @brief EXTI line detection callbacks.
- * @param GPIO_Pin: Specifies the pins connected EXTI line
- * @retval None
- */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(GPIO_Pin);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_gpio_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_gpio_ex.c deleted file mode 100644 index 77cc9cb2..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_gpio_ex.c +++ /dev/null @@ -1,145 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief GPIO Extension HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
- * + Extended features functions
- *
- @verbatim
- ==============================================================================
- ##### GPIO Peripheral extension features #####
- ==============================================================================
- [..] GPIO module on STM32F1 family, manage also the AFIO register:
- (+) Possibility to use the EVENTOUT Cortex feature
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to use EVENTOUT Cortex feature
- (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
- (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
- (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @brief GPIO HAL module driver
- * @{
- */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
- * @{
- */
-
-/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
- (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
- (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
- * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
- * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
- * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
- * @retval None
- */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
-{
- /* Verify the parameters */
- assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
- assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
-
- /* Apply the new configuration */
- MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource));
-}
-
-/**
- * @brief Enables the Event Output.
- * @retval None
- */
-void HAL_GPIOEx_EnableEventout(void)
-{
- SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @brief Disables the Event Output.
- * @retval None
- */
-void HAL_GPIOEx_DisableEventout(void)
-{
- CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_hcd.c b/lib/hal-stm32f1/source/stm32f1xx_hal_hcd.c deleted file mode 100644 index 48a133b4..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_hcd.c +++ /dev/null @@ -1,1196 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_hcd.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief HCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#)Declare a HCD_HandleTypeDef handle structure, for example:
- HCD_HandleTypeDef hhcd;
-
- (#)Fill parameters of Init structure in HCD handle
-
- (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
-
- (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
- (##) Enable the HCD/USB Low Level interface clock using the following macro
- (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
-
- (##) Initialize the related GPIO clocks
- (##) Configure HCD pin-out
- (##) Configure HCD NVIC interrupt
-
- (#)Associate the Upper USB Host stack to the HAL HCD Driver:
- (##) hhcd.pData = phost;
-
- (#)Enable HCD transmission and reception:
- (##) HAL_HCD_Start();
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-
-#ifdef HAL_HCD_MODULE_ENABLED
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @defgroup HCD HCD
- * @brief HCD HAL module driver
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function ----------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
-static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Functions HCD Exported Functions
- * @{
- */
-
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the host driver
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
-{
- /* Check the HCD handle allocation */
- if(hhcd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
-
- if(hhcd->State == HAL_HCD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hhcd->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_HCD_MspInit(hhcd);
- }
-
- hhcd->State = HAL_HCD_STATE_BUSY;
-
- /* Disable the Interrupts */
- __HAL_HCD_DISABLE(hhcd);
-
- /* Init the Core (common init.) */
- USB_CoreInit(hhcd->Instance, hhcd->Init);
-
- /* Force Host Mode*/
- USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE);
-
- /* Init Host */
- USB_HostInit(hhcd->Instance, hhcd->Init);
-
- hhcd->State= HAL_HCD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize a host channel
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @param epnum: Endpoint number.
- * This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
- * This parameter can be a value from 0 to 255
- * @param speed: Current device speed.
- * This parameter can be one of these values:
- * HCD_SPEED_FULL: Full speed mode,
- * HCD_SPEED_LOW: Low speed mode
- * @param ep_type: Endpoint Type.
- * This parameter can be one of these values:
- * EP_TYPE_CTRL: Control type,
- * EP_TYPE_ISOC: Isochronous type,
- * EP_TYPE_BULK: Bulk type,
- * EP_TYPE_INTR: Interrupt type
- * @param mps: Max Packet Size.
- * This parameter can be a value from 0 to32K
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(hhcd);
-
- hhcd->hc[ch_num].dev_addr = dev_address;
- hhcd->hc[ch_num].max_packet = mps;
- hhcd->hc[ch_num].ch_num = ch_num;
- hhcd->hc[ch_num].ep_type = ep_type;
- hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
- hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
- hhcd->hc[ch_num].speed = speed;
-
- status = USB_HC_Init(hhcd->Instance,
- ch_num,
- epnum,
- dev_address,
- speed,
- ep_type,
- mps);
- __HAL_UNLOCK(hhcd);
-
- return status;
-}
-
-/**
- * @brief Halt a host channel
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num)
-{
- __HAL_LOCK(hhcd);
- USB_HC_Halt(hhcd->Instance, ch_num);
- __HAL_UNLOCK(hhcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the host driver
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
-{
- /* Check the HCD handle allocation */
- if(hhcd == NULL)
- {
- return HAL_ERROR;
- }
-
- hhcd->State = HAL_HCD_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_HCD_MspDeInit(hhcd);
-
- __HAL_HCD_DISABLE(hhcd);
-
- hhcd->State = HAL_HCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the HCD MSP.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes HCD MSP.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
- * @brief HCD IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the USB Host Data
- Transfer
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Submit a new URB for processing
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
- * This parameter can be a value from 1 to 15
- * @param direction: Channel number.
- * This parameter can be one of these values:
- * 0 : Output / 1 : Input
- * @param ep_type: Endpoint Type.
- * This parameter can be one of these values:
- * EP_TYPE_CTRL: Control type/
- * EP_TYPE_ISOC: Isochronous type/
- * EP_TYPE_BULK: Bulk type/
- * EP_TYPE_INTR: Interrupt type/
- * @param token: Endpoint Type.
- * This parameter can be one of these values:
- * 0: HC_PID_SETUP / 1: HC_PID_DATA1
- * @param pbuff: pointer to URB data
- * @param length: Length of URB data
- * @param do_ping: activate do ping protocol (for high speed only).
- * This parameter can be one of these values:
- * 0 : do ping inactive / 1 : do ping active
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping)
-{
- hhcd->hc[ch_num].ep_is_in = direction;
- hhcd->hc[ch_num].ep_type = ep_type;
-
- if(token == 0U)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
-
- /* Manage Data Toggle */
- switch(ep_type)
- {
- case EP_TYPE_CTRL:
- if((token == 1U) && (direction == 0U)) /*send data */
- {
- if (length == 0U)
- { /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1U;
- }
-
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
- }
- }
- break;
-
- case EP_TYPE_BULK:
- if(direction == 0U)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0U)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- break;
-
- case EP_TYPE_INTR:
- if(direction == 0U)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0U)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0U)
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- {
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- break;
-
- case EP_TYPE_ISOC:
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
- }
-
- hhcd->hc[ch_num].xfer_buff = pbuff;
- hhcd->hc[ch_num].xfer_len = length;
- hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0U;
- hhcd->hc[ch_num].ch_num = ch_num;
- hhcd->hc[ch_num].state = HC_IDLE;
-
- return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]));
-}
-
-/**
- * @brief handle HCD interrupt request.
- * @param hhcd: HCD handle
- * @retval None
- */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-
- uint32_t index = 0U, interrupt = 0U;
-
- /* ensure that we are in device mode */
- if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
- {
- /* Avoid spurious interrupt */
- if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
- {
- return;
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
- {
- /* Incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
- {
- /* Incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
- {
- /* Incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
- }
-
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
- {
- /* Incorrect mode, acknowledge the interrupt */
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
- }
-
- /* Handle Host Disconnect Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
- {
-
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- /* Handle Host Port Interrupts */
- HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ);
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
- }
-
- /* Handle Host Port Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
- {
- HCD_Port_IRQHandler (hhcd);
- }
-
- /* Handle Host SOF Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
- {
- HAL_HCD_SOF_Callback(hhcd);
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
- }
-
- /* Handle Host channel Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
- {
- interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
- for (index = 0U; index < hhcd->Init.Host_channels ; index++)
- {
- if (interrupt & (1 << index))
- {
- if ((USBx_HC(index)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
- {
- HCD_HC_IN_IRQHandler (hhcd, index);
- }
- else
- {
- HCD_HC_OUT_IRQHandler (hhcd, index);
- }
- }
- }
- __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
- }
-
- /* Handle Rx Queue Level Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- HCD_RXQLVL_IRQHandler (hhcd);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
- }
-}
-
-/**
- * @brief SOF callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_SOF_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Connexion Event callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Connect_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disonnection Event callback.
- * @param hhcd: HCD handle
- * @retval None
- */
-__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_Disconnect_Callback could be implemented in the user file
- */
-}
-
-/**
- * @brief Notify URB state change callback.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @param urb_state:
- * This parameter can be one of these values:
- * URB_IDLE/
- * URB_DONE/
- * URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
- * URB_STALL/
- * @retval None
- */
-__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hhcd);
- UNUSED(chnum);
- UNUSED(urb_state);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the HCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start the host driver
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
- __HAL_HCD_ENABLE(hhcd);
- USB_DriveVbus(hhcd->Instance, 1U);
- __HAL_UNLOCK(hhcd);
- return HAL_OK;
-}
-
-/**
- * @brief Stop the host driver
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
- USB_StopHost(hhcd->Instance);
- __HAL_UNLOCK(hhcd);
- return HAL_OK;
-}
-
-/**
- * @brief Reset the host port
- * @param hhcd: HCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
-{
- return (USB_ResetPort(hhcd->Instance));
-}
-
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the HCD handle state
- * @param hhcd: HCD handle
- * @retval HAL state
- */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
-{
- return hhcd->State;
-}
-
-/**
- * @brief Return URB state for a channel
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval URB state.
- * This parameter can be one of these values:
- * URB_IDLE/
- * URB_DONE/
- * URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
- * URB_STALL/
- */
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].urb_state;
-}
-
-
-/**
- * @brief Return the last host transfer size
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval last transfer size in byte
- */
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].xfer_count;
-}
-
-/**
- * @brief Return the Host Channel state
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval Host channel state
- * This parameter can be one of the these values:
- * HC_IDLE/
- * HC_XFRC/
- * HC_HALTED/
- * HC_NYET/
- * HC_NAK/
- * HC_STALL/
- * HC_XACTERR/
- * HC_BBLERR/
- * HC_DATATGLERR/
- */
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- return hhcd->hc[chnum].state;
-}
-
-/**
- * @brief Return the current Host frame number
- * @param hhcd: HCD handle
- * @retval Current Host frame number
- */
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
-{
- return (USB_GetCurrentFrame(hhcd->Instance));
-}
-
-/**
- * @brief Return the Host enumeration speed
- * @param hhcd: HCD handle
- * @retval Enumeration speed
- */
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
-{
- return (USB_GetHostSpeed(hhcd->Instance));
-}
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @addtogroup HCD_Private_Functions
- * @{
- */
-/**
- * @brief This function handles Host Channel IN interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval none
- */
-static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0U;
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].state = HC_STALL;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- USB_HC_Halt(hhcd->Instance, chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- hhcd->hc[chnum].state = HC_DATATGLERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- }
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
- {
- hhcd->hc[chnum].state = HC_XFRC;
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
-
- if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-
- }
- else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
- {
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
- hhcd->hc[chnum].urb_state = URB_DONE;
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
- hhcd->hc[chnum].toggle_in ^= 1U;
-
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
- {
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
- if(hhcd->hc[chnum].state == HC_XFRC)
- {
- hhcd->hc[chnum].urb_state = URB_DONE;
- }
- else if (hhcd->hc[chnum].state == HC_STALL)
- {
- hhcd->hc[chnum].urb_state = URB_STALL;
- }
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
- {
- if(hhcd->hc[chnum].ErrCnt++ > 3U)
- {
- hhcd->hc[chnum].ErrCnt = 0U;
- hhcd->hc[chnum].urb_state = URB_ERROR;
- }
- else
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- }
- else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
- {
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- }
-}
-
-/**
- * @brief This function handles Host Channel OUT interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
- * This parameter can be a value from 1 to 15
- * @retval none
- */
-static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0U;
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
-
- if( hhcd->hc[chnum].do_ping == 1U)
- {
- hhcd->hc[chnum].state = HC_NYET;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
- {
- hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt= 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
-
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
- {
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
- hhcd->hc[chnum].state = HC_XFRC;
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
- {
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_STALL;
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_XACTERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- hhcd->hc[chnum].state = HC_DATATGLERR;
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
- {
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
- if(hhcd->hc[chnum].state == HC_XFRC)
- {
- hhcd->hc[chnum].urb_state = URB_DONE;
- if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
- {
- hhcd->hc[chnum].toggle_out ^= 1U;
- }
- }
- else if (hhcd->hc[chnum].state == HC_NAK)
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
- else if (hhcd->hc[chnum].state == HC_NYET)
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- hhcd->hc[chnum].do_ping = 0U;
- }
- else if (hhcd->hc[chnum].state == HC_STALL)
- {
- hhcd->hc[chnum].urb_state = URB_STALL;
- }
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
- {
- if(hhcd->hc[chnum].ErrCnt++ > 3U)
- {
- hhcd->hc[chnum].ErrCnt = 0U;
- hhcd->hc[chnum].urb_state = URB_ERROR;
- }
- else
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
- }
-
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
-}
-
-/**
- * @brief This function handles Rx Queue Level interrupt requests.
- * @param hhcd: HCD handle
- * @retval none
- */
-static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0U;
- uint32_t pktsts;
- uint32_t pktcnt;
- uint32_t temp = 0U;
- uint32_t tmpreg = 0U;
-
- temp = hhcd->Instance->GRXSTSP;
- channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
- pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U;
- pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
-
- switch (pktsts)
- {
- case GRXSTS_PKTSTS_IN:
- /* Read the data into the host buffer. */
- if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void *)0U))
- {
- USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-
- /*manage multiple Xfer */
- hhcd->hc[channelnum].xfer_buff += pktcnt;
- hhcd->hc[channelnum].xfer_count += pktcnt;
-
- if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
- {
- /* re-activate the channel when more packets are expected */
- tmpreg = USBx_HC(channelnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(channelnum)->HCCHAR = tmpreg;
- hhcd->hc[channelnum].toggle_in ^= 1U;
- }
- }
- break;
-
- case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
- break;
-
- case GRXSTS_PKTSTS_IN_XFER_COMP:
- case GRXSTS_PKTSTS_CH_HALTED:
- default:
- break;
- }
-}
-
-/**
- * @brief This function handles Host Port interrupt requests.
- * @param hhcd: HCD handle
- * @retval None
- */
-static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- __IO uint32_t hprt0 = 0, hprt0_dup = 0U;
-
- /* Handle Host Port Interrupts */
- hprt0 = USBx_HPRT0;
- hprt0_dup = USBx_HPRT0;
-
- hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- /* Check whether Port Connect Detected */
- if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
- {
- if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- HAL_HCD_Connect_Callback(hhcd);
- }
- hprt0_dup |= USB_OTG_HPRT_PCDET;
- }
-
- /* Check whether Port Enable Changed */
- if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
- {
- hprt0_dup |= USB_OTG_HPRT_PENCHNG;
-
- if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
- {
- if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
- {
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
- }
- else
- {
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
- }
- HAL_HCD_Connect_Callback(hhcd);
- }
- else
- {
- /* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- }
- }
-
- /* Check For an over current */
- if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
- {
- hprt0_dup |= USB_OTG_HPRT_POCCHNG;
- }
-
- /* Clear Port Interrupts */
- USBx_HPRT0 = hprt0_dup;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_i2c.c b/lib/hal-stm32f1/source/stm32f1xx_hal_i2c.c deleted file mode 100644 index 0f4305b6..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_i2c.c +++ /dev/null @@ -1,5575 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_i2c.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief I2C HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Inter Integrated Circuit (I2C) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State, Mode and Error functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The I2C HAL driver can be used as follows:
-
- (#) Declare a I2C_HandleTypeDef handle structure, for example:
- I2C_HandleTypeDef hi2c;
-
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
- (##) Enable the I2Cx interface clock
- (##) I2C pins configuration
- (+++) Enable the clock for the I2C GPIOs
- (+++) Configure I2C pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the I2Cx interrupt priority
- (+++) Enable the NVIC I2C IRQ Channel
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
- (+++) Enable the DMAx interface clock using
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
- (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx channel
-
- (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
- Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
-
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
-
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
- (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
- *** Polling mode IO MEM operation ***
- =====================================
- [..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
- *** Interrupt mode IO sequential operation ***
- ==============================================
- [..]
- (@) These interfaces allow to manage a sequential transfer with a repeated start condition
- when a direction change during transfer
- [..]
- (+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
- (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition
- (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and without a final stop condition in both cases
- (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
- if no direction change and with a final stop condition in both cases
-
- (+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
-
- *** Interrupt mode IO MEM operation ***
- =======================================
- [..]
- (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
- *** DMA mode IO MEM operation ***
- =================================
- [..]
- (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-
- *** I2C HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in I2C HAL driver.
-
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
- [..]
- (@) You can refer to the I2C HAL driver header file for more useful macros
-
- *** I2C Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
- (@) See ErrataSheet to know full silicon limitation list of your product.
-
- (#) Workarounds Implemented inside I2C HAL Driver
- (##) Wrong data read into data register (Polling and Interrupt mode)
- (##) Start cannot be generated after a misplaced Stop
- (##) Some software events must be managed before the current byte is being transferred:
- Workaround: Use DMA in general, except when the Master is receiving a single byte.
- For Interupt mode, I2C should have the highest priority in the application.
- (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
- Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
- supported by the slave.
- (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
- Workaround: If the slave device allows it, use the clock stretching mechanism
- by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup I2C I2C
- * @brief I2C HAL module driver
- * @{
- */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup I2C_Private_Define
- * @{
- */
-#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
-#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
-#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
-
-/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions
- * @{
- */
-/* Private functions to handle DMA transfer */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-
-static void I2C_ITError(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
-
-/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the I2Cx peripheral:
-
- (+) User must Implement HAL_I2C_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
-
- (+) Call the function HAL_I2C_Init() to configure the selected device with
- the selected configuration:
- (++) Communication Speed
- (++) Duty cycle
- (++) Addressing mode
- (++) Own Address 1
- (++) Dual Addressing mode
- (++) Own Address 2
- (++) General call mode
- (++) Nostretch mode
-
- (+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
- uint32_t freqrange = 0U;
- uint32_t pclk1 = 0U;
-
- /* Check the I2C handle allocation */
- if(hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
- assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
- assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
- assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
- assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
- assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
- assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
- assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
- assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
- if(hi2c->State == HAL_I2C_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2c->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_I2C_MspInit(hi2c);
- }
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Get PCLK1 frequency */
- pclk1 = HAL_RCC_GetPCLK1Freq();
-
- /* Calculate frequency range */
- freqrange = I2C_FREQRANGE(pclk1);
-
- /*---------------------------- I2Cx CR2 Configuration ----------------------*/
- /* Configure I2Cx: Frequency range */
- hi2c->Instance->CR2 = freqrange;
-
- /*---------------------------- I2Cx TRISE Configuration --------------------*/
- /* Configure I2Cx: Rise Time */
- hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
-
- /*---------------------------- I2Cx CCR Configuration ----------------------*/
- /* Configure I2Cx: Speed */
- hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
-
- /*---------------------------- I2Cx CR1 Configuration ----------------------*/
- /* Configure I2Cx: Generalcall and NoStretch mode */
- hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Configure I2Cx: Own Address1 and addressing mode */
- hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
-
- /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
- /* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
-
- /* Enable the selected I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the I2C peripheral.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Check the I2C handle allocation */
- if(hi2c == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
- hi2c->State = HAL_I2C_STATE_BUSY;
-
- /* Disable the I2C Peripheral Clock */
- __HAL_I2C_DISABLE(hi2c);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_I2C_MspDeInit(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
-}
-
-/**
- * @brief I2C MSP Init.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval None
- */
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief I2C MSP DeInit
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval None
- */
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2C data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2C_Master_Transmit()
- (++) HAL_I2C_Master_Receive()
- (++) HAL_I2C_Slave_Transmit()
- (++) HAL_I2C_Slave_Receive()
- (++) HAL_I2C_Mem_Write()
- (++) HAL_I2C_Mem_Read()
- (++) HAL_I2C_IsDeviceReady()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2C_Master_Transmit_IT()
- (++) HAL_I2C_Master_Receive_IT()
- (++) HAL_I2C_Slave_Transmit_IT()
- (++) HAL_I2C_Slave_Receive_IT()
- (++) HAL_I2C_Master_Sequential_Transmit_IT()
- (++) HAL_I2C_Master_Sequential_Receive_IT()
- (++) HAL_I2C_Slave_Sequential_Transmit_IT()
- (++) HAL_I2C_Slave_Sequential_Receive_IT()
- (++) HAL_I2C_Mem_Write_IT()
- (++) HAL_I2C_Mem_Read_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2C_Master_Transmit_DMA()
- (++) HAL_I2C_Master_Receive_DMA()
- (++) HAL_I2C_Slave_Transmit_DMA()
- (++) HAL_I2C_Slave_Receive_DMA()
- (++) HAL_I2C_Mem_Write_DMA()
- (++) HAL_I2C_Mem_Read_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
- (++) HAL_I2C_MasterTxCpltCallback()
- (++) HAL_I2C_MasterRxCpltCallback()
- (++) HAL_I2C_SlaveTxCpltCallback()
- (++) HAL_I2C_SlaveRxCpltCallback()
- (++) HAL_I2C_ErrorCallback()
- (++) HAL_I2C_AbortCpltCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- while(hi2c->XferSize > 0U)
- {
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
-
- /* Wait until BTF flag is set */
- if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- if(hi2c->XferSize == 0U)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- else if(hi2c->XferSize == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Re-enable IRQs */
- __enable_irq();
- }
- else if(hi2c->XferSize == 2U)
- {
- /* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Re-enable IRQs */
- __enable_irq();
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- while(hi2c->XferSize > 0U)
- {
- if(hi2c->XferSize <= 3U)
- {
- /* One byte */
- if(hi2c->XferSize == 1U)
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- /* Two bytes */
- else if(hi2c->XferSize == 2U)
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Re-enable IRQs */
- __enable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- /* 3 Last bytes */
- else
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Re-enable IRQs */
- __enable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
- else
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
- }
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* If 10bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- while(hi2c->XferSize > 0U)
- {
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
-
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- hi2c->XferSize--;
- }
- }
-
- /* Wait until AF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- while(hi2c->XferSize > 0U)
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
-
- /* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- __IO uint32_t Prev_State = 0x00U;
- __IO uint32_t count = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Check Busy Flag only if FIRST call of Master interface */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- Prev_State = hi2c->PreviousState;
-
- /* Generate Start */
- if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
- {
- /* Generate Start condition if first transfer */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- __IO uint32_t count = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Check Busy Flag only if FIRST call of Master interface */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
- {
- /* Generate Start condition if first transfer */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- hi2c->State = HAL_I2C_STATE_LISTEN;
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
- /* Disable Address listen mode only if a transfer is not ongoing */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Disable EVT and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort a master I2C process communication with Interrupt.
- * @note This abort can be called only if state is ready
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(DevAddress);
-
- /* Abort Master transfer during Receive or Transmit process */
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_ABORT;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->XferCount = 0U;
-
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c);
-
- return HAL_OK;
- }
- else
- {
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- while(hi2c->XferSize > 0U)
- {
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
-
- /* Wait until BTF flag is set */
- if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- if(hi2c->XferSize == 0U)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- else if(hi2c->XferSize == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Re-enable IRQs */
- __enable_irq();
- }
- else if(hi2c->XferSize == 2U)
- {
- /* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Re-enable IRQs */
- __enable_irq();
- }
- else
- {
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- while(hi2c->XferSize > 0U)
- {
- if(hi2c->XferSize <= 3U)
- {
- /* One byte */
- if(hi2c->XferSize== 1U)
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- /* Two bytes */
- else if(hi2c->XferSize == 2U)
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Re-enable IRQs */
- __enable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- /* 3 Last bytes */
- else
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
- __disable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Re-enable IRQs */
- __enable_irq();
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
- else
- {
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
- }
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
- hi2c->Memaddress = MemAddress;
- hi2c->MemaddSize = MemAddSize;
- hi2c->EventCount = 0U;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
- hi2c->Memaddress = MemAddress;
- hi2c->MemaddSize = MemAddSize;
- hi2c->EventCount = 0U;
-
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- if(hi2c->XferSize > 0U)
- {
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- __IO uint32_t count = 0U;
-
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be read
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
- uint32_t tickstart = 0x00U;
- __IO uint32_t count = 0U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- if(Size == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
-
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- }
- else
- {
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Checks if target device is ready for communication.
- * @note This function is used with Memory devices
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param Trials Number of trials
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
- uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- do
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
- /* Wait until ADDR or AF flag are set */
- /* Get tick */
- tickstart = HAL_GetTick();
-
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- tmp3 = hi2c->State;
- while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State = HAL_I2C_STATE_TIMEOUT;
- }
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- tmp3 = hi2c->State;
- }
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Check if the ADDR flag has been set */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Clear ADDR Flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_OK;
- }
- else
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Clear AF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- }while(I2C_Trials++ < Trials);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles I2C event interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
- uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
- uint32_t itsources = READ_REG(hi2c->Instance->CR2);
-
- uint32_t CurrentMode = hi2c->Mode;
-
- /* Master or Memory mode selected */
- if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
- {
- /* SB Set ----------------------------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_Master_SB(hi2c);
- }
- /* ADD10 Set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_Master_ADD10(hi2c);
- }
- /* ADDR Set --------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_Master_ADDR(hi2c);
- }
-
- /* I2C in mode Transmitter -----------------------------------------------*/
- if((sr2itflags & I2C_FLAG_TRA) != RESET)
- {
- /* TXE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_MasterTransmit_TXE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_MasterTransmit_BTF(hi2c);
- }
- }
- /* I2C in mode Receiver --------------------------------------------------*/
- else
- {
- /* RXNE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_MasterReceive_RXNE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_MasterReceive_BTF(hi2c);
- }
- }
- }
- /* Slave mode selected */
- else
- {
- /* ADDR set --------------------------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_Slave_ADDR(hi2c);
- }
- /* STOPF set --------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_Slave_STOPF(hi2c);
- }
- /* I2C in mode Transmitter -----------------------------------------------*/
- else if((sr2itflags & I2C_FLAG_TRA) != RESET)
- {
- /* TXE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_SlaveTransmit_TXE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_SlaveTransmit_BTF(hi2c);
- }
- }
- /* I2C in mode Receiver --------------------------------------------------*/
- else
- {
- /* RXNE set and BTF reset ----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_SlaveReceive_RXNE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
- {
- I2C_SlaveReceive_BTF(hi2c);
- }
- }
- }
-}
-
-/**
- * @brief This function handles I2C error interrupt request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
- uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
- uint32_t itsources = READ_REG(hi2c->Instance->CR2);
-
- /* I2C Bus error interrupt occurred ----------------------------------------*/
- if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-
- /* Workaround: Start cannot be generated after a misplaced Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
- }
-
- /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
- if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
- }
-
- /* I2C Acknowledge failure error interrupt occurred ------------------------*/
- if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
- {
- tmp1 = hi2c->Mode;
- tmp2 = hi2c->XferCount;
- tmp3 = hi2c->State;
- tmp4 = hi2c->PreviousState;
- if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
- ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
- ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
- {
- I2C_Slave_AF(hi2c);
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
- }
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
- }
-
- /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
- if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
- }
-
- /* Call the Error Callback in case of Error detected -----------------------*/
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- I2C_ITError(hi2c);
- }
-}
-
-/**
- * @brief Master Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Master Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
- */
-}
-
-/** @brief Slave Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Slave Address Match callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
- * @param AddrMatchCode Address Match Code
- * @retval None
- */
-__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
- UNUSED(TransferDirection);
- UNUSED(AddrMatchCode);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AddrCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Listen Complete callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ListenCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Tx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemTxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Memory Rx Transfer completed callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemRxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief I2C error callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief I2C abort callback.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
- */
-__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2c);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AbortCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State, Mode and Error functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2C handle state.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL state
- */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
- /* Return I2C handle state */
- return hi2c->State;
-}
-
-/**
- * @brief Return the I2C Master, Slave, Memory or no mode.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL mode
- */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->Mode;
-}
-
-/**
- * @brief Return the I2C error code
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval I2C Error Code
- */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
- return hi2c->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Handle TXE flag for Master
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentMode = hi2c->Mode;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
- {
- /* Call TxCpltCallback() directly if no stop mode is set */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
- {
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
-
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- else /* Generate Stop condition then Call TxCpltCallback() */
- {
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- }
- }
- else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
- ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
- {
- if(hi2c->XferCount == 0U)
- {
- /* Disable BUF interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
- }
- else
- {
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- if(hi2c->EventCount == 0)
- {
- /* If Memory address size is 8Bit */
- if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
- hi2c->EventCount += 2;
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
-
- hi2c->EventCount++;
- }
- }
- else if(hi2c->EventCount == 1)
- {
- /* Send LSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
- hi2c->EventCount++;
- }
- else if(hi2c->EventCount == 2)
- {
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- /* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
- }
- }
- else
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle BTF flag for Master transmitter
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- if(hi2c->XferCount != 0U)
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
- else
- {
- /* Call TxCpltCallback() directly if no stop mode is set */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
- {
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
-
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- else /* Generate Stop condition then Call TxCpltCallback() */
- {
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle RXNE flag for Master
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- uint32_t tmp = 0U;
-
- tmp = hi2c->XferCount;
- if(tmp > 3U)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
- else if((tmp == 2U) || (tmp == 3U))
- {
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
- }
-
- /* Disable BUF interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
- }
- else
- {
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
- }
-
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle BTF flag for Master receiver
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- if(hi2c->XferCount == 3U)
- {
- if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
- else if(hi2c->XferCount == 2U)
- {
- /* Prepare next transfer or stop current transfer */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
- {
- if(CurrentXferOptions != I2C_NEXT_FRAME)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
- }
-
- /* Disable EVT and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- }
- else
- {
- /* Disable EVT and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
- }
- else
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle SB flag for Master
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- if(hi2c->EventCount == 0U)
- {
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
- }
- else
- {
- hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
- }
- }
- else
- {
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- /* Send slave 7 Bits address */
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
- }
- else
- {
- hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
- }
- }
- else
- {
- if(hi2c->EventCount == 0U)
- {
- /* Send header of slave address */
- hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
- }
- else if(hi2c->EventCount == 1U)
- {
- /* Send header of slave address */
- hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle ADD10 flag for Master
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
-{
- /* Send slave address */
- hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle ADDR flag for Master
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentMode = hi2c->Mode;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
- uint32_t Prev_State = hi2c->PreviousState;
-
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
- else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- hi2c->EventCount++;
- }
- else
- {
- if(hi2c->XferCount == 0U)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- else if(hi2c->XferCount == 1U)
- {
- if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- }
- /* Prepare next transfer or stop current transfer */
- else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
- && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
- {
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
- else
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- }
- else if(hi2c->XferCount == 2U)
- {
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
- {
- /* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
- {
- /* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
- }
- }
- else
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
- {
- /* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- /* Reset Event counter */
- hi2c->EventCount = 0U;
- }
- }
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle TXE flag for Slave
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
-
- if(hi2c->XferCount != 0U)
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
-
- if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- /* Last Byte is received, disable Interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
- /* Set state at HAL_I2C_STATE_LISTEN */
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- hi2c->State = HAL_I2C_STATE_LISTEN;
-
- /* Call the Tx complete callback to inform upper layer of the end of receive process */
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle BTF flag for Slave transmitter
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->XferCount != 0U)
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle RXNE flag for Slave
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
-
- if(hi2c->XferCount != 0U)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
-
- if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- /* Last Byte is received, disable Interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-
- /* Set state at HAL_I2C_STATE_LISTEN */
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
- hi2c->State = HAL_I2C_STATE_LISTEN;
-
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle BTF flag for Slave receiver
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->XferCount != 0U)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle ADD flag for Slave
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
-{
- uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
- uint16_t SlaveAddrCode = 0U;
-
- /* Transfer Direction requested by Master */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
- {
- TransferDirection = I2C_DIRECTION_TRANSMIT;
- }
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
- {
- SlaveAddrCode = hi2c->Init.OwnAddress1;
- }
- else
- {
- SlaveAddrCode = hi2c->Init.OwnAddress2;
- }
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle STOPF flag for Slave
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
-
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Clear STOPF flag */
- __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* If a DMA is ongoing, Update handle size context */
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
- {
- if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
- }
- else
- {
- hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
- }
- }
-
- /* All data are not transferred, so set error code accordingly */
- if(hi2c->XferCount != 0U)
- {
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
-
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
-
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c);
- }
- else
- {
- if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
- (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
- }
- else
- {
- if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
- (CurrentState == HAL_I2C_STATE_LISTEN))
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
- }
- else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
- else
- {
- /* Clear AF flag only */
- /* State Listen, but XferOptions == FIRST or NEXT */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief I2C interrupts error process
- * @param hi2c I2C handle.
- * @retval None
- */
-static void I2C_ITError(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
-
- if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
- {
- /* keep HAL_I2C_STATE_LISTEN */
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_LISTEN;
- }
- else
- {
- /* If state is an abort treatment on going, don't change state */
- /* This change will be do later */
- if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
- {
- hi2c->State = HAL_I2C_STATE_READY;
- }
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- }
-
- /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- /* Abort DMA transfer */
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
- {
- hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
- if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
- {
- /* Set the DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
- {
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
- }
- }
- else
- {
- /* Set the DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
- {
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- }
-
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
- }
- }
- }
- else if(hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- }
-
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- /* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- }
-
- /* Call user error callback */
- HAL_I2C_ErrorCallback(hi2c);
- }
- /* STOP Flag is not set after a NACK reception */
- /* So may inform upper layer that listen phase is stopped */
- /* during NACK error treatment */
- if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
- {
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- HAL_I2C_ListenCpltCallback(hi2c);
- }
-}
-
-/**
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- /* Generate Start condition if first transfer */
- if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
- {
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
- }
- else
- {
- /* Send header of slave address */
- hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
- /* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
- }
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address for read request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentXferOptions = hi2c->XferOptions;
-
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start condition if first transfer */
- if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
- {
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
- }
- else
- {
- /* Send header of slave address */
- hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
- /* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send header of slave address */
- hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
- }
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Send LSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
- }
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
-
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief DMA I2C process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentMode = hi2c->Mode;
-
- if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
- {
- /* Disable DMA Request */
- hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
- hi2c->XferCount = 0U;
-
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- }
- else
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Disable Last DMA */
- hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
-
- /* Disable DMA Request */
- hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
- hi2c->XferCount = 0U;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
- else
- {
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
- }
- }
-}
-
-/**
- * @brief DMA I2C communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- hi2c->XferCount = 0U;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- HAL_I2C_ErrorCallback(hi2c);
-}
-
-/**
- * @brief DMA I2C communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- hi2c->XferCount = 0U;
-
- /* Reset XferAbortCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if(hi2c->State == HAL_I2C_STATE_ABORT)
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_AbortCpltCallback(hi2c);
- }
- else
- {
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- HAL_I2C_ErrorCallback(hi2c);
- }
-}
-
-/**
- * @brief This function handles I2C Communication Timeout.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param Flag specifies the I2C flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Wait until flag is set */
- while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for Master addressing phase.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param Flag specifies the I2C flag to check.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
- {
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
- /* Clear AF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- {
- /* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Timeout Timeout duration
- * @param Tickstart Tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- {
- /* Check if a STOPF is detected */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- /* Check for the Timeout */
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief This function handles Acknowledge failed detection during an I2C Communication.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
-{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-/**
- * @}
- */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_i2s.c b/lib/hal-stm32f1/source/stm32f1xx_hal_i2s.c deleted file mode 100644 index 48ff26f7..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_i2s.c +++ /dev/null @@ -1,1460 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_i2s.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Integrated Interchip Sound (I2S) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The I2S HAL driver can be used as follow:
-
- (#) Declare a I2S_HandleTypeDef handle structure.
- (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
- (##) I2S pins configuration:
- (+++) Enable the clock for the I2S GPIOs.
- (+++) Configure these I2S pins as alternate function.
- (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
- and HAL_I2S_Receive_IT() APIs).
- (+++) Configure the I2Sx interrupt priority.
- (+++) Enable the NVIC I2S IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
- and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx Channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Channel.
- (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Channel.
-
- (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
- using HAL_I2S_Init() function.
-
- -@- The specific I2S interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
- -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
- For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
- in order to achieve the maximum accuracy.
- -@- Make sure that either:
- (+@) External clock source is configured after setting correctly
- the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
- *** I2S HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in I2S HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
- (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
- (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
- [..]
- (@) You can refer to the I2S HAL driver header file for more useful macros
-
-
- *** I2C Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- (@) Only the 16-bit mode with no data extension can be used when the I2S
- is in Master and used the PCM long synchronization mode.
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @defgroup I2S I2S
- * @brief I2S HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
- uint32_t Timeout);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the I2Sx peripheral in simplex mode:
-
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_I2S_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Standard
- (++) Data Format
- (++) MCLK Output
- (++) Audio frequency
- (++) Polarity
-
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx peripheral.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the I2S according to the specified parameters
- * in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
- uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
- uint32_t tmp = 0U, i2sclk = 0U;
-
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
- assert_param(IS_I2S_MODE(hi2s->Init.Mode));
- assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
- assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
- assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Initialize Default I2S IrqHandler ISR */
- hi2s->IrqHandlerISR = I2S_IRQHandler;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
-
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
- hi2s->Instance->I2SPR = 0x0002U;
-
- /* Get the I2SCFGR register value */
- tmpreg = hi2s->Instance->I2SCFGR;
-
- /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
- /* If the requested audio frequency is not the default, compute the prescaler */
- if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing) *******************/
- /* Set I2S Packet Length value*/
- if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 32U;
- }
- else
- {
- /* Packet length is 16 bits */
- packetlength = 16U;
- }
-
- /* I2S standard */
- if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
- {
- /* In I2S standard packet lenght is multiplied by 2 */
- packetlength = packetlength * 2U;
- }
-
- if(hi2s->Instance == SPI2)
- {
- /* Get the source clock value: based on SPI2 Instance */
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
- }
- else if(hi2s->Instance == SPI3)
- {
- /* Get the source clock value: based on SPI3 Instance */
- i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
- }
- else
- {
- /* Get the source clock value: based on System Clock value */
- i2sclk = HAL_RCC_GetSysClockFreq();
- }
-
- /* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
- }
- else
- {
- tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
- }
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
- }
-
- /* Remove the flatting point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)1U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint32_t) (i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_ERROR;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
- /* Configure the I2S with the I2S_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
- (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
- /* Write to SPIx I2SCFGR */
- WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the I2S peripheral
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Check the I2S handle allocation */
- if(hi2s == NULL)
- {
- return HAL_ERROR;
- }
-
- hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_I2S_MspDeInit(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief I2S MSP Init
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S MSP DeInit
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_MspDeInit could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the I2S data
- transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
- or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
-
- (#) Blocking mode functions are :
- (++) HAL_I2S_Transmit()
- (++) HAL_I2S_Receive()
-
- (#) No-Blocking mode functions with Interrupt are :
- (++) HAL_I2S_Transmit_IT()
- (++) HAL_I2S_Receive_IT()
-
- (#) No-Blocking mode functions with DMA are :
- (++) HAL_I2S_Transmit_DMA()
- (++) HAL_I2S_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2S_TxCpltCallback()
- (++) HAL_I2S_RxCpltCallback()
- (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tmp1 = 0U;
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- while(hi2s->TxXferCount > 0U)
- {
- hi2s->Instance->DR = (*pData++);
- hi2s->TxXferCount--;
-
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Clear underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
- }
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming)
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continuous way and as the I2S is not disabled at the end of the I2S transaction
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tmp1 = 0U;
-
- if((pData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Receive data */
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
-
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
-
- (*pData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmp1 = 0U;
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pTxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
- * between Master and Slave otherwise the I2S interrupt should be optimized.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t tmp1 = 0U;
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pRxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
-
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Transmit data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t *tmp = NULL;
- uint32_t tmp1 = 0U;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
-
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Tx request is already enabled */
- if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
- {
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
- uint32_t *tmp = NULL;
- uint32_t tmp1 = 0U;
-
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pRxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Rx request is already enabled */
- if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
- {
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the audio channel playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Disable the I2S DMA Tx request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA Rx request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio channel playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Enable the I2S DMA Tx request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Enable the I2S DMA Rx request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- }
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the audio channel playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* Disable the I2S DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
-
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmatx);
- }
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
-
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmarx);
- }
- /* Disable I2S peripheral */
- __HAL_I2S_DISABLE(hi2s);
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- /* Call the IrqHandler ISR set during HAL_I2S_INIT */
- hi2s->IrqHandlerISR(hi2s);
-}
-
-/**
- * @brief Tx Transfer Half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief I2S error callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the I2S state
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL state
- */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->State;
-}
-
-/**
- * @brief Return the I2S error code
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval I2S Error Code
- */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
- return hi2s->ErrorCode;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-/**
- * @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
- {
- /* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
-
- hi2s->TxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- HAL_I2S_TxCpltCallback(hi2s);
-}
-/**
- * @brief DMA I2S transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
- {
- /* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
- }
- HAL_I2S_RxCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2S_RxHalfCpltCallback(hi2s);
-}
-
-/**
- * @brief DMA I2S communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0U;
- hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
- HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_TxCpltCallback(hi2s);
- }
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval HAL status
- */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
- /* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_RxCpltCallback(hi2s);
- }
-}
-
-/**
- * @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @retval None
- */
-static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- __IO uint32_t i2ssr = hi2s->Instance->SR;
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* I2S in mode Receiver ------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- I2S_Receive_IT(hi2s);
- }
-
- /* I2S Overrun error interrupt occured -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
- {
- /* I2S in mode Transmitter -----------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
- }
-
- /* I2S Underrun error interrupt occurred --------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- HAL_I2S_ErrorCallback(hi2s);
- }
- }
-}
-
-/**
- * @brief This function handles I2S Communication Timeout.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
- * the configuration information for I2S module
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
- uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set to status*/
- while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#endif /* HAL_I2S_MODULE_ENABLED */
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_irda.c b/lib/hal-stm32f1/source/stm32f1xx_hal_irda.c deleted file mode 100644 index a55069cf..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_irda.c +++ /dev/null @@ -1,2133 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_irda.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief IRDA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the IrDA SIR ENDEC block (IrDA):
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The IRDA HAL driver can be used as follows:
-
- (#) Declare a IRDA_HandleTypeDef handle structure.
- (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) IRDA pins configuration:
- (+++) Enable the clock for the IRDA GPIOs.
- (+++) Configure the IRDA pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
- and HAL_IRDA_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
-
- (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
- and Mode(Receiver/Transmitter) in the hirda Init structure.
-
- (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_IRDA_MspInit() API.
- [..]
- (@) The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
- [..]
- Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
- (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
- (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
- (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
- (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
- (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
-
- *** IRDA HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IRDA HAL driver.
-
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
- (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
- (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
- (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
- (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
- (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
-
- [..]
- (@) You can refer to the IRDA HAL driver header file for more useful macros
- @endverbatim
- [..]
- (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible IRDA frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | 1 STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | 1 STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | 1 STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | 1 STB | |
- +-------------------------------------------------------------+
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup IRDA IRDA
- * @brief HAL IRDA module driver
- * @{
- */
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions
- * @{
- */
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
- * @{
- */
-
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in IrDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) BaudRate
- (++) WordLength
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible IRDA frame formats.
- (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- (++) Mode: Receiver/transmitter modes
- (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
- [..]
- The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
- are available in reference manual).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- if(hirda->gState == HAL_IRDA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hirda->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_IRDA_MspInit(hirda);
- }
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* Disable the IRDA peripheral */
- __HAL_IRDA_DISABLE(hirda);
-
- /* Set the IRDA communication parameters */
- IRDA_SetConfig(hirda);
-
- /* In IrDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
- CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-
- /* Enable the IRDA peripheral */
- __HAL_IRDA_ENABLE(hirda);
-
- /* Set the prescaler */
- MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-
- /* Configure the IrDA mode */
- MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
-
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
-
- /* Initialize the IRDA state*/
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the IRDA peripheral
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- hirda->gState = HAL_IRDA_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_IRDA_DISABLE(hirda);
-
- /* DeInit the low level hardware */
- HAL_IRDA_MspDeInit(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_RESET;
- hirda->RxState = HAL_IRDA_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief IRDA MSP Init.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit can be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA MSP DeInit.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the IRDA data transfers.
- IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
- is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
- While receiving data, transmission should be avoided as the data to be transmitted
- could be corrupted.
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, these APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_IRDA_ErrorCallback() user callback will be executed when a communication
- error is detected
-
- (#) Blocking mode APIs are:
- (++) HAL_IRDA_Transmit()
- (++) HAL_IRDA_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are:
- (++) HAL_IRDA_Transmit_IT()
- (++) HAL_IRDA_Receive_IT()
- (++) HAL_IRDA_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are:
- (++) HAL_IRDA_Transmit_DMA()
- (++) HAL_IRDA_Receive_DMA()
- (++) HAL_IRDA_DMAPause()
- (++) HAL_IRDA_DMAResume()
- (++) HAL_IRDA_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_IRDA_TxHalfCpltCallback()
- (++) HAL_IRDA_TxCpltCallback()
- (++) HAL_IRDA_RxHalfCpltCallback()
- (++) HAL_IRDA_RxCpltCallback()
- (++) HAL_IRDA_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0U)
- {
- hirda->TxXferCount--;
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- pData +=2U;
- }
- else
- {
- pData +=1U;
- }
- }
- else
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
- }
- }
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(hirda->RxXferCount > 0U)
- {
- hirda->RxXferCount--;
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*)pData;
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
- pData +=2U;
- }
- else
- {
- *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
- pData +=1U;
- }
- }
- else
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
- }
- }
- }
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Transmit data register empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Enable the IRDA Data Register not empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the IRDA transmit DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
-
- /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
- __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
- uint32_t dmarequest = 0x00U;
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
- {
- /* Disable the IRDA DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
-
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- /* Enable the IRDA DMA Tx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
-
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer */
- __HAL_IRDA_CLEAR_OREFLAG(hirda);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the IRDA DMA Rx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
- uint32_t dmarequest = 0x00U;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
- */
-
- /* Stop IRDA DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmatx);
- }
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmarx);
- }
- IRDA_EndRxTransfer(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel: use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel: use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Restore hirda->RxState and hirda->gState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- hirda->gState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0x00U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hirda->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0x00U;
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
-{
- uint32_t AbortCplt = 0x01U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
- }
- else
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
- }
- else
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at IRDA level */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
- {
- /* IRDA Tx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- hirda->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
- {
- /* IRDA Rx DMA Abort callback has already been initialised :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- hirda->hdmarx->XferAbortCallback = NULL;
- AbortCplt = 0x01U;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
- {
- /* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
- {
- /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
- hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0x00U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hirda->TxXferCount = 0x00U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hirda IRDA handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0x00U;
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hirda->RxXferCount = 0x00U;
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles IRDA interrupt request.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
- uint32_t isrflags = READ_REG(hirda->Instance->SR);
- uint32_t cr1its = READ_REG(hirda->Instance->CR1);
- uint32_t cr3its = READ_REG(hirda->Instance->CR3);
- uint32_t errorflags = 0x00U;
- uint32_t dmarequest = 0x00U;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
- {
- /* IRDA in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- return;
- }
- }
-
- /* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* IRDA parity error interrupt occurred -------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
- }
-
- /* IRDA noise error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- }
-
- /* IRDA frame error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- }
-
- /* IRDA Over-Run interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- }
- /* Call IRDA Error Call back function if need be -----------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
- {
- /* IRDA in mode Receiver ---------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
- {
- /* Blocking error : transfer is aborted
- Set the IRDA state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- IRDA_EndRxTransfer(hirda);
-
- /* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
-
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- }
- }
- return;
- } /* End if some error occurs */
-
- /* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- IRDA_Transmit_IT(hirda);
- return;
- }
-
- /* IRDA in mode Transmitter end --------------------------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- IRDA_EndTransmit_IT(hirda);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callbacks.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer complete callbacks.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer complete callbacks.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA error callbacks.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda IRDA handle.
- * @retval None
- */
-__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort Transmit Complete callback.
- * @param hirda IRDA handle.
- * @retval None
- */
-__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief IRDA Abort ReceiveComplete callback.
- * @param hirda IRDA handle.
- * @retval None
- */
-__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief IRDA State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of IrDA
- communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
- (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the IRDA state.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL state
- */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
-
- return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the IRDA error code
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval IRDA Error Code
- */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
- return hirda->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief DMA IRDA transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- hirda->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
- }
- /* DMA Circular mode */
- else
- {
- HAL_IRDA_TxCpltCallback(hirda);
- }
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_IRDA_TxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- hirda->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
- HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- HAL_IRDA_RxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
- uint32_t dmarequest = 0x00U;
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Stop IRDA DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
- {
- hirda->TxXferCount = 0U;
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
- {
- hirda->RxXferCount = 0U;
- IRDA_EndRxTransfer(hirda);
- }
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
-
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief This function handles IRDA Communication Timeout.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param Flag: specifies the IRDA flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Tickstart: Tick start value
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda: IRDA handle.
- * @retval None
- */
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-}
-
-/**
- * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
- * @param hirda: IRDA handle.
- * @retval None
- */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-/**
- * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0x00U;
- hirda->TxXferCount = 0x00U;
-
- HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
- {
- if(hirda->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
- {
- if(hirda->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->TxXferCount = 0x00U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->RxXferCount = 0x00U;
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
-}
-
-/**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- hirda->pTxBuffPtr += 2U;
- }
- else
- {
- hirda->pTxBuffPtr += 1U;
- }
- }
- else
- {
- hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
- }
-
- if(--hirda->TxXferCount == 0U)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable the IRDA Transmit Complete Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- /* Tx process is ended, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hirda->pRxBuffPtr;
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
- hirda->pRxBuffPtr += 2U;
- }
- else
- {
- *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
- hirda->pRxBuffPtr += 1U;
- }
- }
- else
- {
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
- }
- else
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
- }
- }
-
- if(--hirda->RxXferCount == 0U)
- {
- /* Disable the IRDA Data Register not empty Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Rx process is completed, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configures the IRDA peripheral.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
- /* Check the parameters */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
- assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
- assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
- assert_param(IS_IRDA_MODE(hirda->Init.Mode));
- assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
-
- /*-------------------------- USART CR2 Configuration ------------------------*/
- /* Clear STOP[13:12] bits */
- CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
-
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
- /* Write to USART CR1 */
- SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Clear CTSE and RTSE bits */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- if(hirda->Instance == USART1)
- {
- SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
- }
- else
- {
- SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_iwdg.c b/lib/hal-stm32f1/source/stm32f1xx_hal_iwdg.c deleted file mode 100644 index 59f39a19..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_iwdg.c +++ /dev/null @@ -1,258 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_iwdg.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief IWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and Start functions
- * + IO operation functions
- *
- @verbatim
- ==============================================================================
- ##### IWDG Generic features #####
- ==============================================================================
- [..]
- (+) The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
-
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
- disabled. The counter starts counting down from the reset value (0xFFF).
- When it reaches the end of count value (0x000) a reset signal is
- generated (IWDG reset).
-
- (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
-
- (+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
- reset occurs.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the IWDG counter either continues to work normally or stops, depending
- on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
-
- [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM5 CH4 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
- value will be loaded in the IWDG counter each time the watchdog is
- reloaded, then the IWDG will start counting down from this value.
- (++) wait for status flags to be reset"
-
- (#) Then the application program must refresh the IWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- HAL_IWDG_Refresh() function.
-
- *** IWDG HAL driver macros list ***
- ====================================
- [..]
- Below the list of most used macros in IWDG HAL driver:
- (+) __HAL_IWDG_START: Enable the IWDG peripheral
- (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
- the reload register
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-/** @defgroup IWDG IWDG
- * @brief IWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
- * @{
- */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to HSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48U
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Start functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters in the
- IWDG_InitTypeDef of associated handle.
- (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
- is reloaded in order to exit function with correct time base.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the IWDG according to the specified parameters in the
- * IWDG_InitTypeDef and start watchdog. Before exiting function,
- * watchdog is refreshed in order to have correct time base.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
- uint32_t tickstart;
-
- /* Check the IWDG handle allocation */
- if(hiwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
- assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
- assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-
- /* Enable IWDG. LSI is turned on automaticaly */
- __HAL_IWDG_START(hiwdg);
-
- /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
- IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
- /* Write to IWDG registers the Prescaler & Reload values to work with */
- hiwdg->Instance->PR = hiwdg->Init.Prescaler;
- hiwdg->Instance->RLR = hiwdg->Init.Reload;
-
- /* Check pending flag, if previous update not done, return timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Refresh the IWDG.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Refresh the IWDG.
- * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
- /* Reload IWDG counter with value defined in the reload register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_mmc.c b/lib/hal-stm32f1/source/stm32f1xx_hal_mmc.c deleted file mode 100644 index 82168a83..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_mmc.c +++ /dev/null @@ -1,2598 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_mmc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief MMC card HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (MMC) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + MMC card Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_MMC_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
- examples.
- You can easily tailor this configuration according to hardware resources.
-
- [..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with MMC and eMMC cards devices.
- It is used as follows:
-
- (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
- (##) SDMMC pins configuration for MMC card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
- and according to your pin assignment;
- (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
- and HAL_MMC_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
- (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
- (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDMMC and DMA interrupt priorities using functions
- HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
- (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
- and __HAL_MMC_DISABLE_IT() inside the communication process.
- (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
- and __HAL_MMC_CLEAR_IT()
- (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
- and HAL_MMC_WriteBlocks_IT() APIs).
- (+++) Configure the SDMMC interrupt priorities using function
- HAL_NVIC_SetPriority();
- (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
- and __HAL_MMC_DISABLE_IT() inside the communication process.
- (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
- and __HAL_MMC_CLEAR_IT()
- (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
-
-
- *** MMC Card Initialization and configuration ***
- ================================================
- [..]
- To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
- SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
- This function provide the following operations:
-
- (#) Initialize the SDMMC peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
- The MMC Card frequency (SDMMC_CK) is computed as follows:
-
- SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
- In initialization mode and according to the MMC Card standard,
- make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
-
- This phase of initialization is done through SDMMC_Init() and
- SDMMC_PowerState_ON() SDMMC low level APIs.
-
- (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
- This phase allows the card initialization and identification
- and check the MMC Card type (Standard Capacity or High Capacity)
- The initialization flow is compatible with MMC standard.
-
- This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
- of plug-off plug-in.
-
- (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
- frequency is set to 24MHz. You can change or adapt this frequency by adjusting
- the "ClockDiv" field.
- In transfer mode and according to the MMC Card standard, make sure that the
- SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDMMC
- peripheral in bypass mode. Refer to the corresponding reference manual
- for more details.
-
- (#) Select the corresponding MMC Card according to the address read with the step 2.
-
- (#) Configure the MMC Card in wide bus mode: 4-bits data.
-
- *** MMC Card Read operation ***
- ==============================
- [..]
- (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
-
- (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the DMA transfer process through the MMC Rx interrupt event.
-
- (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the IT transfer process through the MMC Rx interrupt event.
-
- *** MMC Card Write operation ***
- ===============================
- [..]
- (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
-
- (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the DMA transfer process through the MMC Tx interrupt event.
-
- (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the IT transfer process through the MMC Tx interrupt event.
-
- *** MMC card status ***
- ======================
- [..]
- (+) The MMC Status contains status bits that are related to the MMC Memory
- Card proprietary features. To get MMC card status use the HAL_MMC_GetCardStatus().
-
- *** MMC card information ***
- ===========================
- [..]
- (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
- It returns useful information about the MMC card such as block size, card type,
- block number ...
-
- *** MMC card CSD register ***
- ============================
- [..]
- (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
- Some of the CSD parameters are useful for card initialization and identification.
-
- *** MMC card CID register ***
- ============================
- [..]
- (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
- Some of the CID parameters are useful for card initialization and identification.
-
- *** MMC HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in MMC HAL driver.
-
- (+) __HAL_MMC_ENABLE : Enable the MMC device
- (+) __HAL_MMC_DISABLE : Disable the MMC device
- (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
- (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer
- (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
- (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
- (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
- (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
-
- [..]
- (@) You can refer to the MMC HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MMC
- * @{
- */
-
-#ifdef HAL_MMC_MODULE_ENABLED
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup MMC_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
-static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
-static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
-static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAError(DMA_HandleTypeDef *hdma);
-static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
-static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup MMC_Exported_Functions
- * @{
- */
-
-/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize the MMC
- card device to be ready for use.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the MMC according to the specified parameters in the
- MMC_HandleTypeDef and create the associated handle.
- * @param hmmc: Pointer to the MMC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
-{
- /* Check the MMC handle allocation */
- if(hmmc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
- assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
- assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv));
-
- if(hmmc->State == HAL_MMC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hmmc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_MMC_MspInit(hmmc);
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize the Card parameters */
- HAL_MMC_InitCard(hmmc);
-
- /* Initialize the error code */
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the MMC operation */
- hmmc->Context = MMC_CONTEXT_NONE;
-
- /* Initialize the MMC state */
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the MMC Card.
- * @param hmmc: Pointer to MMC handle
- * @note This function initializes the MMC card. It could be used when a card
- re-initialization is needed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
-{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- MMC_InitTypeDef Init;
-
- /* Default SDMMC peripheral configuration for MMC card initialization */
- Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDIO_BUS_WIDE_1B;
- Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDIO_INIT_CLK_DIV;
-
- /* Initialize SDMMC peripheral interface with default configuration */
- SDIO_Init(hmmc->Instance, Init);
-
- /* Disable SDMMC Clock */
- __HAL_MMC_DISABLE(hmmc);
-
- /* Set Power State to ON */
- SDIO_PowerState_ON(hmmc->Instance);
-
- /* Enable SDMMC Clock */
- __HAL_MMC_ENABLE(hmmc);
-
- /* Required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(2U);
-
- /* Identify card operating voltage */
- errorstate = MMC_PowerON(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- /* Card initialization */
- errorstate = MMC_InitCard(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the MMC card.
- * @param hmmc: Pointer to MMC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
-{
- /* Check the MMC handle allocation */
- if(hmmc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Set SD power state to off */
- MMC_PowerOFF(hmmc);
-
- /* De-Initialize the MSP layer */
- HAL_MMC_MspDeInit(hmmc);
-
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_RESET;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the MMC MSP.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MMC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize MMC MSP.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_MMC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the data
- transfer from/to MMC card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of MMC blocks to read
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Poll on SDMMC flags */
-#ifdef SDIO_STA_STBITERR
- while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
-#endif /* SDIO_STA_STBITERR */
- {
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
- {
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- *(tempbuff + count) = SDIO_ReadFIFO(hmmc->Instance);
- }
- tempbuff += 8U;
- }
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock read */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)))
- {
- *tempbuff = SDIO_ReadFIFO(hmmc->Instance);
- tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of MMC blocks to write
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
- uint32_t *tempbuff = (uint32_t *)pData;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- /* Write block(s) in polling mode */
-#ifdef SDIO_STA_STBITERR
- while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-#else /* SDIO_STA_STBITERR not defined */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
-#endif /* SDIO_STA_STBITERR */
- {
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE))
- {
- /* Write data to SDIO Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- SDIO_WriteFIFO(hmmc->Instance, (tempbuff + count));
- }
- tempbuff += 8U;
- }
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock write */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR))
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Rx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pRxBuffPtr = (uint32_t *)pData;
- hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- hmmc->pTxBuffPtr = (uint32_t *)pData;
- hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- /* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Rx
- * interrupt event.
- * @param hmmc: Pointer MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
-#ifdef SDIO_STA_STBITER
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
-#else /* SDIO_STA_STBITERR not defined */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
-#endif /* SDIO_STA_STBITERR */
-
- /* Set the DMA transfer complete callback */
- hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
-
- /* Set the DMA Abort callback */
- hmmc->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable MMC DMA transfer */
- __HAL_MMC_DMA_ENABLE(hmmc);
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(NULL == pData)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Initialize data control register */
- hmmc->Instance->DCTRL = 0U;
-
- /* Enable MMC Error interrupts */
-#ifdef SDIO_STA_STBITER
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
-#else /* SDIO_STA_STBITERR not defined */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
-#endif /* SDIO_STA_STBITERR */
-
- /* Set the DMA transfer complete callback */
- hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
-
- /* Set the DMA Abort callback */
- hmmc->hdmatx->XferAbortCallback = NULL;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
- }
- else
- {
- hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Enable SDIO DMA transfer */
- __HAL_MMC_DMA_ENABLE(hmmc);
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Erases the specified memory area of the given MMC card.
- * @note This API should be followed by a check on the card state through
- * HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
-{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(hmmc->State == HAL_MMC_STATE_READY)
- {
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
- {
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
- }
-
- /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles MMC card interrupt request.
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
-{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- /* Check for SDIO interrupt flags */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DATAEND) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
-
-#ifdef SDIO_STA_STBITERR
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
-#else /* SDIO_STA_STBITERR not defined */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR);
-#endif
-
- if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
- {
- if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
- {
- HAL_MMC_RxCpltCallback(hmmc);
- }
- else
- {
- HAL_MMC_TxCpltCallback(hmmc);
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
- {
- /* Disable the DMA transfer for transmit request by setting the DMAEN bit
- in the MMC DCTRL register */
- hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- HAL_MMC_TxCpltCallback(hmmc);
- }
- }
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXFIFOHE) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_TXFIFOHE);
-
- MMC_Write_IT(hmmc);
- }
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXFIFOHF) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_RXFIFOHF);
-
- MMC_Read_IT(hmmc);
- }
-
-#ifdef SDIO_STA_STBITERR
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_STBITERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- }
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
-
- /* Disable all interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
-
- if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- /* Abort the MMC DMA Streams */
- if(hmmc->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
- {
- MMC_DMATxAbort(hmmc->hdmatx);
- }
- }
- else if(hmmc->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
- {
- MMC_DMARxAbort(hmmc->hdmarx);
- }
- }
- else
- {
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_READY;
- HAL_MMC_AbortCallback(hmmc);
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
- {
- /* Set the MMC state to ready to be able to start again the process */
- hmmc->State = HAL_MMC_STATE_READY;
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
-#else /* SDIO_STA_STBITERR not defined */
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- }
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- /* Disable all interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- /* Abort the MMC DMA Streams */
- if(hmmc->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
- {
- MMC_DMATxAbort(hmmc->hdmatx);
- }
- }
- else if(hmmc->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
- {
- MMC_DMARxAbort(hmmc->hdmarx);
- }
- }
- else
- {
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_READY;
- HAL_MMC_AbortCallback(hmmc);
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
- {
- /* Set the MMC state to ready to be able to start again the process */
- hmmc->State = HAL_MMC_STATE_READY;
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
-#endif /* SDIO_STA_STBITERR */
-}
-
-/**
- * @brief return the MMC state
- * @param hmmc: Pointer to mmc handle
- * @retval HAL state
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
-{
- return hmmc->State;
-}
-
-/**
-* @brief Return the MMC error code
-* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
-* @retval MMC Error Code
-*/
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
-{
- return hmmc->ErrorCode;
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hmmc: Pointer to MMC handle
- * @retval None
- */
- __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief MMC error callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief MMC Abort callbacks
- * @param hmmc: Pointer MMC handle
- * @retval None
- */
-__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hmmc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the MMC card
- operations and get the related information
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CID register.
- * @param hmmc: Pointer to MMC handle
- * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
- * contains all CID register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
-{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0xFF000000U) >> 24U);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0x00FF0000U) >> 16U);
- pCID->OEM_AppliID = tmp << 8U;
-
- /* Byte 2 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0x000000FF00U) >> 8U);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hmmc->CID[0U] & 0x000000FFU);
- pCID->ProdName1 = tmp << 24U;
-
- /* Byte 4 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0xFF000000U) >> 24U);
- pCID->ProdName1 |= tmp << 16U;
-
- /* Byte 5 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0x00FF0000U) >> 16U);
- pCID->ProdName1 |= tmp << 8U;
-
- /* Byte 6 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0x0000FF00U) >> 8U);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CID[1U] & 0x000000FFU);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0xFF000000U) >> 24U);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0x00FF0000U) >> 16U);
- pCID->ProdSN = tmp << 24U;
-
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0x0000FF00U) >> 8U);
- pCID->ProdSN |= tmp << 16U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CID[2U] & 0x000000FFU);
- pCID->ProdSN |= tmp << 8U;
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0xFF000000U) >> 24U);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0x00FF0000U) >> 16U);
- pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
- pCID->ManufactDate = (tmp & 0x0FU) << 8U;
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0x0000FF00U) >> 8U);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CID[3U] & 0x000000FFU);
- pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
- pCID->Reserved2 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CSD register.
- * @param hmmc: Pointer to MMC handle
- * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that
- * contains all CSD register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
-{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (hmmc->CSD[0U] & 0xFF000000U) >> 24U;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
- pCSD->Reserved1 = tmp & 0x03U;
-
- /* Byte 1 */
- tmp = (hmmc->CSD[0U] & 0x00FF0000U) >> 16U;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hmmc->CSD[0U] & 0x0000FF00U) >> 8U;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hmmc->CSD[0U] & 0x000000FFU;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hmmc->CSD[1U] & 0xFF000000U) >> 24U;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
-
- /* Byte 5 */
- tmp = (hmmc->CSD[1U] & 0x00FF0000U) >> 16U;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
-
- /* Byte 6 */
- tmp = (hmmc->CSD[1U] & 0x0000FF00U) >> 8U;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
- pCSD->Reserved2 = 0; /*!< Reserved */
-
- pCSD->DeviceSize = (tmp & 0x03U) << 10U;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CSD[2U] & 0xFF000000U) >> 24U);
- pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CSD[2U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
- pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8U);
- pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
-
- hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hmmc->MmcCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
- hmmc->MmcCard.BlockSize = 1U << (pCSD->RdBlockLen);
-
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
- hmmc->MmcCard.LogBlockSize = 512U;
-
- pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
- pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CSD[2U] & 0x000000FFU);
- pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
- pCSD->WrProtectGrSize = (tmp & 0x7FU);
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0xFF000000U) >> 24U);
- pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
- pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
- pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
- pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
- pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
- pCSD->Reserved3 = 0U;
- pCSD->ContentProtectAppli = (tmp & 0x01U);
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0x0000FF00U) >> 8U);
- pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
- pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
- pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
- pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
- pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
- pCSD->ECC = (tmp & 0x03U);
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CSD[3U] & 0x000000FFU);
- pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
- pCSD->Reserved4 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the MMC card info.
- * @param hmmc: Pointer to MMC handle
- * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
- * will contain the MMC card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
-{
- pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
- pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
- pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
- pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
- pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
- pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
- pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables wide bus operation for the requested card if supported by
- * card.
- * @param hmmc: Pointer to MMC handle
- * @param WideMode: Specifies the MMC card wide bus mode
- * This parameter can be one of the following values:
- * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
- * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
- * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
-{
- __IO uint32_t count = 0U;
- SDIO_InitTypeDef Init;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0U, busy = 0U;
-
- /* Check the parameters */
- assert_param(IS_SDIO_BUS_WIDE(WideMode));
-
- /* Chnage Satte */
- hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Update Clock for Bus mode update */
- Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDIO_INIT_CLK_DIV;
- /* Initialize SDIO*/
- SDIO_Init(hmmc->Instance, Init);
-
- if(WideMode == SDIO_BUS_WIDE_8B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else if(WideMode == SDIO_BUS_WIDE_4B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else if(WideMode == SDIO_BUS_WIDE_1B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
- }
- else
- {
- /* WideMode is not a valid argument*/
- hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
- }
-
- /* Check for switch error and violation of the trial number of sending CMD 13 */
- while(busy == 0U)
- {
- if(count++ == SDMMC_MAX_TRIAL)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- busy = (((response >> 7U) == 1U) ? 0U : 1U);
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_DATATIMEOUT;
- while((response & 0x00000100U) == 0U)
- {
- if(count-- == 0U)
- {
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- return HAL_ERROR;
- }
-
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
- }
-
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Configure the SDIO peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockBypass = hmmc->Init.ClockBypass;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- SDIO_Init(hmmc->Instance, Init);
- }
-
- /* Change State */
- hmmc->State = HAL_MMC_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Gets the current mmc card data state.
- * @param hmmc: pointer to MMC handle
- * @retval Card state
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t resp1 = 0U;
-
- errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_OK)
- {
- hmmc->ErrorCode |= errorstate;
- }
-
- cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
-
- return cardstate;
-}
-
-/**
- * @brief Abort the current transfer and disable the MMC.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information for MMC module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
- {
- /* Disable the MMC DMA request */
- hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the MMC DMA Tx Stream */
- if(hmmc->hdmatx != NULL)
- {
- HAL_DMA_Abort(hmmc->hdmatx);
- }
- /* Abort the MMC DMA Rx Stream */
- if(hmmc->hdmarx != NULL)
- {
- HAL_DMA_Abort(hmmc->hdmarx);
- }
- }
-
- hmmc->State = HAL_MMC_STATE_READY;
- CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
- }
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information for MMC module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
- {
- /* Disable the MMC DMA request */
- hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the MMC DMA Tx Stream */
- if(hmmc->hdmatx != NULL)
- {
- hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
- if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
- {
- hmmc->hdmatx = NULL;
- }
- }
- /* Abort the MMC DMA Rx Stream */
- if(hmmc->hdmarx != NULL)
- {
- hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
- if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
- {
- hmmc->hdmarx = NULL;
- }
- }
- }
-
- /* No transfer ongoing on both DMA channels*/
- if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL))
- {
- CardState = HAL_MMC_GetCardState(hmmc);
- hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
- }
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
- {
- HAL_MMC_AbortCallback(hmmc);
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup MMC_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA MMC transmit process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
-
- /* Enable DATAEND Interrupt */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND));
-}
-
-/**
- * @brief DMA MMC receive process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- /* Send stop command in multiblock write */
- if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
-
- /* Disable the DMA transfer for transmit request by setting the DMAEN bit
- in the MMC DCTRL register */
- hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
-
- HAL_MMC_RxCpltCallback(hmmc);
-}
-
-/**
- * @brief DMA MMC communication error callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void MMC_DMAError(DMA_HandleTypeDef *hdma)
-{
- MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- HAL_MMC_CardStateTypeDef CardState;
-
- if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
- {
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- /* Disable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
- CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
- }
-
- hmmc->State= HAL_MMC_STATE_READY;
- }
-
- HAL_MMC_ErrorCallback(hmmc);
-}
-
-/**
- * @brief DMA MMC Tx Abort callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
-{
- MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- HAL_MMC_CardStateTypeDef CardState;
-
- if(hmmc->hdmatx != NULL)
- {
- hmmc->hdmatx = NULL;
- }
-
- /* All DMA channels are aborted */
- if(hmmc->hdmarx == NULL)
- {
- CardState = HAL_MMC_GetCardState(hmmc);
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
-
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- HAL_MMC_AbortCallback(hmmc);
- }
- else
- {
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
- }
-}
-
-/**
- * @brief DMA MMC Rx Abort callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
-{
- MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- HAL_MMC_CardStateTypeDef CardState;
-
- if(hmmc->hdmarx != NULL)
- {
- hmmc->hdmarx = NULL;
- }
-
- /* All DMA channels are aborted */
- if(hmmc->hdmatx == NULL)
- {
- CardState = HAL_MMC_GetCardState(hmmc);
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
- {
- hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
-
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
- {
- HAL_MMC_AbortCallback(hmmc);
- }
- else
- {
- HAL_MMC_ErrorCallback(hmmc);
- }
- }
- }
-}
-
-
-/**
- * @brief Initializes the mmc card.
- * @param hmmc: Pointer to MMC handle
- * @retval MMC Card error state
- */
-static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
-{
- HAL_MMC_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint16_t mmc_rca = 1;
-
- /* Check the power State */
- if(SDIO_GetPowerState(hmmc->Instance) == 0U)
- {
- /* Power off */
- return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- /* Send CMD2 ALL_SEND_CID */
- errorstate = SDMMC_CmdSendCID(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card identification number data */
- hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
- hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
- hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
- hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
- }
-
- /* Send CMD3 SET_REL_ADDR with argument 0 */
- /* MMC Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get the MMC card RCA */
- hmmc->MmcCard.RelCardAdd = mmc_rca;
-
- /* Send CMD9 SEND_CSD with argument as card's RCA */
- errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card Specific Data */
- hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
- hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
- hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
- hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
- }
-
- /* Get the Card Class */
- hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U);
-
- /* Get CSD parameters */
- HAL_MMC_GetCardCSD(hmmc, &CSD);
-
- /* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hmmc->Instance, hmmc->Init);
-
- /* All cards are initialized */
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Enquires cards about their operating voltage and configures clock
- * controls and stores MMC information that will be needed in future
- * in the MMC handle.
- * @param hmmc: Pointer to MMC handle
- * @retval error state
- */
-static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
-{
- __IO uint32_t count = 0U;
- uint32_t response = 0U, validvoltage = 0U;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- /* CMD0: GO_IDLE_STATE */
- errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
-
- while(validvoltage == 0U)
- {
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_MMC_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
- errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
- }
-
- /* When power routine is finished and command returns valid voltage */
- if ((response & eMMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE)
- {
- /* When voltage range of the card is within 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD;
- }
- else
- {
- /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD;
- }
-
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Turns the SDIO output signals off.
- * @param hmmc: Pointer to MMC handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
-{
- /* Set Power State to OFF */
- SDIO_PowerState_OFF(hmmc->Instance);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the current card's status.
- * @param hmmc: Pointer to MMC handle
- * @param pCardStatus: pointer to the buffer that will contain the MMC card
- * status (Card Status register)
- * @retval error state
- */
-static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
-{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
- if(pCardStatus == NULL)
- {
- return HAL_MMC_ERROR_PARAM;
- }
-
- /* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* Get MMC card status */
- *pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
- return HAL_MMC_ERROR_NONE;
-}
-
-/**
- * @brief Wrap up reading in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
- * @retval HAL status
- */
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
-{
- uint32_t count = 0U;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hmmc->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- *(tmp + count) = SDIO_ReadFIFO(hmmc->Instance);
- }
-
- hmmc->pRxBuffPtr += 8U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Wrap up writing in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
- * the configuration information.
- * @retval HAL status
- */
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
-{
- uint32_t count = 0U;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hmmc->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- SDIO_WriteFIFO(hmmc->Instance, (tmp + count));
- }
-
- hmmc->pTxBuffPtr += 8U;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_msp_template.c b/lib/hal-stm32f1/source/stm32f1xx_hal_msp_template.c deleted file mode 100644 index 351062e3..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_msp_template.c +++ /dev/null @@ -1,111 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_msp_template.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief HAL BSP module.
- * This file template is located in the HAL folder and should be copied
- * to the user folder.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL_MSP HAL_MSP
- * @brief HAL MSP module.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
- * @{
- */
-
-/**
- * @brief Initializes the Global MSP.
- * @retval None
- */
-void HAL_MspInit(void)
-{
-
-}
-
-/**
- * @brief DeInitializes the Global MSP.
- * @retval None
- */
-void HAL_MspDeInit(void)
-{
-
-}
-
-/**
- * @brief Initializes the PPP MSP.
- * @retval None
- */
-void HAL_PPP_MspInit(void)
-{
-
-}
-
-/**
- * @brief DeInitializes the PPP MSP.
- * @retval None
- */
-void HAL_PPP_MspDeInit(void)
-{
-
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_nand.c b/lib/hal-stm32f1/source/stm32f1xx_hal_nand.c deleted file mode 100644 index 85ad5085..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_nand.c +++ /dev/null @@ -1,1804 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_nand.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief NAND HAL module driver.
- * This file provides a generic firmware to drive NAND memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NAND flash memories. It uses the FSMC layer functions to interface
- with NAND devices. This driver is used as follows:
-
- (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
- with control and timing parameters for both common and attribute spaces.
-
- (+) Read NAND flash memory maker and device IDs using the function
- HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NAND flash memory by read/write operations using the functions
- HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
- HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
- HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
- HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
- to read/write page(s)/spare area(s). These functions use specific device
- information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
- structure. The read/write address information is contained by the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
-
- (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
- The erase block address information is contained in the Nand_Address_Typedef
- structure passed as parameter.
-
- (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
-
- (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
- HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
- feature or the function HAL_NAND_GetECC() to get the ECC correction code.
-
- (+) You can monitor the NAND device HAL state by calling the function
- HAL_NAND_GetState()
-
- [..]
- (@) This driver is a set of generic APIs which handle standard NAND flash operations.
- If a NAND flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-
-/** @defgroup NAND NAND
- * @brief NAND HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NAND memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ComSpace_Timing: pointer to Common space timing structure
- * @param AttSpace_Timing: pointer to Attribute space timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
-{
- /* Check the NAND handle state */
- if(hnand == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnand->State == HAL_NAND_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnand->Lock = HAL_UNLOCKED;
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspInit(hnand);
- }
-
- /* Initialize NAND control Interface */
- FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
-
- /* Initialize NAND common space timing Interface */
- FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
-
- /* Initialize NAND attribute space timing Interface */
- FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
-
- /* Enable the NAND device */
- __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
-{
- /* Initialize the low level hardware (MSP) */
- HAL_NAND_MspDeInit(hnand);
-
- /* Configure the NAND registers with their reset values */
- FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
-
- /* Reset the NAND controller state */
- hnand->State = HAL_NAND_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND MSP Init
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NAND MSP DeInit
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
-*/
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
-{
- /* Check NAND interrupt Rising edge flag */
- if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Rising edge pending bit */
- __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
- }
-
- /* Check NAND interrupt Level flag */
- if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Level pending bit */
- __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
- }
-
- /* Check NAND interrupt Falling edge flag */
- if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt Falling edge pending bit */
- __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
- }
-
- /* Check NAND interrupt FIFO empty flag */
- if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
- {
- /* NAND interrupt callback*/
- HAL_NAND_ITCallback(hnand);
-
- /* Clear NAND interrupt FIFO empty pending bit */
- __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
- }
-}
-
-/**
- * @brief NAND interrupt feature callback
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval None
- */
-__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnand);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NAND_ITCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NAND Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NAND
- memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read the NAND memory electronic signature
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pNAND_ID: NAND ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
-{
- __IO uint32_t data = 0U;
- __IO uint32_t data1 = 0U;
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
-
- /* Read the electronic signature from NAND flash */
- if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
- {
- data = *(__IO uint32_t *)deviceaddress;
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
- }
- else
- {
- data = *(__IO uint32_t *)deviceaddress;
- data1 = *((__IO uint32_t *)deviceaddress + 4U);
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
- pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory reset
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Configure the device: Enter the physical parameters of the device
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
-{
- hnand->Config.PageSize = pDeviceConfig->PageSize;
- hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
- hnand->Config.BlockSize = pDeviceConfig->BlockSize;
- hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
- hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
- hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
- hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Page(s) from NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer
- * @param NumPageToRead : number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- /* Check if an extra command is needed for reading pages */
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Page(s) from NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
- * @param NumPageToRead : number of pages to read from block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) read loop */
- while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
-
- /* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
- }
-
- /* Increment read pages number */
- numPagesRead++;
-
- /* Decrement pages to read */
- NumPageToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Page(s) to NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
- * @param NumPageToWrite : number of pages to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Page(s) write loop */
- while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
-
- /* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written pages number */
- numPagesWritten++;
-
- /* Decrement pages to write */
- NumPageToWrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaToRead: Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read Spare area(s) from NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaToRead: Number of spare area to read
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
-
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-
- if(hnand->Config.ExtraCommandEnable == ENABLE)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- }
-
- /* Get Data into Buffer */
- for(; index < size; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
- }
-
- /* Increment read spare areas number */
- numSpareAreaRead++;
-
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the FSMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Page address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = COLUMN_ADDRESS(hnand);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief Write Spare area(s) to NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaTowrite : number of spare areas to write to block
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
-{
- __IO uint32_t index = 0U;
- uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the FSMC_NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* NAND raw address calculation */
- nandaddress = ARRAY_ADDRESS(pAddress, hnand);
-
- /* Column in page address */
- columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
-
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- {
- /* update the buffer size */
- size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
-
- /* Cards with page size <= 512 bytes */
- if((hnand->Config.PageSize) <= 512U)
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
- else /* (hnand->Config.PageSize) > 512 */
- {
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- }
- else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- }
- }
-
- /* Write data to memory */
- for(; index < size; index++)
- {
- *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Increment written spare areas number */
- numSpareAreaWritten++;
-
- /* Decrement spare areas to write */
- NumSpareAreaTowrite--;
-
- /* Increment the NAND address */
- nandaddress = (uint32_t)(nandaddress + 1U);
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory Block erase
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t deviceaddress = 0U;
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnand);
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
-
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_READY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Read status until NAND is ready */
- while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
-}
-
-/**
- * @brief NAND memory read status
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval NAND status
- */
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
-{
- uint32_t data = 0U;
- uint32_t deviceaddress = 0U;
-
- /* Identify the device address */
- if(hnand->Init.NandBank == FSMC_NAND_BANK2)
- {
- deviceaddress = NAND_DEVICE1;
- }
- else
- {
- deviceaddress = NAND_DEVICE2;
- }
-
- /* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
-
- /* Read status register data */
- data = *(__IO uint8_t *)deviceaddress;
-
- /* Return the status */
- if((data & NAND_ERROR) == NAND_ERROR)
- {
- return NAND_ERROR;
- }
- else if((data & NAND_READY) == NAND_READY)
- {
- return NAND_READY;
- }
-
- return NAND_BUSY;
-}
-
-/**
- * @brief Increment the NAND memory address
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @retval The new status of the increment address operation. It can be:
- * - NAND_VALID_ADDRESS: When the new address is valid address
- * - NAND_INVALID_ADDRESS: When the new address is invalid address
- */
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
-{
- uint32_t status = NAND_VALID_ADDRESS;
-
- /* Increment page address */
- pAddress->Page++;
-
- /* Check NAND address is valid */
- if(pAddress->Page == hnand->Config.BlockSize)
- {
- pAddress->Page = 0U;
- pAddress->Block++;
-
- if(pAddress->Block == hnand->Config.PlaneSize)
- {
- pAddress->Block = 0U;
- pAddress->Plane++;
-
- if(pAddress->Plane == (hnand->Config.PlaneNbr))
- {
- status = NAND_INVALID_ADDRESS;
- }
- }
- }
-
- return (status);
-}
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NAND interface.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Enable ECC feature */
- FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FSMC_NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
-{
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Disable ECC feature */
- FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param ECCval: pointer to ECC value
- * @param Timeout: maximum timeout to wait
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check the NAND controller state */
- if(hnand->State == HAL_NAND_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Get NAND ECC value */
- status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
-
- /* Update the NAND state */
- hnand->State = HAL_NAND_STATE_READY;
-
- return status;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NAND State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NAND controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NAND state
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @retval HAL state
- */
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
-{
- return hnand->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_nor.c b/lib/hal-stm32f1/source/stm32f1xx_hal_nor.c deleted file mode 100644 index 598b8ada..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_nor.c +++ /dev/null @@ -1,1060 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_nor.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief NOR HAL module driver.
- * This file provides a generic firmware to drive NOR memories mounted
- * as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control NOR flash memories. It uses the FSMC layer functions to interface
- with NOR devices. This driver is used as follows:
-
- (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
- with control and timing parameters for both normal and extended mode.
-
- (+) Read NOR flash memory manufacturer code and device IDs using the function
- HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
- structure declared by the function caller.
-
- (+) Access NOR flash memory by read/write data unit operations using the functions
- HAL_NOR_Read(), HAL_NOR_Program().
-
- (+) Perform NOR flash erase block/chip operations using the functions
- HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-
- (+) Read the NOR flash CFI (common flash interface) IDs using the function
- HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
- structure declared by the function caller.
-
- (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
- HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
-
- (+) You can monitor the NOR device HAL state by calling the function
- HAL_NOR_GetState()
- [..]
- (@) This driver is a set of generic APIs which handle standard NOR flash operations.
- If a NOR flash device contains different operations and/or implementations,
- it should be implemented separately.
-
- *** NOR HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in NOR HAL driver.
-
- (+) NOR_WRITE : NOR memory write data to specified address
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-
-/** @defgroup NOR NOR
- * @brief NOR driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
- * @{
- */
-
-/* Constants to define address to set to write a command */
-#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
-#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
-#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
-#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
-
-/* Constants to define data to program a command */
-#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
-#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
-#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
-#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
-#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
-#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
-#define NOR_CMD_DATA_CFI (uint16_t)0x0098
-
-#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
-#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
-#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
-
-/* Mask on NOR STATUS REGISTER */
-#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
-#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup NOR_Private_Macros NOR Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Variables NOR Private Variables
- * @{
- */
-
-static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timing: pointer to NOR control timing structure
- * @param ExtTiming: pointer to NOR extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the NOR handle parameter */
- if(hnor == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hnor->State == HAL_NOR_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hnor->Lock = HAL_UNLOCKED;
-
- /* Initialize the low level hardware (MSP) */
- HAL_NOR_MspInit(hnor);
- }
-
- /* Initialize NOR control Interface */
- FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
-
- /* Initialize NOR timing Interface */
- FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
-
- /* Initialize NOR extended mode timing Interface */
- FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
-
- /* Initialize NOR Memory Data Width*/
- if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
- {
- uwNORMemoryDataWidth = NOR_MEMORY_8B;
- }
- else
- {
- uwNORMemoryDataWidth = NOR_MEMORY_16B;
- }
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_NOR_MspDeInit(hnor);
-
- /* Configure the NOR registers with their reset values */
- FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief NOR MSP Init
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP DeInit
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval None
- */
-__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief NOR MSP Wait fro Ready/Busy signal
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Timeout: Maximum timeout value
- * @retval None
- */
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hnor);
- UNUSED(Timeout);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_NOR_MspWait could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### NOR Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the NOR memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read NOR flash IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_ID : pointer to NOR ID structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read data from NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress: pointer to Device address
- * @param pData : pointer to read data
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
-
- /* Read the data */
- *pData = *(__IO uint32_t *)(uint32_t)pAddress;
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Program data to NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pAddress: Device address
- * @param pData : pointer to the data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a block of data from the FSMC NOR memory.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param uwAddress: NOR memory internal address to read from.
- * @param pData: pointer to the buffer that receives the data read from the
- * NOR memory.
- * @param uwBufferSize : number of Half word to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while( uwBufferSize > 0U)
- {
- *pData++ = *(__IO uint16_t *)uwAddress;
- uwAddress += 2U;
- uwBufferSize--;
- }
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a half-word buffer to the FSMC NOR memory. This function
- * must be used only with S29GL128P NOR memory.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param uwAddress: NOR memory internal address from which the data
- * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
- * 64 bytes boundary for example).
- * @param pData: pointer to source data buffer.
- * @param uwBufferSize: number of Half words to write.
- * @note The maximum buffer size allowed is NOR memory dependent
- * (can be 64 Bytes max for example).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
- uint16_t * p_currentaddress = (uint16_t *)NULL;
- uint16_t * p_endaddress = (uint16_t *)NULL;
- uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Initialize variables */
- p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
- p_endaddress = p_currentaddress + (uwBufferSize-1U);
- lastloadedaddress = (uint32_t)(uwAddress);
-
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
-
- /* Load Data into NOR Buffer */
- while(p_currentaddress <= p_endaddress)
- {
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
-
- NOR_WRITE(p_currentaddress, *pData++);
-
- p_currentaddress++;
- }
-
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param BlockAddress : Block to erase address
- * @param Address: Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Erase the entire NOR chip.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address : Device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Address);
-
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-
- /* Check the NOR memory status and update the controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read NOR flash CFI IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param pNOR_CFI : pointer to NOR CFI IDs structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
-{
- uint32_t deviceaddress = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Select the NOR device address */
- if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
- {
- deviceaddress = NOR_MEMORY_ADRESS1;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
- {
- deviceaddress = NOR_MEMORY_ADRESS2;
- }
- else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
- {
- deviceaddress = NOR_MEMORY_ADRESS3;
- }
- else /* FSMC_NORSRAM_BANK4 */
- {
- deviceaddress = NOR_MEMORY_ADRESS4;
- }
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
- /* read the NOR CFI information */
- pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
- pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
- pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
- pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
-
- /* Check the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group3 Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### NOR Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the NOR interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Enable write operation */
- FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
-{
- /* Process Locked */
- __HAL_LOCK(hnor);
-
- /* Update the SRAM controller state */
- hnor->State = HAL_NOR_STATE_BUSY;
-
- /* Disable write operation */
- FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
-
- /* Update the NOR controller state */
- hnor->State = HAL_NOR_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hnor);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup NOR_Exported_Functions_Group4 State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### NOR State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the NOR controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the NOR controller state
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @retval NOR controller state
- */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
-{
- return hnor->State;
-}
-
-/**
- * @brief Returns the NOR operation status.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
- * the configuration information for NOR module.
- * @param Address: Device address
- * @param Timeout: NOR progamming Timeout
- * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
- * or HAL_NOR_STATUS_TIMEOUT
- */
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{
- HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
- uint32_t tickstart = 0U;
-
- /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
- HAL_NOR_MspWait(hnor, Timeout);
-
- /* Get tick */
- tickstart = HAL_GetTick();
- while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- status = HAL_NOR_STATUS_TIMEOUT;
- }
- }
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmp_sr1 = *(__IO uint16_t *)Address;
- tmp_sr2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS;
- }
-
- if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
-
- tmp_sr1 = *(__IO uint16_t *)Address;
- tmp_sr2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return NOR_Success */
- if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
- {
- return HAL_NOR_STATUS_SUCCESS;
- }
- else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- return HAL_NOR_STATUS_ERROR;
- }
- }
-
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_pccard.c b/lib/hal-stm32f1/source/stm32f1xx_hal_pccard.c deleted file mode 100644 index 77240743..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_pccard.c +++ /dev/null @@ -1,748 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_pccard.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief PCCARD HAL module driver.
- * This file provides a generic firmware to drive PCCARD memories mounted
- * as external device.
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control PCCARD/compact flash memories. It uses the FSMC/FSMC layer functions
- to interface with PCCARD devices. This driver is used for:
-
- (+) PCCARD/compact flash memory configuration sequence using the function
- HAL_PCCARD_Init() with control and timing parameters for both common and
- attribute spaces.
-
- (+) Read PCCARD/compact flash memory maker and device IDs using the function
- HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
- structure declared by the function caller.
-
- (+) Access PCCARD/compact flash memory by read/write operations using the functions
- HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
-
- (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
-
- (+) Perform PCCARD/compact flash erase sector operation using the function
- HAL_PCCARD_Erase_Sector().
-
- (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
-
- (+) You can monitor the PCCARD/compact flash device HAL state by calling the function
- HAL_PCCARD_GetState()
-
- [..]
- (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
- operations. If a PCCARD/compact flash device contains different operations
- and/or implementations, it should be implemented separately.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-
-/** @defgroup PCCARD PCCARD
- * @brief PCCARD HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
- * @{
- */
-
-#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
-#define PCCARD_TIMEOUT_SECTOR 0x0000FFFFU
-#define PCCARD_TIMEOUT_STATUS 0x01000000U
-
-#define PCCARD_STATUS_OK (uint8_t)0x58
-#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
- * @{
- */
-
-/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### PCCARD Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize
- the PCCARD memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Perform the PCCARD memory Initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @param ComSpaceTiming: Common space timing structure
- * @param AttSpaceTiming: Attribute space timing structure
- * @param IOSpaceTiming: IO space timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
-{
- /* Check the PCCARD controller state */
- if(hpccard == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hpccard->State == HAL_PCCARD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hpccard->Lock = HAL_UNLOCKED;
-
- /* Initialize the low level hardware (MSP) */
- HAL_PCCARD_MspInit(hpccard);
- }
-
- /* Initialize the PCCARD state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize PCCARD control Interface */
- FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
-
- /* Init PCCARD common space timing Interface */
- FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
-
- /* Init PCCARD attribute space timing Interface */
- FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
-
- /* Init PCCARD IO space timing Interface */
- FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
-
- /* Enable the PCCARD device */
- __FSMC_PCCARD_ENABLE(hpccard->Instance);
-
- /* Update the PCCARD state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Perform the PCCARD memory De-initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_PCCARD_MspDeInit(hpccard);
-
- /* Configure the PCCARD registers with their reset values */
- FSMC_PCCARD_DeInit(hpccard->Instance);
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-/**
- * @brief PCCARD MSP Init
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval None
- */
-__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpccard);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCCARD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief PCCARD MSP DeInit
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval None
- */
-__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpccard);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCCARD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### PCCARD Input Output and memory functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the PCCARD memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read Compact Flash's ID.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @param CompactFlash_ID: Compact flash ID structure.
- * @param pStatus: pointer to compact flash status
- * @retval HAL status
- *
- */
-HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
-{
- uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
- uint8_t status = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hpccard);
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize the CF status */
- *pStatus = PCCARD_READY;
-
- /* Send the Identify Command */
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU;
-
- /* Read CF IDs and timeout treatment */
- do
- {
- /* Read the CF status */
- status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-
- timeout--;
- }while((status != PCCARD_STATUS_OK) && timeout);
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
- else
- {
- /* Read CF ID bytes */
- for(index = 0U; index < 16U; index++)
- {
- CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
- }
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @param pBuffer: pointer to destination read buffer
- * @param SectorAddress: Sector address to read
- * @param pStatus: pointer to CF status
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
-{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
- uint8_t status = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hpccard);
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize CF status */
- *pStatus = PCCARD_READY;
-
- /* Set the parameters to write a sector */
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
-
- do
- {
- /* wait till the Status = 0x80 */
- status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }while((status == 0x80U) && timeout);
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
-
- timeout = 0xFFFFU;
-
- do
- {
- /* wait till the Status = PCCARD_STATUS_OK */
- status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }while((status != PCCARD_STATUS_OK) && timeout);
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
-
- /* Read bytes */
- for(; index < PCCARD_SECTOR_SIZE; index++)
- {
- *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Write sector to PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @param pBuffer: pointer to source write buffer
- * @param SectorAddress: Sector address to write
- * @param pStatus: pointer to CF status
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
-{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
- uint8_t status = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hpccard);
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize CF status */
- *pStatus = PCCARD_READY;
-
- /* Set the parameters to write a sector */
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
-
- do
- {
- /* Wait till the Status = PCCARD_STATUS_OK */
- status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }while((status != PCCARD_STATUS_OK) && timeout);
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
-
- /* Write bytes */
- for(; index < PCCARD_SECTOR_SIZE; index++)
- {
- *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
- }
-
- do
- {
- /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
- status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Erase sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @param SectorAddress: Sector address to erase
- * @param pStatus: pointer to CF status
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
-{
- uint32_t timeout = 0x400U;
- uint8_t status = 0;
-
- /* Process Locked */
- __HAL_LOCK(hpccard);
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Update the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- /* Initialize CF status */
- *pStatus = PCCARD_READY;
-
- /* Set the parameters to write a sector */
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
- *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
-
- /* wait till the CF is ready */
- status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-
- while((status != PCCARD_STATUS_WRITE_OK) && timeout)
- {
- status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }
-
- if(timeout == 0U)
- {
- *pStatus = PCCARD_TIMEOUT_ERROR;
- }
-
- /* Check the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reset the PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
-{
- /* Process Locked */
- __HAL_LOCK(hpccard);
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_BUSY;
- }
-
- /* Provide an SW reset and Read and verify the:
- - CF Configuration Option Register at address 0x98000200 --> 0x80
- - Card Configuration and Status Register at address 0x98000202 --> 0x00
- - Pin Replacement Register at address 0x98000204 --> 0x0C
- - Socket and Copy Register at address 0x98000206 --> 0x00
- */
-
- /* Check the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_BUSY;
-
- *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
-
- /* Check the PCCARD controller state */
- hpccard->State = HAL_PCCARD_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hpccard);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles PCCARD device interrupt request.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval HAL status
-*/
-void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
-{
- /* Check PCCARD interrupt Rising edge flag */
- if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
- {
- /* PCCARD interrupt callback*/
- HAL_PCCARD_ITCallback(hpccard);
-
- /* Clear PCCARD interrupt Rising edge pending bit */
- __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
- }
-
- /* Check PCCARD interrupt Level flag */
- if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
- {
- /* PCCARD interrupt callback*/
- HAL_PCCARD_ITCallback(hpccard);
-
- /* Clear PCCARD interrupt Level pending bit */
- __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
- }
-
- /* Check PCCARD interrupt Falling edge flag */
- if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
- {
- /* PCCARD interrupt callback*/
- HAL_PCCARD_ITCallback(hpccard);
-
- /* Clear PCCARD interrupt Falling edge pending bit */
- __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
- }
-
- /* Check PCCARD interrupt FIFO empty flag */
- if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
- {
- /* PCCARD interrupt callback*/
- HAL_PCCARD_ITCallback(hpccard);
-
- /* Clear PCCARD interrupt FIFO empty pending bit */
- __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
- }
-
-}
-
-/**
- * @brief PCCARD interrupt feature callback
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval None
- */
-__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpccard);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCCARD_ITCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### PCCARD Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the PCCARD controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the PCCARD controller state
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval HAL state
- */
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
-{
- return hpccard->State;
-}
-
-/**
- * @brief Get the compact flash memory status
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval New status of the CF operation. This parameter can be:
- * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
- * a Timeout error
- * - CompactFlash_READY: when memory is ready for the next operation
- *
- */
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
-{
- uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_PCCARD_STATUS_ONGOING;
- }
-
- status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-
- while((status_cf == PCCARD_BUSY) && timeout)
- {
- status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
- timeout--;
- }
-
- if(timeout == 0U)
- {
- status_cf = PCCARD_TIMEOUT_ERROR;
- }
-
- /* Return the operation status */
- return (HAL_PCCARD_StatusTypeDef) status_cf;
-}
-
-/**
- * @brief Reads the Compact Flash memory status using the Read status command
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
- * the configuration information for PCCARD module.
- * @retval The status of the Compact Flash memory. This parameter can be:
- * - CompactFlash_BUSY: when memory is busy
- * - CompactFlash_READY: when memory is ready for the next operation
- * - CompactFlash_ERROR: when the previous operation gererates error
- */
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
-{
- uint8_t data = 0U, status_cf = PCCARD_BUSY;
-
- /* Check the PCCARD controller state */
- if(hpccard->State == HAL_PCCARD_STATE_BUSY)
- {
- return HAL_PCCARD_STATUS_ONGOING;
- }
-
- /* Read status operation */
- data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-
- if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
- {
- status_cf = PCCARD_TIMEOUT_ERROR;
- }
- else if((data & PCCARD_READY) == PCCARD_READY)
- {
- status_cf = PCCARD_READY;
- }
-
- return (HAL_PCCARD_StatusTypeDef) status_cf;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_pcd.c b/lib/hal-stm32f1/source/stm32f1xx_hal_pcd.c deleted file mode 100644 index 5a73a2a8..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_pcd.c +++ /dev/null @@ -1,1426 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_pcd.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The PCD HAL driver can be used as follows:
-
- (#) Declare a PCD_HandleTypeDef handle structure, for example:
- PCD_HandleTypeDef hpcd;
-
- (#) Fill parameters of Init structure in HCD handle
-
- (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
-
- (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
- (##) Enable the PCD/USB Low Level interface clock using the following macro
- (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available
- on STM32F102xx and STM32F103xx devices
- (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available
- on STM32F105xx and STM32F107xx devices
-
- (##) Initialize the related GPIO clocks
- (##) Configure PCD pin-out
- (##) Configure PCD NVIC interrupt
-
- (#)Associate the Upper USB device stack to the HAL PCD Driver:
- (##) hpcd.pData = pdev;
-
- (#)Enable HCD transmission and reception:
- (##) HAL_PCD_Start();
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @defgroup PCD PCD
- * @brief PCD HAL module driver
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-#if defined (USB_OTG_FS)
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-#endif /* USB */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
- uint32_t index = 0U;
-
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
- if(hpcd->State == HAL_PCD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hpcd->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
-
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
-
- /* Init endpoints structures */
- for (index = 0U; index < 15U ; index++)
- {
- /* Init ep structure */
- hpcd->IN_ep[index].is_in = 1U;
- hpcd->IN_ep[index].num = index;
- hpcd->IN_ep[index].tx_fifo_num = index;
- /* Control until ep is actvated */
- hpcd->IN_ep[index].type = EP_TYPE_CTRL;
- hpcd->IN_ep[index].maxpacket = 0U;
- hpcd->IN_ep[index].xfer_buff = 0U;
- hpcd->IN_ep[index].xfer_len = 0U;
- }
-
- for (index = 0U; index < 15U ; index++)
- {
- hpcd->OUT_ep[index].is_in = 0U;
- hpcd->OUT_ep[index].num = index;
- hpcd->IN_ep[index].tx_fifo_num = index;
- /* Control until ep is activated */
- hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
- hpcd->OUT_ep[index].maxpacket = 0U;
- hpcd->OUT_ep[index].xfer_buff = 0U;
- hpcd->OUT_ep[index].xfer_len = 0U;
- }
-
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
-
- hpcd->USB_Address = 0U;
- hpcd->State= HAL_PCD_STATE_READY;
-
- USB_DevDisconnect (hpcd->Instance);
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the PCD peripheral
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Check the PCD handle allocation */
- if(hpcd == NULL)
- {
- return HAL_ERROR;
- }
-
- hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Stop Device */
- HAL_PCD_Stop(hpcd);
-
- /* DeInit the low level hardware */
- HAL_PCD_MspDeInit(hpcd);
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the PCD MSP.
- * @param hpcd: PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes PCD MSP.
- * @param hpcd: PCD handle
- * @retval None
- */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Start The USB Device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- HAL_PCDEx_SetConnectionState (hpcd, 1);
- USB_DevConnect (hpcd->Instance);
- __HAL_PCD_ENABLE(hpcd);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Stop The USB Device.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- __HAL_PCD_DISABLE(hpcd);
- USB_StopDevice(hpcd->Instance);
- USB_DevDisconnect (hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-#if defined (USB_OTG_FS)
-/**
- * @brief This function handles PCD interrupt request.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
- uint32_t fifoemptymsk = 0U, temp = 0U;
- USB_OTG_EPTypeDef *ep = NULL;
-
- /* ensure that we are in device mode */
- if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
- {
- /* avoid spurious interrupt */
- if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
- {
- return;
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
- {
- /* incorrect mode, acknowledge the interrupt */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
- {
- epnum = 0U;
-
- /* Read in the device interrupt bits */
- ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-
- while ( ep_intr )
- {
- if (ep_intr & 0x1U)
- {
- epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-
- if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
- HAL_PCD_DataOutStageCallback(hpcd, epnum);
- }
-
- if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
- {
- /* Inform the upper layer that a setup packet is available */
- HAL_PCD_SetupStageCallback(hpcd);
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
- }
-
- if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
- {
- CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
- }
- }
- epnum++;
- ep_intr >>= 1U;
- }
- }
-
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
- {
- /* Read in the device interrupt bits */
- ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-
- epnum = 0U;
-
- while ( ep_intr )
- {
- if (ep_intr & 0x1U) /* In ITR */
- {
- epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-
- if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
- {
- fifoemptymsk = 0x1U << epnum;
- USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-
- HAL_PCD_DataInStageCallback(hpcd, epnum);
- }
- if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
- }
- if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
- }
- if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
- }
- if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
- {
- CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
- }
- if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
- {
- PCD_WriteEmptyTxFifo(hpcd , epnum);
- }
- }
- epnum++;
- ep_intr >>= 1U;
- }
- }
-
- /* Handle Resume Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
- {
- /* Clear the Remote Wake-up signalling */
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
- HAL_PCD_ResumeCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
- }
-
- /* Handle Suspend Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
- {
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
-
- HAL_PCD_SuspendCallback(hpcd);
- }
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
- }
-
- /* Handle Reset Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
- {
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
- USB_FlushTxFifo(hpcd->Instance , 0x10U);
-
- for (index = 0U; index < hpcd->Init.dev_endpoints ; index++)
- {
- USBx_INEP(index)->DIEPINT = 0xFFU;
- USBx_OUTEP(index)->DOEPINT = 0xFFU;
- }
- USBx_DEVICE->DAINT = 0xFFFFFFFFU;
- USBx_DEVICE->DAINTMSK |= 0x10001U;
-
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
-
- /* Set Default Address to 0 */
- USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-
- /* setup EP0 to receive SETUP packets */
- USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
- }
-
- /* Handle Enumeration done Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
- {
- USB_ActivateSetup(hpcd->Instance);
- hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
- hpcd->Init.speed = USB_OTG_SPEED_FULL;
- hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
-
- HAL_PCD_ResetCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
- }
-
- /* Handle RxQLevel Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
- {
- USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- temp = USBx->GRXSTSP;
- ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
- if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
- {
- if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
- {
- USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
- }
- }
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
- {
- USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
- }
- USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
-
- /* Handle SOF Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
- {
- HAL_PCD_SOFCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
- }
-
- /* Handle Incomplete ISO IN Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
- {
- HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
- }
-
- /* Handle Incomplete ISO OUT Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
- {
- HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
- }
-
- /* Handle Connection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
- {
- HAL_PCD_ConnectCallback(hpcd);
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
- }
-
- /* Handle Disconnection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
- {
- temp = hpcd->Instance->GOTGINT;
-
- if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
- {
- HAL_PCD_DisconnectCallback(hpcd);
- }
- hpcd->Instance->GOTGINT |= temp;
- }
- }
-}
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/**
- * @brief This function handles PCD interrupt request.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
- {
- /* servicing of the endpoint correct transfer interrupt */
- /* clear of the CTR flag into the sub */
- PCD_EP_ISR_Handler(hpcd);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
- HAL_PCD_ResetCallback(hpcd);
- HAL_PCD_SetAddress(hpcd, 0U);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
- }
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
- {
- hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE);
- hpcd->Instance->CNTR &= ~(USB_CNTR_FSUSP);
-
- HAL_PCD_ResumeCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
- {
- /* Force low-power mode in the macrocell */
- hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
-
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
- hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
- {
- HAL_PCD_SuspendCallback(hpcd);
- }
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
- {
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
- HAL_PCD_SOFCallback(hpcd);
- }
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
- {
- /* clear ESOF flag in ISTR */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
- }
-}
-#endif /* USB */
-
-/**
- * @brief Data out stage callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Data IN stage callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DataInStageCallback could be implemented in the user file
- */
-}
-/**
- * @brief Setup stage callback
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Start Of Frame callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SOFCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USB Reset callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResetCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Suspend event callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_SuspendCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Resume event callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ResumeCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO OUT callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Incomplete ISO IN callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
- * @retval None
- */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(epnum);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Connection event callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_ConnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Disconnection event callbacks
- * @param hpcd: PCD handle
- * @retval None
- */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Connect the USB device
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- HAL_PCDEx_SetConnectionState (hpcd, 1);
- USB_DevConnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Disconnect the USB device
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- HAL_PCDEx_SetConnectionState (hpcd, 0U);
- USB_DevDisconnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-/**
- * @brief Set the USB Device address
- * @param hpcd: PCD handle
- * @param address: new device address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
- __HAL_LOCK(hpcd);
- hpcd->USB_Address = address;
- USB_SetDevAddress(hpcd->Instance, address);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-/**
- * @brief Open and configure an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint type
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
- HAL_StatusTypeDef ret = HAL_OK;
- PCD_EPTypeDef *ep = NULL;
-
- if ((ep_addr & 0x80U) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
- }
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
-
- __HAL_LOCK(hpcd);
- USB_ActivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
- return ret;
-}
-
-/**
- * @brief Deactivate an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep = NULL;
-
- if ((ep_addr & 0x80U) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
- }
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
-
- __HAL_LOCK(hpcd);
- USB_DeactivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the reception buffer
- * @param len: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
- PCD_EPTypeDef *ep = NULL;
-
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0U;
- ep->is_in = 0U;
- ep->num = ep_addr & 0x7FU;
-
- if ((ep_addr & 0x7FU) == 0U)
- {
- USB_EP0StartXfer(hpcd->Instance , ep);
- }
- else
- {
- USB_EPStartXfer(hpcd->Instance , ep);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Get Received Data Size
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval Data Size
- */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
-}
-/**
- * @brief Send an amount of data
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the transmission buffer
- * @param len: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
- PCD_EPTypeDef *ep = NULL;
-
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pBuf;
- ep->xfer_len = len;
- ep->xfer_count = 0U;
- ep->is_in = 1U;
- ep->num = ep_addr & 0x7FU;
-
- if ((ep_addr & 0x7FU) == 0U)
- {
- USB_EP0StartXfer(hpcd->Instance , ep);
- }
- else
- {
- USB_EPStartXfer(hpcd->Instance , ep);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set a STALL condition over an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep = NULL;
-
- if ((0x80U & ep_addr) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 1U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- __HAL_LOCK(hpcd);
- USB_EPSetStall(hpcd->Instance , ep);
- if((ep_addr & 0x7FU) == 0U)
- {
- USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
- }
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Clear a STALL condition over in an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- PCD_EPTypeDef *ep = NULL;
-
- if ((0x80U & ep_addr) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- ep->is_stall = 0U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- __HAL_LOCK(hpcd);
- USB_EPClearStall(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief Flush an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
- __HAL_LOCK(hpcd);
-
- if ((ep_addr & 0x80U) == 0x80U)
- {
- USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
- }
- else
- {
- USB_FlushRxFifo(hpcd->Instance);
- }
-
- __HAL_UNLOCK(hpcd);
-
- return HAL_OK;
-}
-
-/**
- * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- return(USB_ActivateRemoteWakeup(hpcd->Instance));
-}
-
-/**
- * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
- return(USB_DeActivateRemoteWakeup(hpcd->Instance));
-}
-/**
- * @}
- */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the PCD state
- * @param hpcd: PCD handle
- * @retval HAL state
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
- return hpcd->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup PCD_Private_Functions
- * @{
- */
-#if defined (USB_OTG_FS)
-/**
- * @brief DCD_WriteEmptyTxFifo
- * check FIFO for the next packet to be loaded
- * @param hpcd: PCD handle
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
-{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- USB_OTG_EPTypeDef *ep = NULL;
- int32_t len = 0;
- uint32_t len32b = 0U;
- uint32_t fifoemptymsk = 0U;
-
- ep = &hpcd->IN_ep[epnum];
- len = ep->xfer_len - ep->xfer_count;
-
- if (len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
-
- len32b = (len + 3U) / 4U;
-
- while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
- ep->xfer_count < ep->xfer_len &&
- ep->xfer_len != 0U)
- {
- /* Write the FIFO */
- len = ep->xfer_len - ep->xfer_count;
-
- if ((uint32_t)len > ep->maxpacket)
- {
- len = ep->maxpacket;
- }
- len32b = (len + 3U) / 4U;
-
- USB_WritePacket(USBx, ep->xfer_buff, epnum, len);
-
- ep->xfer_buff += len;
- ep->xfer_count += len;
- }
-
- if(len <= 0)
- {
- fifoemptymsk = 0x01U << epnum;
- USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-
- }
-
- return HAL_OK;
-}
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/**
- * @brief This function handles PCD Endpoint interrupt request.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
- PCD_EPTypeDef *ep = NULL;
- uint16_t count = 0;
- uint8_t epindex = 0;
- __IO uint16_t wIstr = 0;
- __IO uint16_t wEPVal = 0;
-
- /* stay in loop while pending interrupts */
- while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
- {
- /* extract highest priority endpoint number */
- epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
- if (epindex == 0)
- {
- /* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
- if ((wIstr & USB_ISTR_DIR) == 0)
- {
- /* DIR = 0 */
-
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- ep = &hpcd->IN_ep[0];
-
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, 0U);
-
-
- if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
- {
- hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0U;
- }
-
- }
- else
- {
- /* DIR = 1 */
-
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
- /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &hpcd->OUT_ep[0U];
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
- if ((wEPVal & USB_EP_SETUP) != 0U)
- {
- /* Get SETUP Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
- /* Process SETUP Packet*/
- HAL_PCD_SetupStageCallback(hpcd);
- }
-
- else if ((wEPVal & USB_EP_CTR_RX) != 0U)
- {
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- /* Get Control Data OUT Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_count != 0U)
- {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- ep->xfer_buff+=ep->xfer_count;
- }
-
- /* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0U);
-
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
- }
- }
- }
- else
- {
- /* Decode and service non control endpoints interrupt */
-
- /* process related endpoint register */
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
- if ((wEPVal & USB_EP_CTR_RX) != 0U)
- {
- /* clear int flag */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
- ep = &hpcd->OUT_ep[epindex];
-
- /* OUT double Buffering*/
- if (ep->doublebuffer == 0U)
- {
- count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
- }
- }
- else
- {
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
- {
- /*read from endpoint BUF0Addr buffer*/
- count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
- }
- /*multi-packet on the NON control OUT endpoint*/
- ep->xfer_count+=count;
- ep->xfer_buff+=count;
-
- if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
- {
- /* RX COMPLETE */
- HAL_PCD_DataOutStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
-
- } /* if((wEPVal & EP_CTR_RX) */
-
- if ((wEPVal & USB_EP_CTR_TX) != 0U)
- {
- ep = &hpcd->IN_ep[epindex];
-
- /* clear int flag */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
-
- /* IN double Buffering*/
- if (ep->doublebuffer == 0U)
- {
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- }
- }
- else
- {
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
- {
- /*read from endpoint BUF0Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
- }
- /*multi-packet on the NON control IN endpoint*/
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff+=ep->xfer_count;
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
- {
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
- }
- }
- }
- return HAL_OK;
-}
-#endif /* USB */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_pcd_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_pcd_ex.c deleted file mode 100644 index 602a51d7..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_pcd_ex.c +++ /dev/null @@ -1,252 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_pcd_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief Extended PCD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Extended features functions: Update FIFO configuration,
- * PMA configuration for EPs
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-
-/** @defgroup PCDEx PCDEx
- * @brief PCD Extended HAL module driver
- * @{
- */
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-
-/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief PCDEx control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Update FIFO (USB_OTG_FS)
- (+) Update PMA configuration (USB)
-
-@endverbatim
- * @{
- */
-
-#if defined (USB_OTG_FS)
-/**
- * @brief Set Tx FIFO
- * @param hpcd: PCD handle
- * @param fifo: The number of Tx fifo
- * @param size: Fifo size
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
-{
- uint8_t index = 0;
- uint32_t Tx_Offset = 0U;
-
- /* TXn min size = 16 words. (n : Transmit FIFO index)
- When a TxFIFO is not used, the Configuration should be as follows:
- case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
- --> Txm can use the space allocated for Txn.
- case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
- --> Txn should be configured with the minimum space of 16 words
- The FIFO is used optimally when used TxFIFOs are allocated in the top
- of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
- When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-
- Tx_Offset = hpcd->Instance->GRXFSIZ;
-
- if(fifo == 0U)
- {
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16U) | Tx_Offset;
- }
- else
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
- for(index = 0; index < (fifo - 1); index++)
- {
- Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16U);
- }
-
- /* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1U] = (size << 16U) | Tx_Offset;
-
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Set Rx FIFO
- * @param hpcd: PCD handle
- * @param size: Size of Rx fifo
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
-{
- hpcd->Instance->GRXFSIZ = size;
- return HAL_OK;
-}
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/**
- * @brief Configure PMA for EP
- * @param hpcd : Device instance
- * @param ep_addr: endpoint address
- * @param ep_kind: endpoint Kind
- * USB_SNG_BUF: Single Buffer used
- * USB_DBL_BUF: Double Buffer used
- * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
- * this parameter is 16-bit value providing the address
- * in PMA allocated to endpoint.
- * In case of double buffer endpoint this parameter
- * is a 32-bit value providing the endpoint buffer 0 address
- * in the LSB part of 32-bit value and endpoint buffer 1 address
- * in the MSB part of 32-bit value.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
-
-{
- PCD_EPTypeDef *ep = NULL;
-
- /* initialize ep structure*/
- if ((ep_addr & 0x80U) == 0x80U)
- {
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
- }
- else
- {
- ep = &hpcd->OUT_ep[ep_addr];
- }
-
- /* Here we check if the endpoint is single or double Buffer*/
- if (ep_kind == PCD_SNG_BUF)
- {
- /*Single Buffer*/
- ep->doublebuffer = 0U;
- /*Configure te PMA*/
- ep->pmaadress = (uint16_t)pmaadress;
- }
- else /*USB_DBL_BUF*/
- {
- /*Double Buffer Endpoint*/
- ep->doublebuffer = 1U;
- /*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0x0000FFFFU;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
- }
-
- return HAL_OK;
-}
-#endif /* USB */
-/**
- * @}
- */
-
-/** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions
- * @brief Manage device connection state
- * @{
- */
-/**
- * @brief Software Device Connection,
- * this function is not required by USB OTG FS peripheral, it is used
- * only by USB Device FS peripheral.
- * @param hpcd: PCD handle
- * @param state: connection state (0 : disconnected / 1: connected)
- * @retval None
- */
-__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(state);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCDEx_SetConnectionState could be implemented in the user file
- */
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_pwr.c b/lib/hal-stm32f1/source/stm32f1xx_hal_pwr.c deleted file mode 100644 index 0261be65..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_pwr.c +++ /dev/null @@ -1,639 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_pwr.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief PWR HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PWR PWR
- * @brief PWR HAL module driver
- * @{
- */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
- * @{
- */
-#define PVD_MODE_IT 0x00010000U
-#define PVD_MODE_EVT 0x00020000U
-#define PVD_RISING_EDGE 0x00000001U
-#define PVD_FALLING_EDGE 0x00000002U
-/**
- * @}
- */
-
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
- * @{
- */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET 0x00U
-#define PWR_CSR_OFFSET 0x04U
-#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
- * @}
- */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
- * @{
- */
-/* --- CR Register ---*/
-/* Alias word address of LPSDSR bit */
-#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
-#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
-
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
-#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
-#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
- * @{
- */
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP1 bit */
-#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup PWR_Private_Functions PWR Private Functions
- * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
- * @{
- */
-static void PWR_OverloadWfe(void);
-
-/* Private functions ---------------------------------------------------------*/
-__NOINLINE
-static void PWR_OverloadWfe(void)
-{
- __asm volatile( "wfe" );
- __asm volatile( "nop" );
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- After reset, the backup domain (RTC registers, RTC backup data
- registers) is protected against possible unwanted
- write accesses.
- To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() macro.
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @retval None
- */
-void HAL_PWR_DeInit(void)
-{
- __HAL_RCC_PWR_FORCE_RESET();
- __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
- * @brief Enables access to the backup domain (RTC registers, RTC
- * backup data registers ).
- * @note If the HSE divided by 128 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_EnableBkUpAccess(void)
-{
- /* Enable access to RTC and backup registers */
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables access to the backup domain (RTC registers, RTC
- * backup data registers).
- * @note If the HSE divided by 128 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @retval None
- */
-void HAL_PWR_DisableBkUpAccess(void)
-{
- /* Disable access to RTC and backup registers */
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
-
- *** PVD configuration ***
- =========================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a
- threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
- than the PVD threshold. This event is internally connected to the EXTI
- line16 and can generate an interrupt if enabled. This is done through
- __HAL_PVD_EXTI_ENABLE_IT() macro.
- (+) The PVD is stopped in Standby mode.
-
- *** WakeUp pin configuration ***
- ================================
- [..]
- (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
- forced in input pull-down configuration and is active on rising edges.
- (+) There is one WakeUp pin:
- WakeUp Pin 1 on PA.00.
-
- [..]
-
- *** Low Power modes configuration ***
- =====================================
- [..]
- The device features 3 low-power modes:
- (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
- NVIC, SysTick, etc. are kept running
- (+) Stop mode: All clocks are stopped
- (+) Standby mode: 1.8V domain powered off
-
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
- functions with
- (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-
- (+) Exit:
- (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
- (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
- (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
- (+++) Any EXTI Line (Internal or External) configured in Event mode
-
- *** Stop mode ***
- =================
- [..]
- The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
- clock gating. The voltage regulator can be configured either in normal or low-power mode.
- In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
- oscillators are disabled. SRAM and register contents are preserved.
- In Stop mode, all I/O pins keep the same state as in Run mode.
-
- (+) Entry:
- The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
- function with:
- (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
- (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
- (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
- (+) Exit:
- (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
- (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
-
- *** Standby mode ***
- ====================
- [..]
- The Standby mode allows to achieve the lowest power consumption. It is based on the
- Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
- consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
- switched off. SRAM and register contents are lost except for registers in the Backup domain
- and Standby circuitry
-
- (+) Entry:
- (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
- NRSTpin, IWDG Reset
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..]
-
- (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
- without depending on an external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
-
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
- configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
- *** PWR Workarounds linked to Silicon Limitation ***
- ====================================================
- [..]
- Below the list of all silicon limitations known on STM32F1xx prouct.
-
- (#)Workarounds Implemented inside PWR HAL Driver
- (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
- * information for the PVD.
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
- assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
- /* Set PLS[7:5] bits according to PVDLevel value */
- MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-
- /* Clear any previous config. Keep it clear if no event or IT mode is selected */
- __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
- __HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-
- /* Configure interrupt mode */
- if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_IT();
- }
-
- /* Configure event mode */
- if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
- }
-
- /* Configure the edge */
- if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
- }
-
- if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
- {
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
- }
-}
-
-/**
- * @brief Enables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_EnablePVD(void)
-{
- /* Enable the power voltage detector */
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the Power Voltage Detector(PVD).
- * @retval None
- */
-void HAL_PWR_DisablePVD(void)
-{
- /* Disable the power voltage detector */
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1
- * @retval None
- */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameter */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Enable the EWUPx pin */
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
- * This parameter can be one of the following values:
- * @arg PWR_WAKEUP_PIN1
- * @retval None
- */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
- /* Check the parameter */
- assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
- /* Disable the EWUPx pin */
- *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Enters Sleep mode.
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
- * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
- * When WFI entry is used, tick interrupt have to be disabled if not desired as
- * the interrupt wake up source.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
- /* Check the parameters */
- /* No check on Regulator because parameter not used in SLEEP mode */
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Regulator);
-
- assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- __WFE();
- __WFE();
- }
-}
-
-/**
- * @brief Enters Stop mode.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by using an interrupt or a wakeup event,
- * HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
- * This parameter can be one of the following values:
- * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
- * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
- * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
- * @retval None
- */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(Regulator));
- assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
- /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
- CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
-
- /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* Select Stop mode entry --------------------------------------------------*/
- if(STOPEntry == PWR_STOPENTRY_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __SEV();
- PWR_OverloadWfe(); /* WFE redefine locally */
- PWR_OverloadWfe(); /* WFE redefine locally */
- }
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Enters Standby mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - TAMPER pin if configured for tamper or calibration out.
- * - WKUP pin (PA0) if enabled.
- * @retval None
- */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
- /* Select Standby mode */
- SET_BIT(PWR->CR, PWR_CR_PDDS);
-
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
- /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
- __force_stores();
-#endif
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-
-/**
- * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
- * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * Setting this bit is useful when the processor is expected to run only on
- * interruptions handling.
- * @retval None
- */
-void HAL_PWR_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
- * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
- * re-enters SLEEP mode when an interruption handling is over.
- * @retval None
- */
-void HAL_PWR_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-
-/**
- * @brief Enables CORTEX M3 SEVONPEND bit.
- * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_EnableSEVOnPend(void)
-{
- /* Set SEVONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-/**
- * @brief Disables CORTEX M3 SEVONPEND bit.
- * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
- * WFE to wake up when an interrupt moves from inactive to pended.
- * @retval None
- */
-void HAL_PWR_DisableSEVOnPend(void)
-{
- /* Clear SEVONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-
-
-/**
- * @brief This function handles the PWR PVD interrupt request.
- * @note This API should be called under the PVD_IRQHandler().
- * @retval None
- */
-void HAL_PWR_PVD_IRQHandler(void)
-{
- /* Check PWR exti flag */
- if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
- {
- /* PWR PVD interrupt user callback */
- HAL_PWR_PVDCallback();
-
- /* Clear PWR Exti pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
- }
-}
-
-/**
- * @brief PWR PVD interrupt callback
- * @retval None
- */
-__weak void HAL_PWR_PVDCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_PVDCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_rcc.c b/lib/hal-stm32f1/source/stm32f1xx_hal_rcc.c deleted file mode 100644 index 570da59c..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_rcc.c +++ /dev/null @@ -1,1303 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Reset and Clock Control (RCC) peripheral:
- * + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- @verbatim
- ==============================================================================
- ##### RCC specific features #####
- ==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
- and all peripherals are off except internal SRAM, Flash and JTAG.
- (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
- all peripherals mapped on these buses are running at HSI speed.
- (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (+) All GPIOs are in input floating state, except the JTAG pins which
- are assigned to be used for debug purpose.
- [..] Once the device started from reset, the user application has to:
- (+) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB buses prescalers
- (+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals whose clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS)
-
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-
-#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
- * @{
- */
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-static void RCC_Delay(uint32_t mdelay);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..]
- This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
- and APB2).
-
- [..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
- (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
-
- (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
-
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
- (#) PLL (clocked by HSI or HSE), featuring different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
- (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
-
- (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clocks automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
- (Non-Maskable Interrupt) exception vector.
-
- (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
- HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
-
- [..] System, AHB and APB buses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these buses. You can use
- "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
- divided by 128.
- (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
- to work correctly. This clock is derived of the main PLL through PLL Multiplier.
- (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
- (+@) IWDG clock which is always the LSI clock.
-
- (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
- For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
- @endverbatim
- * @{
- */
-
-/*
- Additional consideration on the SYSCLK based on Latency settings:
- +-----------------------------------------------+
- | Latency | SYSCLK clock frequency (MHz) |
- |---------------|-------------------------------|
- |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- |---------------|-------------------------------|
- |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- |---------------|-------------------------------|
- |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- +-----------------------------------------------+
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE and PLL OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS and MCO1 OFF
- * - All interrupts disabled
- * @note This function does not modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
- */
-void HAL_RCC_DeInit(void)
-{
- /* Switch SYSCLK to HSI */
- CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-
- /* Reset HSEON, CSSON, & PLLON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Set HSITRIM bits to the reset value */
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
-
-#if defined(RCC_CFGR2_SUPPORT)
- /* Reset CFGR2 register */
- CLEAR_REG(RCC->CFGR2);
-
-#endif /* RCC_CFGR2_SUPPORT */
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
-}
-
-/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this macro. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- /* To have a fully stabilized clock in the specified range, a software delay of 1ms
- should be added.*/
- RCC_Delay(1);
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- FlagStatus pwrclkchanged = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Require to disable power clock if necessary */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
-#if defined(RCC_CR_PLL2ON)
- /*-------------------------------- PLL2 Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
- if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
- {
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
- assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLLI2S is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
-
- /* Configure the main PLL2 multiplication factors. */
- __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
-
- /* Enable the main PLL2. */
- __HAL_RCC_PLL2_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Set PREDIV1 source to HSE */
- CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
-
-#endif /* RCC_CR_PLL2ON */
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv factor --------------------------------*/
- /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
- if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
- {
- /* Check the parameter */
- assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
-#if defined(RCC_CFGR2_PREDIV1SRC)
- assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
-
- /* Set PREDIV1 source */
- SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
-#endif /* RCC_CFGR2_PREDIV1SRC */
-
- /* Set PREDIV1 Value */
- __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
- }
-
- /* Configure the main PLL clock source and multiplication factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLMUL);
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
- *
- * @note The HSI is used (enabled by hardware) as system clock source after
- * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after start-up delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
- * currently used as system clock source.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) of the device. */
-
-#if defined(FLASH_ACR_LATENCY)
- /* Increasing the number of wait states because of higher CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
-#endif /* FLASH_ACR_LATENCY */
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-#if defined(FLASH_ACR_LATENCY)
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-#endif /* FLASH_ACR_LATENCY */
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
- @verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
-
- @endverbatim
- * @{
- */
-
-/**
- * @brief Selects the clock source to output on MCO pin.
- * @note MCO pin should be configured in alternate function mode.
- * @param RCC_MCOx specifies the output direction for the clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
- * @param RCC_MCOSource specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- @if STM32F105xC
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
- @endif
- @if STM32F107xC
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
- @endif
- * @param RCC_MCODiv specifies the MCO DIV.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
- * @retval None
- */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
- GPIO_InitTypeDef gpio = {0U};
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO(RCC_MCOx));
- assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(RCC_MCOx);
- UNUSED(RCC_MCODiv);
-
- /* Configure the MCO1 pin in alternate function mode */
- gpio.Mode = GPIO_MODE_AF_PP;
- gpio.Speed = GPIO_SPEED_FREQ_HIGH;
- gpio.Pull = GPIO_NOPULL;
- gpio.Pin = MCO1_PIN;
-
- /* MCO1 Clock Enable */
- MCO1_CLK_ENABLE();
-
- HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-
- /* Configure the MCO clock source */
- __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
-}
-
-/**
- * @brief Enables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
- * @retval None
- */
-void HAL_RCC_EnableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
- * @brief Disables the Clock Security System.
- * @retval None
- */
-void HAL_RCC_DisableCSS(void)
-{
- *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Returns the SYSCLK frequency
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
- * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**)
- * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
- * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-#else
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
-#if defined(RCC_CFGR2_PREDIV1)
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-#else
- const uint8_t aPredivFactorTable[2] = {1, 2};
-#endif /*RCC_CFGR2_PREDIV1*/
-
-#endif
- uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
- uint32_t sysclockfreq = 0U;
-#if defined(RCC_CFGR2_PREDIV1SRC)
- uint32_t prediv2 = 0U, pll2mul = 0U;
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-
- tmpreg = RCC->CFGR;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (tmpreg & RCC_CFGR_SWS)
- {
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
- {
- sysclockfreq = HSE_VALUE;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
- {
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
- if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
-#if defined(RCC_CFGR2_PREDIV1)
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
-#else
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
-#endif /*RCC_CFGR2_PREDIV1*/
-#if defined(RCC_CFGR2_PREDIV1SRC)
-
- if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
- {
- /* PLL2 selected as Prediv1 source */
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
- pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
- }
- else
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
- }
-
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
- /* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
- {
- pllclk = pllclk / 2;
- }
-#else
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
-#endif /*RCC_CFGR2_PREDIV1SRC*/
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
- }
- sysclockfreq = pllclk;
- break;
- }
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- default: /* HSI used as system clock */
- {
- sysclockfreq = HSI_VALUE;
- break;
- }
- }
- return sysclockfreq;
-}
-
-/**
- * @brief Returns the HCLK frequency
- * @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated within this function
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- return SystemCoreClock;
-}
-
-/**
- * @brief Returns the PCLK1 frequency
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
-}
-
-/**
- * @brief Returns the PCLK2 frequency
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
-}
-
-/**
- * @brief Configures the RCC_OscInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
- * will be configured.
- * @retval None
- */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- /* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
-
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-#if defined(RCC_CFGR2_PREDIV1SRC)
- /* Get the Prediv1 source --------------------------------------------------*/
- RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
-#endif /* RCC_CFGR2_PREDIV1SRC */
-
- /* Get the HSE configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
- RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
-
- /* Get the HSI configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-
- /* Get the LSE configuration -----------------------------------------------*/
- if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
-
- /* Get the PLL configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
-#if defined(RCC_CR_PLL2ON)
- /* Get the PLL2 configuration -----------------------------------------------*/
- if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
- {
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
- }
- RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
- RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
-#endif /* RCC_CR_PLL2ON */
-}
-
-/**
- * @brief Get the RCC_ClkInitStruct according to the internal
- * RCC configuration registers.
- * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
- * contains the current clock configuration.
- * @param pFLatency Pointer on the Flash Latency.
- * @retval None
- */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
- /* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
- assert_param(pFLatency != NULL);
-
- /* Set all possible values for the Clock type parameter --------------------*/
- RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
- RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
-#if defined(FLASH_ACR_LATENCY)
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-#else
- /* For VALUE lines devices, only LATENCY_0 can be set*/
- *pFLatency = (uint32_t)FLASH_LATENCY_0;
-#endif
-}
-
-/**
- * @brief This function handles the RCC CSS interrupt request.
- * @note This API should be called under the NMI_Handler().
- * @retval None
- */
-void HAL_RCC_NMI_IRQHandler(void)
-{
- /* Check RCC CSSF flag */
- if(__HAL_RCC_GET_IT(RCC_IT_CSS))
- {
- /* RCC Clock Security System interrupt user callback */
- HAL_RCC_CSSCallback();
-
- /* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
- }
-}
-
-/**
- * @brief This function provides delay (in milliseconds) based on CPU cycles method.
- * @param mdelay: specifies the delay time length, in milliseconds.
- * @retval None
- */
-static void RCC_Delay(uint32_t mdelay)
-{
- __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
- do
- {
- __NOP();
- }
- while (Delay --);
-}
-
-/**
- * @brief RCC Clock Security System interrupt callback
- * @retval none
- */
-__weak void HAL_RCC_CSSCallback(void)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CSSCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_rcc_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_rcc_ex.c deleted file mode 100644 index 87fac880..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_rcc_ex.c +++ /dev/null @@ -1,881 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief Extended RCC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities RCC extension peripheral:
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx RCCEx
- * @brief RCC Extension HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
- * @{
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extended Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the RCC Clocks
- frequencies.
- [..]
- (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
- the backup registers) are set to their reset values.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
- * RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * contains the configuration information for the Extended Peripherals clocks(RTC clock).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
- * the backup registers) are set to their reset values.
- *
- * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
- * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
- * manually disable it.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t tickstart = 0U, temp_reg = 0U;
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t pllactive = 0U;
-#endif /* STM32F105xC || STM32F107xC */
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*------------------------------- RTC/LCD Configuration ------------------------*/
- if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
- {
- /* check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- FlagStatus pwrclkchanged = RESET;
-
- /* As soon as function is called to change RTC clock source, activation of the
- power domain is done. */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- {
- __HAL_RCC_PWR_CLK_ENABLE();
- pwrclkchanged = SET;
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
- temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
- if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of BDCR register */
- RCC->BDCR = temp_reg;
-
- /* Wait for LSERDY if LSE was enabled */
- if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
- {
- /* Get Start Tick */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-
- /* Require to disable power clock if necessary */
- if(pwrclkchanged == SET)
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- }
- }
-
- /*------------------------------ ADC clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- {
- /* Check the parameters */
- assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
-
- /* Configure the ADC clock source */
- __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
- }
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ I2S2 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
-
- /* Configure the I2S2 clock source */
- __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
- }
-
- /*------------------------------ I2S3 Configuration ------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
-
- /* Configure the I2S3 clock source */
- __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
- }
-
- /*------------------------------ PLL I2S Configuration ----------------------*/
- /* Check that PLLI2S need to be enabled */
- if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Update flag to indicate that PLL I2S should be active */
- pllactive = 1;
- }
-
- /* Check if PLL I2S need to be enabled */
- if (pllactive == 1)
- {
- /* Enable PLL I2S only if not active */
- if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
- assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLL2 is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
-
- /* Configure the main PLLI2S multiplication factors. */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
-
- /* Enable the main PLLI2S. */
- __HAL_RCC_PLLI2S_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
- if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
- {
- return HAL_ERROR;
- }
- }
- }
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- /*------------------------------ USB clock Configuration ------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
- {
- /* Check the parameters */
- assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
-
- /* Configure the USB clock source */
- __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
- }
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the PeriphClkInit according to the internal
- * RCC configuration registers.
- * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
- * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
- * @retval None
- */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- uint32_t srcclk = 0U;
-
- /* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
-
- /* Get the RTC configuration -----------------------------------------------*/
- srcclk = __HAL_RCC_GET_RTC_SOURCE();
- /* Source clock is LSE or LSI*/
- PeriphClkInit->RTCClockSelection = srcclk;
-
- /* Get the ADC clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
- PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* Get the I2S2 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
- PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
-
- /* Get the I2S3 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
- PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* Get the I2S2 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
- PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
-
- /* Get the I2S3 clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
- PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- /* Get the USB clock configuration -----------------------------------------*/
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
- PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-}
-
-/**
- * @brief Returns the peripheral clock frequency
- * @note Returns 0 if peripheral clock is unknown
- * @param PeriphClk Peripheral clock identifier
- * This parameter can be one of the following values:
- * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
- @if STM32F103xE
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- @endif
- @if STM32F103xG
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- @endif
- @if STM32F105xC
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F107xC
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F102xx
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- @if STM32F103xx
- * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- @endif
- * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
- */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-#if defined(STM32F105xC) || defined(STM32F107xC)
- const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
-
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
- uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
-#endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
- defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
- const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
- const uint8_t aPredivFactorTable[2] = {1, 2};
-
- uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
- uint32_t temp_reg = 0U, frequency = 0U;
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
- switch (PeriphClk)
- {
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- case RCC_PERIPHCLK_USB:
- {
- /* Get RCC configuration ------------------------------------------------------*/
- temp_reg = RCC->CFGR;
-
- /* Check if PLL is enabled */
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
- {
- pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
-#else
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
- {
- /* PLL2 selected as Prediv1 source */
- /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
- pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
- }
- else
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
- }
-
- /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
- /* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
- {
- pllclk = pllclk / 2;
- }
-#else
- if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
- pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
- }
-#endif /* STM32F105xC || STM32F107xC */
- }
- else
- {
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
- }
-
- /* Calcul of the USB frequency*/
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
- {
- /* Prescaler of 2 selected for USB */
- frequency = pllclk;
- }
- else
- {
- /* Prescaler of 3 selected for USB */
- frequency = (2 * pllclk) / 3;
- }
-#else
- /* USBCLK = PLLCLK / USB prescaler */
- if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
- {
- /* No prescaler selected for USB */
- frequency = pllclk;
- }
- else
- {
- /* Prescaler of 1.5 selected for USB */
- frequency = (pllclk * 2) / 3;
- }
-#endif
- }
- break;
- }
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
- case RCC_PERIPHCLK_I2S2:
- {
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* SYSCLK used as source clock for I2S2 */
- frequency = HAL_RCC_GetSysClockFreq();
-#else
- if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
- {
- /* SYSCLK used as source clock for I2S2 */
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else
- {
- /* Check if PLLI2S is enabled */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
- {
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
- }
- }
-#endif /* STM32F103xE || STM32F103xG */
- break;
- }
- case RCC_PERIPHCLK_I2S3:
- {
-#if defined(STM32F103xE) || defined(STM32F103xG)
- /* SYSCLK used as source clock for I2S3 */
- frequency = HAL_RCC_GetSysClockFreq();
-#else
- if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
- {
- /* SYSCLK used as source clock for I2S3 */
- frequency = HAL_RCC_GetSysClockFreq();
- }
- else
- {
- /* Check if PLLI2S is enabled */
- if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
- {
- /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
- frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
- }
- }
-#endif /* STM32F103xE || STM32F103xG */
- break;
- }
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
- case RCC_PERIPHCLK_RTC:
- {
- /* Get RCC BDCR configuration ------------------------------------------------------*/
- temp_reg = RCC->BDCR;
-
- /* Check if LSE is ready if RTC clock selection is LSE */
- if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
- {
- frequency = LSE_VALUE;
- }
- /* Check if LSI is ready if RTC clock selection is LSI */
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
- {
- frequency = LSI_VALUE;
- }
- else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
- {
- frequency = HSE_VALUE / 128U;
- }
- /* Clock not enabled for RTC*/
- else
- {
- frequency = 0U;
- }
- break;
- }
- case RCC_PERIPHCLK_ADC:
- {
- frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
- break;
- }
- default:
- {
- break;
- }
- }
- return(frequency);
-}
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
- * @brief PLLI2S Management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended PLLI2S Management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PLLI2S
- activation or deactivation
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable PLLI2S
- * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
- * contains the configuration information for the PLLI2S
- * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
-{
- uint32_t tickstart = 0U;
-
- /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
- assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLL2 is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLLI2S. */
- __HAL_RCC_PLLI2S_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
-
-
- /* Configure the main PLLI2S multiplication factors. */
- __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
-
- /* Enable the main PLLI2S. */
- __HAL_RCC_PLLI2S_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable PLLI2S
- * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
-{
- uint32_t tickstart = 0U;
-
- /* Disable PLL I2S as not requested by I2S2 or I2S3*/
- if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
- {
- /* Disable the main PLLI2S. */
- __HAL_RCC_PLLI2S_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
- * @brief PLL2 Management functions
- *
-@verbatim
- ===============================================================================
- ##### Extended PLL2 Management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PLL2
- activation or deactivation
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enable PLL2
- * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
- * contains the configuration information for the PLL2
- * @note The PLL2 configuration not modified if used indirectly as system clock.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
-{
- uint32_t tickstart = 0U;
-
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
- assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
-
- /* Prediv2 can be written only when the PLLI2S is disabled. */
- /* Return an error only if new value is different from the programmed value */
- if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
- (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
- {
- return HAL_ERROR;
- }
-
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the HSE prediv2 factor --------------------------------*/
- __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
-
- /* Configure the main PLL2 multiplication factors. */
- __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
-
- /* Enable the main PLL2. */
- __HAL_RCC_PLL2_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disable PLL2
- * @note PLL2 is not disabled if used indirectly as system clock.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
-{
- uint32_t tickstart = 0U;
-
- /* This bit can not be cleared if the PLL2 clock is used indirectly as system
- clock (i.e. it is used as PLL clock entry that is used as system clock). */
- if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
- (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
- ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
- {
- return HAL_ERROR;
- }
- else
- {
- /* Disable the main PLL2. */
- __HAL_RCC_PLL2_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL2 is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_rtc.c b/lib/hal-stm32f1/source/stm32f1xx_hal_rtc.c deleted file mode 100644 index 511632bf..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_rtc.c +++ /dev/null @@ -1,1720 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_rtc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) peripheral:
- * + Initialization and de-initialization functions
- * + RTC Time and Date functions
- * + RTC Alarm functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above).
- (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base)
- using the HAL_RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
- (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and configure the Tamper Level using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
- mode using HAL_RTCEx_SetTamper_IT() function.
- (+) The TAMPER1 alternate function can be mapped to PC13
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
- function.
-
- ##### WARNING: Drivers Restrictions #####
- ==================================================================
- [..] RTC version used on STM32F1 families is version V1. All the features supported by V2
- (other families) will be not supported on F1.
- [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely
- managed by SW.
- [..] Then, there are some restrictions compared to other families:
- (+) Only format 24 hours supported in HAL (format 12 hours not supported)
- (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost.
- User should implement a way to save date before entering in low power mode (an
- example is provided with firmware package based on backup registers)
- (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called.
- (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need
- to program a new alarm)
-
- ##### Backup Domain Operating Condition #####
- ==============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC operating even when the main digital supply (VDD) is turned
- off, the VBAT pin powers the following blocks:
- (+) The RTC
- (+) The LSE oscillator
- (+) PC13 I/O
-
- [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following pins are available:
- (+) PC13 can be used as a Tamper pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following pins are available:
- (+) PC13 can be used as the Tamper pin
-
- ##### Backup Domain Reset #####
- ==================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
- to their reset values.
- [..] A backup domain reset is generated when one of the following events occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
- (#) Tamper detection event resets all data backup registers.
-
- ##### Backup Domain Access #####
- ==================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for
- PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE)
- (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE()
-
- ##### RTC and low power modes #####
- ==================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A),
- and RTC tamper event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup RTC RTC
- * @brief RTC HAL module driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
- * @{
- */
-#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
-#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
- * @{
- */
-static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
-static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
-static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc);
-static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter);
-static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc);
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-static uint8_t RTC_IsLeapYear(uint16_t nYear);
-static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed);
-static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay);
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to initialize and configure the
- RTC Prescaler (Asynchronous), disable RTC registers Write protection,
- enter and exit the RTC initialization mode,
- RTC registers synchronization check and reference clock detection enable.
- (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by setting the CNF bit in the RTC_CRL register.
- (#) To read the calendar after wakeup from low power modes (Standby or Stop)
- the software must first wait for the RSF bit (Register Synchronized Flag)
- in the RTC_CRL register to be set by hardware.
- The HAL_RTC_WaitForSynchro() function implements the above software
- sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the RTC peripheral
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
- uint32_t prescaler = 0U;
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
- assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut));
- assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-
- if(hrtc->State == HAL_RTC_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hrtc->Lock = HAL_UNLOCKED;
-
- /* Initialize RTC MSP */
- HAL_RTC_MspInit(hrtc);
- }
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Waiting for synchro */
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear Flags Bits */
- CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));
-
- if(hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
- {
- /* Disable the selected Tamper pin */
- CLEAR_BIT(BKP->CR, BKP_CR_TPE);
- }
-
- /* Set the signal which will be routed to RTC Tamper pin*/
- MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
-
- if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND)
- {
- /* RTC Prescaler provided directly by end-user*/
- prescaler = hrtc->Init.AsynchPrediv;
- }
- else
- {
- /* RTC Prescaler will be automatically calculated to get 1 second timebase */
- /* Get the RTCCLK frequency */
- prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
-
- /* Check that RTC clock is enabled*/
- if (prescaler == 0U)
- {
- /* Should not happen. Frequency is not available*/
- hrtc->State = HAL_RTC_STATE_ERROR;
- return HAL_ERROR;
- }
- else
- {
- /* RTC period = RTCCLK/(RTC_PR + 1) */
- prescaler = prescaler - 1U;
- }
- }
-
- /* Configure the RTC_PRLH / RTC_PRLL */
- MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U));
- MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL));
-
- /* Wait for synchro */
- if(RTC_ExitInitMode(hrtc) != HAL_OK)
- {
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
- /* Initialize date to 1st of January 2000 */
- hrtc->DateToUpdate.Year = 0x00U;
- hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
- hrtc->DateToUpdate.Date = 0x01U;
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief DeInitializes the RTC peripheral
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @note This function does not reset the RTC Backup Data registers.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Release Lock */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- CLEAR_REG(hrtc->Instance->CNTL);
- CLEAR_REG(hrtc->Instance->CNTH);
- WRITE_REG(hrtc->Instance->PRLL, 0x00008000U);
- CLEAR_REG(hrtc->Instance->PRLH);
-
- /* Reset All CRH/CRL bits */
- CLEAR_REG(hrtc->Instance->CRH);
- CLEAR_REG(hrtc->Instance->CRL);
-
- if(RTC_ExitInitMode(hrtc) != HAL_OK)
- {
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Wait for synchro*/
- HAL_RTC_WaitForSynchro(hrtc);
-
- /* Clear RSF flag */
- CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
-
- /* De-Initialize RTC MSP */
- HAL_RTC_MspDeInit(hrtc);
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the RTC MSP.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes the RTC MSP.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions
- * @brief RTC Time and Date functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Time and Date functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets RTC current time.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t counter_time = 0U, counter_alarm = 0U;
-
- /* Check input parameters */
- if((hrtc == NULL) || (sTime == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_HOUR24(sTime->Hours));
- assert_param(IS_RTC_MINUTES(sTime->Minutes));
- assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
- counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \
- ((uint32_t)sTime->Minutes * 60U) + \
- ((uint32_t)sTime->Seconds));
- }
- else
- {
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-
- counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \
- ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \
- ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds))));
- }
-
- /* Write time counter in RTC registers */
- if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear Second and overflow flags */
- CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
-
- /* Read current Alarm counter in RTC registers */
- counter_alarm = RTC_ReadAlarmCounter(hrtc);
-
- /* Set again alarm to match with new time if enabled */
- if (counter_alarm != RTC_ALARM_RESETVALUE)
- {
- if(counter_alarm < counter_time)
- {
- /* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24U * 3600U);
-
- /* Write new Alarm counter in RTC registers */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- }
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Gets RTC current time.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
- uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U;
-
- /* Check input parameters */
- if((hrtc == NULL) || (sTime == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Check if counter overflow occurred */
- if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW))
- {
- return HAL_ERROR;
- }
-
- /* Read the time counter*/
- counter_time = RTC_ReadTimeCounter(hrtc);
-
- /* Fill the structure fields with the read parameters */
- hours = counter_time / 3600U;
- sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U);
- sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U);
-
- if (hours >= 24U)
- {
- /* Get number of days elapsed from last calculation */
- days_elapsed = (hours / 24U);
-
- /* Set Hours in RTC_TimeTypeDef structure*/
- sTime->Hours = (hours % 24U);
-
- /* Read Alarm counter in RTC registers */
- counter_alarm = RTC_ReadAlarmCounter(hrtc);
-
- /* Calculate remaining time to reach alarm (only if set and not yet expired)*/
- if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time))
- {
- counter_alarm -= counter_time;
- }
- else
- {
- /* In case of counter_alarm < counter_time */
- /* Alarm expiration already occurred but alarm not deactivated */
- counter_alarm = RTC_ALARM_RESETVALUE;
- }
-
- /* Set updated time in decreasing counter by number of days elapsed */
- counter_time -= (days_elapsed * 24U * 3600U);
-
- /* Write time counter in RTC registers */
- if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Set updated alarm to be set */
- if (counter_alarm != RTC_ALARM_RESETVALUE)
- {
- counter_alarm += counter_time;
-
- /* Write time counter in RTC registers */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
-
- /* Update date */
- RTC_DateUpdate(hrtc, days_elapsed);
- }
- else
- {
- sTime->Hours = hours;
- }
-
- /* Check the input parameters format */
- if(Format != RTC_FORMAT_BIN)
- {
- /* Convert the time structure parameters to BCD format */
- sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours);
- sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes);
- sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds);
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Sets RTC current date.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sDate: Pointer to date structure
- * @param Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U;
-
- /* Check input parameters */
- if((hrtc == NULL) || (sDate == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_YEAR(sDate->Year));
- assert_param(IS_RTC_MONTH(sDate->Month));
- assert_param(IS_RTC_DATE(sDate->Date));
-
- /* Change the current date */
- hrtc->DateToUpdate.Year = sDate->Year;
- hrtc->DateToUpdate.Month = sDate->Month;
- hrtc->DateToUpdate.Date = sDate->Date;
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
- assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
-
- /* Change the current date */
- hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year);
- hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month);
- hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date);
- }
-
- /* WeekDay set by user can be ignored because automatically calculated */
- hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date);
- sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
-
- /* Reset time to be aligned on the same day */
- /* Read the time counter*/
- counter_time = RTC_ReadTimeCounter(hrtc);
-
- /* Fill the structure fields with the read parameters */
- hours = counter_time / 3600U;
- if (hours > 24U)
- {
- /* Set updated time in decreasing counter by number of days elapsed */
- counter_time -= ((hours / 24U) * 24U * 3600U);
- /* Write time counter in RTC registers */
- if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
-
- /* Read current Alarm counter in RTC registers */
- counter_alarm = RTC_ReadAlarmCounter(hrtc);
-
- /* Set again alarm to match with new time if enabled */
- if (counter_alarm != RTC_ALARM_RESETVALUE)
- {
- if(counter_alarm < counter_time)
- {
- /* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24U * 3600U);
-
- /* Write new Alarm counter in RTC registers */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- }
-
-
- }
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets RTC current date.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sDate: Pointer to Date structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
- RTC_TimeTypeDef stime = {0U};
-
- /* Check input parameters */
- if((hrtc == NULL) || (sDate == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
-
- /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
- if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Fill the structure fields with the read parameters */
- sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
- sDate->Year = hrtc->DateToUpdate.Year;
- sDate->Month = hrtc->DateToUpdate.Month;
- sDate->Date = hrtc->DateToUpdate.Date;
-
- /* Check the input parameters format */
- if(Format != RTC_FORMAT_BIN)
- {
- /* Convert the date structure parameters to BCD format */
- sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year);
- sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month);
- sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date);
- }
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group3 Alarm functions
- * @brief RTC Alarm functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified RTC Alarm.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t counter_alarm = 0U, counter_time;
- RTC_TimeTypeDef stime = {0U};
-
- /* Check input parameters */
- if((hrtc == NULL) || (sAlarm == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
- if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Convert time in seconds */
- counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
- ((uint32_t)stime.Minutes * 60U) + \
- ((uint32_t)stime.Seconds));
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
- ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
- ((uint32_t)sAlarm->AlarmTime.Seconds));
- }
- else
- {
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
- ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
- ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
- }
-
- /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
- if (counter_alarm < counter_time)
- {
- /* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24U * 3600U);
- }
-
- /* Write Alarm counter in RTC registers */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t counter_alarm = 0U, counter_time;
- RTC_TimeTypeDef stime = {0U};
-
- /* Check input parameters */
- if((hrtc == NULL) || (sAlarm == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
- if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Convert time in seconds */
- counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
- ((uint32_t)stime.Minutes * 60U) + \
- ((uint32_t)stime.Seconds));
-
- if(Format == RTC_FORMAT_BIN)
- {
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
- ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
- ((uint32_t)sAlarm->AlarmTime.Seconds));
- }
- else
- {
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
- ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
- ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
- }
-
- /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
- if (counter_alarm < counter_time)
- {
- /* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24U * 3600U);
- }
-
- /* Write alarm counter in RTC registers */
- if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
- }
-}
-
-/**
- * @brief Gets the RTC Alarm value and masks.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: Alarm
- * @param Format: Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
- uint32_t counter_alarm = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Alarm);
-
- /* Check input parameters */
- if((hrtc == NULL) || (sAlarm == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Read Alarm counter in RTC registers */
- counter_alarm = RTC_ReadAlarmCounter(hrtc);
-
- /* Fill the structure with the read parameters */
- /* Set hours in a day range (between 0 to 24)*/
- sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U);
- sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U);
- sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U);
-
- if(Format != RTC_FORMAT_BIN)
- {
- sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours);
- sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes);
- sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactive the specified RTC Alarm
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param Alarm: Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Alarm);
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Set to default values ALRH & ALRL registers */
- WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER);
- WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER);
-
- /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */
- __HAL_RTC_ALARM_EXTI_DISABLE_IT();
-
- /* Wait for synchro */
- if(RTC_ExitInitMode(hrtc) != HAL_OK)
- {
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles Alarm interrupt request.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA))
- {
- /* Get the status of the Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
- {
- /* AlarmA callback */
- HAL_RTC_AlarmAEventCallback(hrtc);
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
- }
- }
-
- /* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Alarm A callback.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_AlarmAEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief This function handles AlarmA Polling request.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Get RTC state
-
-@endverbatim
- * @{
- */
-/**
- * @brief Returns the RTC state.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL state
- */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
- return hrtc->State;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
- * are synchronized with RTC APB clock.
- * @note This function must be called before any read operation after an APB reset
- * or an APB clock stop.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Clear RSF flag */
- CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
-
- tickstart = HAL_GetTick();
-
- /* Wait the registers to be synchronised */
- while((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Private_Functions
- * @{
- */
-
-
-/**
- * @brief Read the time counter available in RTC_CNT registers.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval Time counter
- */
-static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
-{
- uint16_t high1 = 0U, high2 = 0U, low = 0U;
- uint32_t timecounter = 0U;
-
- high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
- low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
- high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
-
- if (high1 != high2)
- { /* In this case the counter roll over during reading of CNTL and CNTH registers,
- read again CNTL register then return the counter value */
- timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
- }
- else
- { /* No counter roll over during reading of CNTL and CNTH registers, counter
- value is equal to first value of CNTL and CNTH */
- timecounter = (((uint32_t) high1 << 16U) | low);
- }
-
- return timecounter;
-}
-
-/**
- * @brief Write the time counter in RTC_CNT registers.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param TimeCounter: Counter to write in RTC_CNT registers
- * @retval HAL status
- */
-static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Set RTC COUNTER MSB word */
- WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U));
- /* Set RTC COUNTER LSB word */
- WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
-
- /* Wait for synchro */
- if(RTC_ExitInitMode(hrtc) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Read the time counter available in RTC_ALR registers.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval Time counter
- */
-static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc)
-{
- uint16_t high1 = 0U, low = 0U;
-
- high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
- low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
-
- return (((uint32_t) high1 << 16U) | low);
-}
-
-/**
- * @brief Write the time counter in RTC_ALR registers.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param AlarmCounter: Counter to write in RTC_ALR registers
- * @retval HAL status
- */
-static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- else
- {
- /* Set RTC COUNTER MSB word */
- WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U));
- /* Set RTC COUNTER LSB word */
- WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
-
- /* Wait for synchro */
- if(RTC_ExitInitMode(hrtc) != HAL_OK)
- {
- status = HAL_ERROR;
- }
- }
-
- return status;
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0U;
-
- tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-
- return HAL_OK;
-}
-
-/**
- * @brief Exit the RTC Initialization mode.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
- {
- if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint32_t bcdhigh = 0U;
-
- while(Value >= 10U)
- {
- bcdhigh++;
- Value -= 10U;
- }
-
- return ((uint8_t)(bcdhigh << 4U) | Value);
-}
-
-/**
- * @brief Converts from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint32_t tmp = 0U;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @brief Updates date when time is 23:59:59.
- * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param DayElapsed: Number of days elapsed from last date update
- * @retval None
- */
-static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed)
-{
- uint32_t year = 0U, month = 0U, day = 0U;
- uint32_t loop = 0U;
-
- /* Get the current year*/
- year = hrtc->DateToUpdate.Year;
-
- /* Get the current month and day */
- month = hrtc->DateToUpdate.Month;
- day = hrtc->DateToUpdate.Date;
-
- for (loop = 0U; loop < DayElapsed; loop++)
- {
- if((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \
- (month == 8U) || (month == 10U) || (month == 12U))
- {
- if(day < 31U)
- {
- day++;
- }
- /* Date structure member: day = 31 */
- else
- {
- if(month != 12U)
- {
- month++;
- day = 1U;
- }
- /* Date structure member: day = 31 & month =12 */
- else
- {
- month = 1U;
- day = 1U;
- year++;
- }
- }
- }
- else if((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U))
- {
- if(day < 30U)
- {
- day++;
- }
- /* Date structure member: day = 30 */
- else
- {
- month++;
- day = 1U;
- }
- }
- else if(month == 2U)
- {
- if(day < 28U)
- {
- day++;
- }
- else if(day == 28U)
- {
- /* Leap year */
- if(RTC_IsLeapYear(year))
- {
- day++;
- }
- else
- {
- month++;
- day = 1U;
- }
- }
- else if(day == 29U)
- {
- month++;
- day = 1U;
- }
- }
- }
-
- /* Update year */
- hrtc->DateToUpdate.Year = year;
-
- /* Update day and month */
- hrtc->DateToUpdate.Month = month;
- hrtc->DateToUpdate.Date = day;
-
- /* Update day of the week */
- hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day);
-}
-
-/**
- * @brief Check whether the passed year is Leap or not.
- * @param nYear year to check
- * @retval 1: leap year
- * 0: not leap year
- */
-static uint8_t RTC_IsLeapYear(uint16_t nYear)
-{
- if((nYear % 4U) != 0U)
- {
- return 0U;
- }
-
- if((nYear % 100U) != 0U)
- {
- return 1U;
- }
-
- if((nYear % 400U) == 0U)
- {
- return 1U;
- }
- else
- {
- return 0U;
- }
-}
-
-/**
- * @brief Determines the week number, the day number and the week day number.
- * @param nYear year to check
- * @param nMonth Month to check
- * @param nDay Day to check
- * @note Day is calculated with hypothesis that year > 2000
- * @retval Value which can take one of the following parameters:
- * @arg RTC_WEEKDAY_MONDAY
- * @arg RTC_WEEKDAY_TUESDAY
- * @arg RTC_WEEKDAY_WEDNESDAY
- * @arg RTC_WEEKDAY_THURSDAY
- * @arg RTC_WEEKDAY_FRIDAY
- * @arg RTC_WEEKDAY_SATURDAY
- * @arg RTC_WEEKDAY_SUNDAY
- */
-static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
-{
- uint32_t year = 0U, weekday = 0U;
-
- year = 2000U + nYear;
-
- if(nMonth < 3U)
- {
- /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
- weekday = (((23U * nMonth)/9U) + nDay + 4U + year + ((year-1U)/4U) - ((year-1U)/100U) + ((year-1U)/400U)) % 7U;
- }
- else
- {
- /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
- weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U;
- }
-
- return (uint8_t)weekday;
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_rtc_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_rtc_ex.c deleted file mode 100644 index 541f71d1..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_rtc_ex.c +++ /dev/null @@ -1,593 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_rtc_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief Extended RTC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extension peripheral:
- * + RTC Tamper functions
- * + Extension Control functions
- * + Extension RTC features functions
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/** @defgroup RTCEx RTCEx
- * @brief RTC Extended HAL module driver
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
- * @{
- */
-
-/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions
- * @brief RTC Tamper functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Tamper functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Tamper feature
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets Tamper
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sTamper: Pointer to Tamper Structure.
- * @note Tamper can be enabled only if ASOE and CCO bit are reset
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- /* Check input parameters */
- if((hrtc == NULL) || (sTamper == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
- {
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
-
- MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Sets Tamper with interrupt.
- * @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param sTamper: Pointer to RTC Tamper.
- * @note Tamper can be enabled only if ASOE and CCO bit are reset
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
- /* Check input parameters */
- if((hrtc == NULL) || (sTamper == NULL))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
- {
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
-
- MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
-
- /* Configure the Tamper Interrupt in the BKP->CSR */
- __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivates Tamper.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param Tamper: Selected tamper pin.
- * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Tamper);
-
- assert_param(IS_RTC_TAMPER(Tamper));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the selected Tamper pin */
- CLEAR_BIT(BKP->CR, BKP_CR_TPE);
-
- /* Disable the Tamper Interrupt in the BKP->CSR */
- /* Configure the Tamper Interrupt in the BKP->CSR */
- __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1);
-
- /* Clear the Tamper interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
- SET_BIT(BKP->CSR, BKP_CSR_CTE);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles Tamper interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1))
- {
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
- {
- /* Tamper callback */
- HAL_RTCEx_Tamper1EventCallback(hrtc);
-
- /* Clear the Tamper interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
- }
- }
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Tamper 1 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief This function handles Tamper1 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions
- * @brief RTC Second functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Second functions #####
- ===============================================================================
-
- [..] This section provides functions implementing second interupt handlers
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets Interrupt for second
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc)
-{
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Enable Second interuption */
- __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivates Second.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc)
-{
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Deactivate Second interuption*/
- __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles second interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc)
-{
- if(__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC))
- {
- /* Get the status of the Interrupt */
- if(__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC))
- {
- /* Check if Overrun occurred */
- if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW))
- {
- /* Second error callback */
- HAL_RTCEx_RTCEventErrorCallback(hrtc);
-
- /* Clear flag Second */
- __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
- }
- else
- {
- /* Second callback */
- HAL_RTCEx_RTCEventCallback(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
- }
-
- /* Clear flag Second */
- __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC);
- }
- }
-}
-
-/**
- * @brief Second event callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTCEx_RTCEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Second event error callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval None
- */
-__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Extension Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Writes a data in a specified RTC Backup data register
- (+) Read a data in a specified RTC Backup data register
- (+) Sets the Smooth calibration parameters.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
- * specify the register (depending devices).
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
- uint32_t tmp = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- tmp = (uint32_t)BKP_BASE;
- tmp += (BackupRegister * 4U);
-
- *(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
- * specify the register (depending devices).
- * @retval Read value
- */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
- uint32_t backupregister = 0U;
- uint32_t pvalue = 0U;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(BackupRegister));
-
- backupregister = (uint32_t)BKP_BASE;
- backupregister += (BackupRegister * 4U);
-
- pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
-
- /* Read the specified register */
- return pvalue;
-}
-
-
-/**
- * @brief Sets the Smooth calibration parameters.
- * @param hrtc: RTC handle
- * @param SmoothCalibPeriod: Not used (only present for compatibility with another families)
- * @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families)
- * @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value.
- * This parameter must be a number between 0 and 0x7F.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
-{
- /* Check input parameters */
- if(hrtc == NULL)
- {
- return HAL_ERROR;
- }
- /* Prevent unused argument(s) compilation warning */
- UNUSED(SmoothCalibPeriod);
- UNUSED(SmoothCalibPlusPulses);
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Sets RTC Clock Calibration value.*/
- MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_sd.c b/lib/hal-stm32f1/source/stm32f1xx_hal_sd.c deleted file mode 100644 index 1e55c153..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_sd.c +++ /dev/null @@ -1,2924 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_sd.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SD card HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Secure Digital (SD) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + SD card Control functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
- the user in HAL_SD_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
- examples.
- You can easily tailor this configuration according to hardware resources.
-
- [..]
- This driver is a generic layered driver for SDIO memories which uses the HAL
- SDIO driver functions to interface with SD and uSD cards devices.
- It is used as follows:
-
- (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
- (##) SDIO pins configuration for SD card
- (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
- and according to your pin assignment;
- (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
- and HAL_SD_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
- (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
- (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDIO and DMA interrupt priorities using functions
- HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
- (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
- and __HAL_SD_DISABLE_IT() inside the communication process.
- (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
- and __HAL_SD_CLEAR_IT()
- (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
- and HAL_SD_WriteBlocks_IT() APIs).
- (+++) Configure the SDIO interrupt priorities using function
- HAL_NVIC_SetPriority();
- (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
- and __HAL_SD_DISABLE_IT() inside the communication process.
- (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
- and __HAL_SD_CLEAR_IT()
- (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
-
- *** SD Card Initialization and configuration ***
- ================================================
- [..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
- This function provide the following operations:
-
- (#) Initialize the SDIO peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
- The SD Card frequency (SDIO_CK) is computed as follows:
-
- SDIO_CK = SDIOCLK / (ClockDiv + 2)
-
- In initialization mode and according to the SD Card standard,
- make sure that the SDIO_CK frequency doesn't exceed 400KHz.
-
- This phase of initialization is done through SDIO_Init() and
- SDIO_PowerState_ON() SDIO low level APIs.
-
- (#) Initialize the SD card. The API used is HAL_SD_InitCard().
- This phase allows the card initialization and identification
- and check the SD Card type (Standard Capacity or High Capacity)
- The initialization flow is compatible with SD standard.
-
- This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
- of plug-off plug-in.
-
- (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
- frequency is set to 24MHz. You can change or adapt this frequency by adjusting
- the "ClockDiv" field.
- In transfer mode and according to the SD Card standard, make sure that the
- SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDIO
- peripheral in bypass mode. Refer to the corresponding reference manual
- for more details.
-
- (#) Select the corresponding SD Card according to the address read with the step 2.
-
- (#) Configure the SD Card in wide bus mode: 4-bits data.
-
- *** SD Card Read operation ***
- ==============================
- [..]
- (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
-
- (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
- You could also check the DMA transfer process through the SD Rx interrupt event.
-
- (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
- You could also check the IT transfer process through the SD Rx interrupt event.
-
- *** SD Card Write operation ***
- ===============================
- [..]
- (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
-
- (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
- You could also check the DMA transfer process through the SD Tx interrupt event.
-
- (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
- by adjusting the "NumberOfBlocks" parameter.
- After this, you have to ensure that the transfer is done correctly. The check is done
- through HAL_SD_GetCardState() function for SD card state.
- You could also check the IT transfer process through the SD Tx interrupt event.
-
- *** SD card status ***
- ======================
- [..]
- (+) The SD Status contains status bits that are related to the SD Memory
- Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
-
- *** SD card information ***
- ===========================
- [..]
- (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
- It returns useful information about the SD card such as block size, card type,
- block number ...
-
- *** SD card CSD register ***
- ============================
- [..]
- (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
- Some of the CSD parameters are useful for card initialization and identification.
-
- *** SD card CID register ***
- ============================
- [..]
- (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
- Some of the CSD parameters are useful for card initialization and identification.
-
- *** SD HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in SD HAL driver.
-
- (+) __HAL_SD_ENABLE : Enable the SD device
- (+) __HAL_SD_DISABLE : Disable the SD device
- (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
- (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
- (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
- (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
- (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
- (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
-
- [..]
- (@) You can refer to the SD HAL driver header file for more useful macros
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SD
- * @{
- */
-#ifdef HAL_SD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SD_Private_Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
- * @{
- */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMAError(DMA_HandleTypeDef *hdma);
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
- * @{
- */
-
-/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to initialize/de-initialize the SD
- card device to be ready for use.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SD according to the specified parameters in the
- SD_HandleTypeDef and create the associated handle.
- * @param hsd: Pointer to the SD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
-{
- /* Check the SD handle allocation */
- if(hsd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
- assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
- assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
-
- if(hsd->State == HAL_SD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsd->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_SD_MspInit(hsd);
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize the Card parameters */
- HAL_SD_InitCard(hsd);
-
- /* Initialize the error code */
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- /* Initialize the SD operation */
- hsd->Context = SD_CONTEXT_NONE;
-
- /* Initialize the SD state */
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the SD Card.
- * @param hsd: Pointer to SD handle
- * @note This function initializes the SD card. It could be used when a card
- re-initialization is needed.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- SD_InitTypeDef Init;
-
- /* Default SDIO peripheral configuration for SD card initialization */
- Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- Init.BusWide = SDIO_BUS_WIDE_1B;
- Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDIO_INIT_CLK_DIV;
-
- /* Initialize SDIO peripheral interface with default configuration */
- SDIO_Init(hsd->Instance, Init);
-
- /* Disable SDIO Clock */
- __HAL_SD_DISABLE(hsd);
-
- /* Set Power State to ON */
- SDIO_PowerState_ON(hsd->Instance);
-
- /* Enable SDIO Clock */
- __HAL_SD_ENABLE(hsd);
-
- /* Required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(2U);
-
- /* Identify card operating voltage */
- errorstate = SD_PowerON(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- /* Card initialization */
- errorstate = SD_InitCard(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-Initializes the SD card.
- * @param hsd: Pointer to SD handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
- /* Check the SD handle allocation */
- if(hsd == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Set SD power state to off */
- SD_PowerOFF(hsd);
-
- /* De-Initialize the MSP layer */
- HAL_SD_MspDeInit(hsd);
-
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_RESET;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initializes the SD MSP.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize SD MSP.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the data
- transfer from/to SD card.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of SD blocks to read
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Poll on SDIO flags */
- while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
- {
- /* Read data from SDIO Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
- }
- tempbuff += 8U;
- }
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock read */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
- {
- *tempbuff = SDIO_ReadFIFO(hsd->Instance);
- tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of SD blocks to write
- * @param Timeout: Specify timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
- uint32_t *tempbuff = (uint32_t *)pData;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Write block(s) in polling mode */
- while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
- {
- /* Write data to SDIO Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
- }
- tempbuff += 8U;
- }
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_TIMEOUT;
- }
- }
-
- /* Send stop transmission command in case of multiblock write */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send stop transmission command */
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
- }
-
- /* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Rx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pRxBuffPtr = (uint32_t *)pData;
- hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Tx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- hsd->pTxBuffPtr = (uint32_t *)pData;
- hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- /* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Rx
- * interrupt event.
- * @param hsd: Pointer SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
-
- /* Set the DMA transfer complete callback */
- hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hsd->hdmarx->XferErrorCallback = SD_DMAError;
-
- /* Set the DMA Abort callback */
- hsd->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable SD DMA transfer */
- __HAL_SD_DMA_ENABLE(hsd);
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Tx
- * interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(NULL == pData)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0U;
-
- /* Enable SD Error interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
-
- /* Set the DMA transfer complete callback */
- hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hsd->hdmatx->XferErrorCallback = SD_DMAError;
-
- /* Set the DMA Abort callback */
- hsd->hdmatx->XferAbortCallback = NULL;
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Enable SDIO DMA transfer */
- __HAL_SD_DMA_ENABLE(hsd);
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Erases the specified memory area of the given SD card.
- * @note This API should be followed by a check on the card state through
- * HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(hsd->State == HAL_SD_STATE_READY)
- {
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- return HAL_ERROR;
- }
-
- if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
- {
- hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_BUSY;
-
- /* Check if the card command class supports erase command */
- if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Get start and end block for high capacity cards */
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
- }
-
- /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- }
-
- /* Send CMD38 ERASE */
- errorstate = SDMMC_CmdErase(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief This function handles SD card interrupt request.
- * @param hsd: Pointer to SD handle
- * @retval None
- */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- /* Check for SDIO interrupt flags */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
-
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
-
- if((hsd->Context & SD_CONTEXT_IT) != RESET)
- {
- if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
- {
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- HAL_SD_ErrorCallback(hsd);
- }
- }
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
- {
- HAL_SD_RxCpltCallback(hsd);
- }
- else
- {
- HAL_SD_TxCpltCallback(hsd);
- }
- }
- else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
- {
- if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
- {
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- HAL_SD_ErrorCallback(hsd);
- }
- }
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
- {
- /* Disable the DMA transfer for transmit request by setting the DMAEN bit
- in the SD DCTRL register */
- hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- hsd->State = HAL_SD_STATE_READY;
-
- HAL_SD_TxCpltCallback(hsd);
- }
- }
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE);
-
- SD_Write_IT(hsd);
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF);
-
- SD_Read_IT(hsd);
- }
-
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- }
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
-
- /* Disable all interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
-
- if((hsd->Context & SD_CONTEXT_DMA) != RESET)
- {
- /* Abort the SD DMA Streams */
- if(hsd->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
- {
- SD_DMATxAbort(hsd->hdmatx);
- }
- }
- else if(hsd->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
- {
- SD_DMARxAbort(hsd->hdmarx);
- }
- }
- else
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- HAL_SD_AbortCallback(hsd);
- }
- }
- else if((hsd->Context & SD_CONTEXT_IT) != RESET)
- {
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
- HAL_SD_ErrorCallback(hsd);
- }
- }
-}
-
-/**
- * @brief return the SD state
- * @param hsd: Pointer to sd handle
- * @retval HAL state
- */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
-{
- return hsd->State;
-}
-
-/**
-* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
-* @retval SD Error Code
-*/
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
-{
- return hsd->ErrorCode;
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hsd: Pointer to SD handle
- * @retval None
- */
- __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_TxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief SD error callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_ErrorCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief SD Abort callbacks
- * @param hsd: Pointer SD handle
- * @retval None
- */
-__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsd);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_ErrorCallback can be implemented in the user file
- */
-}
-
-
-/**
- * @}
- */
-
-/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SD card
- operations and get the related information
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CID register.
- * @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CIDTypeDef structure that
- * contains all CID register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
-{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
- pCID->OEM_AppliID = tmp << 8U;
-
- /* Byte 2 */
- tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
- pCID->ProdName1 = tmp << 24U;
-
- /* Byte 4 */
- tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
- pCID->ProdName1 |= tmp << 16;
-
- /* Byte 5 */
- tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
- pCID->ProdName1 |= tmp << 8U;
-
- /* Byte 6 */
- tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
- pCID->ProdSN = tmp << 24U;
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
- pCID->ProdSN |= tmp << 16U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
- pCID->ProdSN |= tmp << 8U;
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
- pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
- pCID->ManufactDate = (tmp & 0x0FU) << 8U;
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
- pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
- pCID->Reserved2 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns information the information of the card which are stored on
- * the CSD register.
- * @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
- * contains all CSD register parameters
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
-{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
- pCSD->Reserved1 = tmp & 0x03U;
-
- /* Byte 1 */
- tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hsd->CSD[0U] & 0x000000FFU;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
-
- /* Byte 5 */
- tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
-
- /* Byte 6 */
- tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
- pCSD->Reserved2 = 0U; /*!< Reserved */
-
- if(hsd->SdCard.CardType == CARD_SDSC)
- {
- pCSD->DeviceSize = (tmp & 0x03U) << 10U;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
- pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
- pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
- pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
-
- hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
- hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen);
-
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
- hsd->SdCard.LogBlockSize = 512U;
- }
- else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
- {
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize = (tmp & 0x3FU) << 16U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
-
- pCSD->DeviceSize |= (tmp << 8U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
-
- pCSD->DeviceSize |= (tmp);
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
-
- hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U);
- hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U;
- }
- else
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
- pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
- pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
- pCSD->WrProtectGrSize = (tmp & 0x7FU);
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
- pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
- pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
- pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
- pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
- pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
- pCSD->Reserved3 = 0U;
- pCSD->ContentProtectAppli = (tmp & 0x01U);
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
- pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
- pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
- pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
- pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
- pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
- pCSD->ECC = (tmp & 0x03U);
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
- pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
- pCSD->Reserved4 = 1U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the SD status info.
- * @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
- * will contain the SD card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
-{
- uint32_t tmp = 0U;
- uint32_t sd_status[16U];
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_OK)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Byte 0 */
- tmp = (sd_status[0U] & 0xC0U) >> 6U;
- pStatus->DataBusWidth = (uint8_t)tmp;
-
- /* Byte 0 */
- tmp = (sd_status[0U] & 0x20U) >> 5U;
- pStatus->SecuredMode = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (sd_status[0U] & 0x00FF0000U) >> 16U;
- pStatus->CardType = (uint16_t)(tmp << 8U);
-
- /* Byte 3 */
- tmp = (sd_status[0U] & 0xFF000000U) >> 24U;
- pStatus->CardType |= (uint16_t)tmp;
-
- /* Byte 4 */
- tmp = (sd_status[1U] & 0xFFU);
- pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U);
-
- /* Byte 5 */
- tmp = (sd_status[1U] & 0xFF00U) >> 8U;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U);
-
- /* Byte 6 */
- tmp = (sd_status[1U] & 0xFF0000U) >> 16U;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U);
-
- /* Byte 7 */
- tmp = (sd_status[1U] & 0xFF000000U) >> 24U;
- pStatus->ProtectedAreaSize |= (uint32_t)tmp;
-
- /* Byte 8 */
- tmp = (sd_status[2U] & 0xFFU);
- pStatus->SpeedClass = (uint8_t)tmp;
-
- /* Byte 9 */
- tmp = (sd_status[2U] & 0xFF00U) >> 8U;
- pStatus->PerformanceMove = (uint8_t)tmp;
-
- /* Byte 10 */
- tmp = (sd_status[2U] & 0xF00000U) >> 20U;
- pStatus->AllocationUnitSize = (uint8_t)tmp;
-
- /* Byte 11 */
- tmp = (sd_status[2U] & 0xFF000000U) >> 24U;
- pStatus->EraseSize = (uint16_t)(tmp << 8U);
-
- /* Byte 12 */
- tmp = (sd_status[3U] & 0xFFU);
- pStatus->EraseSize |= (uint16_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3U] & 0xFC00U) >> 10U;
- pStatus->EraseTimeout = (uint8_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3U] & 0x0300U) >> 8U;
- pStatus->EraseOffset = (uint8_t)tmp;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Gets the SD card info.
- * @param hsd: Pointer to SD handle
- * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
- * will contain the SD card status information
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
-{
- pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
- pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
- pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
- pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
- pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
- pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
- pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
- pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables wide bus operation for the requested card if supported by
- * card.
- * @param hsd: Pointer to SD handle
- * @param WideMode: Specifies the SD card wide bus mode
- * This parameter can be one of the following values:
- * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
- * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
- * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
- SDIO_InitTypeDef Init;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- /* Check the parameters */
- assert_param(IS_SDIO_BUS_WIDE(WideMode));
-
- /* Chnage Satte */
- hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- if(WideMode == SDIO_BUS_WIDE_8B)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
- else if(WideMode == SDIO_BUS_WIDE_4B)
- {
- errorstate = SD_WideBus_Enable(hsd);
-
- hsd->ErrorCode |= errorstate;
- }
- else if(WideMode == SDIO_BUS_WIDE_1B)
- {
- errorstate = SD_WideBus_Disable(hsd);
-
- hsd->ErrorCode |= errorstate;
- }
- else
- {
- /* WideMode is not a valid argument*/
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- }
- }
- else
- {
- /* MMC Card does not support this feature */
- hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
- else
- {
- /* Configure the SDIO peripheral */
- Init.ClockEdge = hsd->Init.ClockEdge;
- Init.ClockBypass = hsd->Init.ClockBypass;
- Init.ClockPowerSave = hsd->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
- Init.ClockDiv = hsd->Init.ClockDiv;
- SDIO_Init(hsd->Instance, Init);
- }
-
- /* Change State */
- hsd->State = HAL_SD_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Gets the current sd card data state.
- * @param hsd: pointer to SD handle
- * @retval Card state
- */
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t resp1 = 0;
-
- errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_OK)
- {
- hsd->ErrorCode |= errorstate;
- }
-
- cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
-
- return cardstate;
-}
-
-/**
- * @brief Abort the current transfer and disable the SD.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information for SD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
- {
- /* Disable the SD DMA request */
- hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
- {
- HAL_DMA_Abort(hsd->hdmatx);
- }
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
- {
- HAL_DMA_Abort(hsd->hdmarx);
- }
- }
-
- hsd->State = HAL_SD_STATE_READY;
- CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
- }
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information for SD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
- {
- /* Disable the SD DMA request */
- hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
- {
- hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
- if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
- {
- hsd->hdmatx = NULL;
- }
- }
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
- {
- hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
- if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
- {
- hsd->hdmarx = NULL;
- }
- }
- }
-
- /* No transfer ongoing on both DMA channels*/
- if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
- {
- CardState = HAL_SD_GetCardState(hsd);
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
- }
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
- {
- HAL_SD_AbortCallback(hsd);
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA SD transmit process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-
- /* Enable DATAEND Interrupt */
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
-}
-
-/**
- * @brief DMA SD receive process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- /* Send stop command in multiblock write */
- if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
- {
- errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= errorstate;
- HAL_SD_ErrorCallback(hsd);
- }
- }
-
- /* Disable the DMA transfer for transmit request by setting the DMAEN bit
- in the SD DCTRL register */
- hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- hsd->State = HAL_SD_STATE_READY;
-
- HAL_SD_RxCpltCallback(hsd);
-}
-
-/**
- * @brief DMA SD communication error callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SD_DMAError(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- HAL_SD_CardStateTypeDef CardState;
-
- if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
- {
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Disable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- hsd->ErrorCode |= HAL_SD_ERROR_DMA;
- CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
- }
-
- hsd->State= HAL_SD_STATE_READY;
- }
-
- HAL_SD_ErrorCallback(hsd);
-}
-
-/**
- * @brief DMA SD Tx Abort callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmatx != NULL)
- {
- hsd->hdmatx = NULL;
- }
-
- /* All DMA channels are aborted */
- if(hsd->hdmarx == NULL)
- {
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- HAL_SD_AbortCallback(hsd);
- }
- else
- {
- HAL_SD_ErrorCallback(hsd);
- }
- }
- }
-}
-
-/**
- * @brief DMA SD Rx Abort callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmarx != NULL)
- {
- hsd->hdmarx = NULL;
- }
-
- /* All DMA channels are aborted */
- if(hsd->hdmatx == NULL)
- {
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
- HAL_SD_AbortCallback(hsd);
- }
- else
- {
- HAL_SD_ErrorCallback(hsd);
- }
- }
- }
-}
-
-
-/**
- * @brief Initializes the sd card.
- * @param hsd: Pointer to SD handle
- * @retval SD Card error state
- */
-static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
-{
- HAL_SD_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint16_t sd_rca = 1U;
-
- /* Check the power State */
- if(SDIO_GetPowerState(hsd->Instance) == 0U)
- {
- /* Power off */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD2 ALL_SEND_CID */
- errorstate = SDMMC_CmdSendCID(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card identification number data */
- hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
- hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
- hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
- hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
- }
- }
-
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Send CMD3 SET_REL_ADDR with argument 0 */
- /* SD Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- }
- if(hsd->SdCard.CardType != CARD_SECURED)
- {
- /* Get the SD card RCA */
- hsd->SdCard.RelCardAdd = sd_rca;
-
- /* Send CMD9 SEND_CSD with argument as card's RCA */
- errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
- else
- {
- /* Get Card Specific Data */
- hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
- hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
- hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
- hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
- }
- }
-
- /* Get the Card Class */
- hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
-
- /* Get CSD parameters */
- HAL_SD_GetCardCSD(hsd, &CSD);
-
- /* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, hsd->Init);
-
- /* All cards are initialized */
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Enquires cards about their operating voltage and configures clock
- * controls and stores SD information that will be needed in future
- * in the SD handle.
- * @param hsd: Pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
-{
- __IO uint32_t count = 0U;
- uint32_t response = 0U, validvoltage = 0U;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- /* CMD0: GO_IDLE_STATE */
- errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
- errorstate = SDMMC_CmdOperCond(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->SdCard.CardVersion = CARD_V1_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0U)
- {
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
- }
- /* Card type is SDSC */
- hsd->SdCard.CardType = CARD_SDSC;
- }
- else
- {
- hsd->SdCard.CardVersion = CARD_V2_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0U)
- {
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
- }
-
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
- {
- hsd->SdCard.CardType = CARD_SDHC_SDXC;
- }
- else
- {
- hsd->SdCard.CardType = CARD_SDSC;
- }
- }
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Turns the SDIO output signals off.
- * @param hsd: Pointer to SD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
- /* Set Power State to OFF */
- SDIO_PowerState_OFF(hsd->Instance);
-
- return HAL_OK;
-}
-
-/**
- * @brief Send Status info command.
- * @param hsd: pointer to SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
- * SD Status register)
- * @retval error state
- */
-static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
-
- /* Check SD response */
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Set block size for card if it is not equal to current block size for card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Send CMD55 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 64U;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
- errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_NONE;
- return errorstate;
- }
-
- /* Get status data */
- while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
- {
- for(count = 0U; count < 8U; count++)
- {
- *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
- }
-
- pSDstatus += 8U;
- }
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- return HAL_SD_ERROR_DATA_TIMEOUT;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- return HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- return HAL_SD_ERROR_RX_OVERRUN;
- }
-
- while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
- {
- *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
- pSDstatus++;
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- /* Clear all the static status flags*/
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Returns the current card's status.
- * @param hsd: Pointer to SD handle
- * @param pCardStatus: pointer to the buffer that will contain the SD card
- * status (Card Status register)
- * @retval error state
- */
-static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if(pCardStatus == NULL)
- {
- return HAL_SD_ERROR_PARAM;
- }
-
- /* Send Status command */
- errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* Get SD card status */
- *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Enables the SDIO wide bus mode.
- * @param hsd: pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
- uint32_t scr[2U] = {0U, 0U};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Get SCR Register */
- errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* If requested card supports wide bus operation */
- if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
- {
- /* Send CMD55 APP_CMD with argument as card's RCA.*/
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- return HAL_SD_ERROR_NONE;
- }
- else
- {
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-}
-
-/**
- * @brief Disables the SDIO wide bus mode.
- * @param hsd: Pointer to SD handle
- * @retval error state
- */
-static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
- uint32_t scr[2U] = {0U, 0U};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
- {
- return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
- }
-
- /* Get SCR Register */
- errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* If requested card supports 1 bit mode operation */
- if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
- {
- /* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
- errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- return HAL_SD_ERROR_NONE;
- }
- else
- {
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
- }
-}
-
-
-/**
- * @brief Finds the SD card SCR register value.
- * @param hsd: Pointer to SD handle
- * @param pSCR: pointer to the buffer that will contain the SCR value
- * @retval error state
- */
-static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
- SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t tickstart = HAL_GetTick();
- uint32_t index = 0U;
- uint32_t tempscr[2U] = {0U, 0U};
-
- /* Set Block Size To 8 Bytes */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- /* Send CMD55 APP_CMD with argument as card's RCA */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 8U;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
- errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_OK)
- {
- return errorstate;
- }
-
- while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
- {
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
- {
- *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
- index++;
- }
-
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
- {
- return HAL_SD_ERROR_TIMEOUT;
- }
- }
-
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
- return HAL_SD_ERROR_DATA_TIMEOUT;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-
- return HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
- return HAL_SD_ERROR_RX_OVERRUN;
- }
- else
- {
- /* No error flag set */
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\
- ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U);
-
- *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\
- ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U);
- }
-
- return HAL_SD_ERROR_NONE;
-}
-
-/**
- * @brief Wrap up reading in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
-{
- uint32_t count = 0U;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hsd->pRxBuffPtr;
-
- /* Read data from SDIO Rx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- *(tmp + count) = SDIO_ReadFIFO(hsd->Instance);
- }
-
- hsd->pRxBuffPtr += 8U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Wrap up writing in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
- * the configuration information.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
-{
- uint32_t count = 0U;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hsd->pTxBuffPtr;
-
- /* Write data to SDIO Tx FIFO */
- for(count = 0U; count < 8U; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, (tmp + count));
- }
-
- hsd->pTxBuffPtr += 8U;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_smartcard.c b/lib/hal-stm32f1/source/stm32f1xx_hal_smartcard.c deleted file mode 100644 index 9ba95725..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_smartcard.c +++ /dev/null @@ -1,1912 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_smartcard.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SMARTCARD HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the SMARTCARD peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SMARTCARD HAL driver can be used as follows:
-
- (#) Declare a SMARTCARD_HandleTypeDef handle structure.
- (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) SMARTCARD pins configuration:
- (+++) Enable the clock for the SMARTCARD GPIOs.
- (+++) Configure the SMARTCARD pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
- and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
- and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
-
- (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMARTCARD_MspInit() API.
- [..]
- (@)The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
- [..]
- Three operation modes are available within this driver:
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
- *** SMARTCARD HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in SMARTCARD HAL driver.
-
- (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-
- [..]
- (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
- @endverbatim
- [..]
- (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible SMARTCARD frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | SMARTCARD frame |
- |---------------------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SMARTCARD SMARTCARD
- * @brief HAL SMARTCARD module driver
- * @{
- */
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions
- * @{
- */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
- * @{
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in Smartcard mode.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
- (+) For the Smartcard mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length => Should be 9 bits (8 bits + parity)
- (++) Stop Bit
- (++) Parity: => Should be enabled
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
- (++) Prescaler
- (++) GuardTime
- (++) NACKState: The Smartcard NACK state
-
- (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
- (++) Word Length = 9 Bits
- (++) 1.5 Stop Bit
- (++) Even parity
- (++) BaudRate = 12096 baud
- (++) Tx and Rx enabled
- [..]
- Please refer to the ISO 7816-3 specification for more details.
-
- [..]
- (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
- [..]
- The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
- procedure (details for the procedure are available in reference manual (RM0329)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SmartCard mode according to the specified
- * parameters in the SMARTCARD_InitTypeDef and create the associated handle.
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-
-
- if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_SMARTCARD_MspInit(hsc);
- }
-
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* Set the Prescaler */
- MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
-
- /* Set the Guard Time */
- MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
-
- /* Set the Smartcard Communication parameters */
- SMARTCARD_SetConfig(hsc);
-
- /* In SmartCard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register
- - HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the SMARTCARD Framing Error Interrupt */
- SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the Peripheral */
- __HAL_SMARTCARD_ENABLE(hsc);
-
- /* Configure the Smartcard NACK state */
- MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
-
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- hsc->Instance->CR3 |= (USART_CR3_SCEN);
-
- /* Initialize the SMARTCARD state*/
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState= HAL_SMARTCARD_STATE_READY;
- hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the USART SmartCard peripheral
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Check the SMARTCARD handle allocation */
- if(hsc == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_SMARTCARD_MspDeInit(hsc);
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_RESET;
- hsc->RxState = HAL_SMARTCARD_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsc);
-
- return HAL_OK;
-}
-
-/**
- * @brief SMARTCARD MSP Init.
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SMARTCARD MSP DeInit
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
- *
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
- [..]
- (#) Smartcard is a single wire half duplex communication protocol.
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- (#) The USART should be configured as:
- (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send an amount of data in blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
- while(hsc->TxXferCount > 0U)
- {
- hsc->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
- pData +=1U;
- }
-
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- hsc->RxXferSize = Size;
- hsc->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(hsc->RxXferCount > 0U)
- {
- hsc->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
- pData +=1U;
- }
-
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->pTxBuffPtr = pData;
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the SMARTCARD Transmit data register empty Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->pRxBuffPtr = pData;
- hsc->RxXferSize = Size;
- hsc->RxXferCount = Size;
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->pTxBuffPtr = pData;
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsc->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the SMARTCARD transmit DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD CR3 register */
- SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->pRxBuffPtr = pData;
- hsc->RxXferSize = Size;
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsc->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
-
- /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
- __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD CR3 register */
- SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
- if(hsc->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsc->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsc->hdmatx);
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
- if(hsc->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsc->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsc->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- hsc->TxXferCount = 0x00U;
- hsc->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Restore hsc->RxState and hsc->gState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
- if(hsc->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsc->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsc->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- hsc->TxXferCount = 0x00U;
-
- /* Restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
- if(hsc->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- hsc->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(hsc->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- hsc->RxXferCount = 0x00U;
-
- /* Restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
-{
- uint32_t AbortCplt = 0x01U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hsc->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
- {
- hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
- }
- else
- {
- hsc->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hsc->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
- }
- else
- {
- hsc->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at SMARTCARD level */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsc->hdmatx != NULL)
- {
- /* SMARTCARD Tx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
- {
- hsc->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsc->hdmarx != NULL)
- {
- /* SMARTCARD Rx DMA Abort callback has already been initialised :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
- {
- hsc->hdmarx->XferAbortCallback = NULL;
- AbortCplt = 0x01U;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
- {
- /* Reset Tx and Rx transfer counters */
- hsc->TxXferCount = 0x00U;
- hsc->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Restore hsc->gState and hsc->RxState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsc);
- }
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsc->hdmatx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
- {
- /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
- hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsc->TxXferCount = 0x00U;
-
- /* Restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- hsc->TxXferCount = 0x00U;
-
- /* Restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param hsc SMARTCARD handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsc->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
- {
- /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
- hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsc->RxXferCount = 0x00U;
-
- /* Restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- hsc->RxXferCount = 0x00U;
-
- /* Restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles SMARTCARD interrupt request.
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
-{
- uint32_t isrflags = READ_REG(hsc->Instance->SR);
- uint32_t cr1its = READ_REG(hsc->Instance->CR1);
- uint32_t cr3its = READ_REG(hsc->Instance->CR3);
- uint32_t dmarequest = 0x00U;
- uint32_t errorflags = 0x00U;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
- {
- /* SMARTCARD in mode Receiver -------------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsc);
- return;
- }
- }
-
- /* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* SMARTCARD parity error interrupt occurred ---------------------------*/
- if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- }
-
- /* SMARTCARD noise error interrupt occurred ----------------------------*/
- if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
- }
-
- /* SMARTCARD frame error interrupt occurred ----------------------------*/
- if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
- }
-
- /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
- if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
- }
-
- /* Call SMARTCARD Error Call back function if need be ------------------*/
- if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
- {
- /* SMARTCARD in mode Receiver ----------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- SMARTCARD_Receive_IT(hsc);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
- if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
- {
- /* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- SMARTCARD_EndRxTransfer(hsc);
-
- /* Disable the SMARTCARD DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the SMARTCARD DMA Rx channel */
- if(hsc->hdmarx != NULL)
- {
- /* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- }
- }
- return;
- } /* End if some error occurs */
-
- /* SMARTCARD in mode Transmitter -------------------------------------------*/
- if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- SMARTCARD_Transmit_IT(hsc);
- return;
- }
-
- /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- SMARTCARD_EndTransmit_IT(hsc);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SMARTCARD error callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SMARTCARD Abort Complete callback.
- * @param hsc SMARTCARD handle.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort Transmit Complete callback.
- * @param hsc SMARTCARD handle.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief SMARTCARD Abort ReceiveComplete callback.
- * @param hsc SMARTCARD handle.
- * @retval None
- */
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SmartCard.
- (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
- (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
-@endverbatim
- * @{
- */
-
-/**
- * @brief return the SMARTCARD state
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval HAL state
- */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hsc->gState;
- temp2 = hsc->RxState;
-
- return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the SMARTCARD error code
- * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD.
- * @retval SMARTCARD Error Code
- */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
-{
- return hsc->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief DMA SMARTCARD transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief DMA SMARTCARD receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->RxXferCount = 0U;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsc);
-}
-
-/**
- * @brief DMA SMARTCARD communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
- uint32_t dmarequest = 0x00U;
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0U;
- hsc->TxXferCount = 0U;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
- /* Stop SMARTCARD DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
- if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
- {
- SMARTCARD_EndTxTransfer(hsc);
- }
-
- /* Stop SMARTCARD DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
- if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
- {
- SMARTCARD_EndRxTransfer(hsc);
- }
-
- HAL_SMARTCARD_ErrorCallback(hsc);
-}
-
-/**
- * @brief This function handles SMARTCARD Communication Timeout.
- * @param hsc: SMARTCARD handle
- * @param Flag: specifies the SMARTCARD flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- /* Disable TXE and RXNE interrupts for the interrupt process */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
-
- hsc->gState= HAL_SMARTCARD_STATE_READY;
- hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsc: SMARTCARD handle.
- * @retval None
- */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
- /* At end of Tx process, restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-}
-
-
-/**
- * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
- * @param hsc: SMARTCARD handle.
- * @retval None
- */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-}
-
-
-
-/**
- * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0x00U;
- hsc->TxXferCount = 0x00U;
-
- HAL_SMARTCARD_ErrorCallback(hsc);
-}
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsc->hdmarx != NULL)
- {
- if(hsc->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsc->TxXferCount = 0x00U;
- hsc->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Restore hsc->gState and hsc->RxState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsc);
-}
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hsc->hdmatx != NULL)
- {
- if(hsc->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hsc->TxXferCount = 0x00U;
- hsc->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Restore hsc->gState and hsc->RxState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortCpltCallback(hsc);
-}
-
-/**
- * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->TxXferCount = 0x00U;
-
- /* Restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
-}
-
-/**
- * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
- * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->RxXferCount = 0x00U;
-
- /* Restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
-}
-
-/**
- * @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- tmp = (uint16_t*) hsc->pTxBuffPtr;
- hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- hsc->pTxBuffPtr += 1U;
-
- if(--hsc->TxXferCount == 0U)
- {
- /* Disable the SMARTCARD Transmit data register empty Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
-
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
-{
- uint16_t* tmp;
-
- /* Check that a Rx process is ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- tmp = (uint16_t*) hsc->pRxBuffPtr;
- *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- hsc->pRxBuffPtr += 1U;
-
- if(--hsc->RxXferCount == 0U)
- {
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsc);
-
- return HAL_OK;
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure the SMARTCARD peripheral
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for SMARTCARD module.
- * @retval None
- */
-static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
-{
- uint32_t tmpreg = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
- assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
- assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
- assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
- assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
- assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
- assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
- assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
- assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
- assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
-
-
- /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
- receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
-
- /*---------------------------- USART CR2 Configuration ---------------------*/
- tmpreg = hsc->Instance->CR2;
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
- /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
- /* Set CPOL bit according to hsc->Init.CLKPolarity value */
- /* Set CPHA bit according to hsc->Init.CLKPhase value */
- /* Set LBCL bit according to hsc->Init.CLKLastBit value */
- /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
- tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
- hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
- /* Write to USART CR2 */
- WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
-
- tmpreg = hsc->Instance->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
- tmpreg |= (uint32_t)(hsc->Init.StopBits);
-
- /* Write to USART CR2 */
- WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = hsc->Instance->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE));
-
- /* Configure the SMARTCARD Word Length, Parity and mode:
- Set the M bits according to hsc->Init.WordLength value
- Set PCE and PS bits according to hsc->Init.Parity value
- Set TE and RE bits according to hsc->Init.Mode value */
- tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
-
- /* Write to USART CR1 */
- WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Clear CTSE and RTSE bits */
- CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-
- /*-------------------------- USART BRR Configuration -----------------------*/
-
- if(hsc->Instance == USART1)
- {
- hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
- }
- else
- {
- hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_spi.c b/lib/hal-stm32f1/source/stm32f1xx_hal_spi.c deleted file mode 100644 index 109080e6..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_spi.c +++ /dev/null @@ -1,3266 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_spi.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Serial Peripheral Interface (SPI) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
- (+++) Enable the DMAx clock
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Channel
- (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SPI_MspInit() API.
- [..]
- Circular mode restriction:
- (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
- (##) Master 2Lines RxOnly
- (##) Master 1Line Rx
- (#) The CRC feature is not managed when the DMA circular mode is enabled
- (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
- the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
- [..]
- Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
- bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
- does not initiate a new transfer the following procedure has to be respected:
- (##) HAL_SPI_DeInit()
- (##) HAL_SPI_Init()
-
- @endverbatim
-
- Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
- the following tables resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
-
- DataSize = SPI_DATASIZE_8BIT:
- +--------------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==================================================================================================|
- | T | Polling | fPCLK/2 | fPCLK/16 | NA | NA | NA | NA |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | / | Interrupt | fPCLK/8 | fPCLK/32 | NA | NA | NA | NA |
- | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | R | Interrupt | fPCLK/8 | fPCLK/16 | fPCLK/32 | fPCLK/16 | fPCLK/64 | fPCLK/4 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/16 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/2 | fPCLK/32 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/2 | fPCLK/64 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
- +--------------------------------------------------------------------------------------------------+
-
- DataSize = SPI_DATASIZE_16BIT:
- +--------------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==================================================================================================|
- | T | Polling | fPCLK/4 | fPCLK/4 | NA | NA | NA | NA |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | / | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | NA | NA |
- | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/8 | fPCLK/64 | fPCLK/2 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | R | Interrupt | fPCLK/8 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/4 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/8 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/4 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/4 | fPCLK/8 |
- +--------------------------------------------------------------------------------------------------+
- [..]
- (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- (@)
- (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-/** @defgroup SPI SPI
- * @brief SPI HAL module driver
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_DEFAULT_TIMEOUT 100U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
- * @{
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-#if (USE_SPI_CRC != 0U)
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif /* USE_SPI_CRC */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPIx peripheral:
-
- (+) User must implement HAL_SPI_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPI_Init() to configure the selected device with
- the selected configuration:
- (++) Mode
- (++) Direction
- (++) Data Size
- (++) Clock Polarity and Phase
- (++) NSS Management
- (++) BaudRate Prescaler
- (++) FirstBit
- (++) TIMode
- (++) CRC Calculation
- (++) CRC Polynomial if CRC enabled
-
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx peripheral.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the SPI according to the specified parameters
- * in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if(hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- if(hspi->State == HAL_SPI_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hspi->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
- Communication speed, First bit and CRC calculation state */
- WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
-
- /* Configure : NSS management */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
-
-#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
- }
-#endif /* USE_SPI_CRC */
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief De Initialize the SPI peripheral.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if(hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check SPI Instance parameter */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disable the SPI Peripheral Clock */
- __HAL_SPI_DISABLE(hspi);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
- HAL_SPI_MspDeInit(hspi);
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
-}
-
-/**
- * @brief De-Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit should be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SPI
- data transfers.
-
- [..] The SPI supports master and slave mode :
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
- exist for 1Line (simplex) and 2Lines (full duplex) modes.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmit an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pData == NULL ) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
- {
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- /* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- /* Transmit data in 8 Bit mode */
- else
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
- {
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
- pData += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- while (hspi->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set to send data */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
- {
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
- pData += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- else
- {
- /* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_ERROR;
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error:
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pData == NULL ) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- /* this is done to handle the CRCNEXT before the latest data */
- hspi->RxXferCount--;
- }
-#endif /* USE_SPI_CRC */
-
- /* Configure communication direction: 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
- {
- /* Transfer loop */
- while(hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- /* read the received data */
- (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
- pData += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
- else
- {
- /* Transfer loop */
- while(hspi->RxXferCount > 0U)
- {
- /* Check the RXNE flag */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
- {
- *((uint16_t*)pData) = hspi->Instance->DR;
- pData += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
- else
- {
- /* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Handle the CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* freeze the CRC before the latest data */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-
- /* Read the latest data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* the latest data has not been received */
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- *((uint16_t*)pData) = hspi->Instance->DR;
- }
- /* Receive last data in 8 Bit mode */
- else
- {
- (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
-
- /* Wait the CRC data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg1 = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
- /* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
-
- if(!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferCount = Size;
- hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount--;
- }
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* Check TXE flag */
- if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Check RXNE flag */
- if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
- {
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
- /* Transmit and Receive data in 8 Bit mode */
- else
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
- {
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
- pTxData += sizeof(uint8_t);
- hspi->TxXferCount--;
- }
- while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
- {
- /* check TXE flag */
- if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
- {
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
- hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
- txallowed = 0U;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- }
-
- /* Wait until RXNE flag is reset */
- if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
- {
- (*(uint8_t *)pRxData++) = hspi->Instance->DR;
- hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
- }
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- }
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- errorcode = HAL_TIMEOUT;
- goto error;
- }
- /* Read CRC */
- tmpreg1 = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg1);
- }
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- errorcode = HAL_ERROR;
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_ERROR;
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
-error :
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
- hspi->RxISR = NULL;
-
- /* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->TxISR = SPI_TxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- /* Enable TXE interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
- }
- else
- {
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- }
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
- hspi->TxISR = NULL;
-
- /* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = SPI_RxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_RxISR_8BIT;
- }
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
-
- if(!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->TxISR = NULL;
- hspi->RxISR = NULL;
- hspi->RxXferSize = 0U;
- hspi->RxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
- {
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pData == NULL) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Set the transaction information */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = (uint8_t *)pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
- hspi->TxXferSize = 0U;
- hspi->TxXferCount = 0U;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-error:
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
-
- /* Check Direction parameter */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
-
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
- if(!((tmp == HAL_SPI_STATE_READY) ||
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- errorcode = HAL_ERROR;
- goto error;
- }
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Set the transaction information */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t*)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t*)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Init field not used in handle to zero */
- hspi->RxISR = NULL;
- hspi->TxISR = NULL;
-
-#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-#endif /* USE_SPI_CRC */
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- }
- else
- {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the Rx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
- hspi->hdmatx->XferErrorCallback = NULL;
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the Tx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
- /* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return errorcode;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
- * before starting new SPI receive process.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- }
-
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- }
-
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- HAL_DMA_Abort(hspi->hdmatx);
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
-
- /* Wait until TXE flag is set */
- do
- {
- if(count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- }
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
- }
- /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- HAL_DMA_Abort(hspi->hdmarx);
-
- /* Disable peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
-
- }
- }
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->state to ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param hspi SPI handle.
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
- * started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable SPI Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
- * before starting new SPI receive process.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
-{
- uint32_t abortcplt;
-
- /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
- {
- hspi->TxISR = SPI_AbortTx_ISR;
- }
-
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
- {
- hspi->RxISR = SPI_AbortRx_ISR;
- }
-
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- abortcplt = 1U;
-
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(hspi->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
- }
- else
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(hspi->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
- }
- else
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- /* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
- {
- /* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
- {
- /* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- if(abortcplt == 1U)
- {
- /* Reset Tx and Rx transfer counters */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
- }
- return HAL_OK;
-}
-
-/**
- * @brief Pause the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resume the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Enable the SPI DMA Tx & Rx requests */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
- */
-
- /* Abort the SPI DMA tx Stream */
- if(hspi->hdmatx != NULL)
- {
- HAL_DMA_Abort(hspi->hdmatx);
- }
- /* Abort the SPI DMA rx Stream */
- if(hspi->hdmarx != NULL)
- {
- HAL_DMA_Abort(hspi->hdmarx);
- }
-
- /* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI interrupt request.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None
- */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
- uint32_t itsource = hspi->Instance->CR2;
- uint32_t itflag = hspi->Instance->SR;
-
- /* SPI in mode Receiver ----------------------------------------------------*/
- if(((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
- {
- hspi->RxISR(hspi);
- return;
- }
-
- /* SPI in mode Transmitter -------------------------------------------------*/
- if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
- {
- hspi->TxISR(hspi);
- return;
- }
-
- /* SPI in Error Treatment --------------------------------------------------*/
- if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
- {
- /* SPI Overrun error interrupt occurred ----------------------------------*/
- if((itflag & SPI_FLAG_OVR) != RESET)
- {
- if(hspi->State != HAL_SPI_STATE_BUSY_TX)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- return;
- }
- }
-
- /* SPI Mode Fault error interrupt occurred -------------------------------*/
- if((itflag & SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- /* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-
- hspi->State = HAL_SPI_STATE_READY;
- /* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
- {
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
-
- /* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
- }
- /* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
- {
- /* Set the SPI DMA Abort callback :
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_SPI_ErrorCallback(hspi);
- }
- }
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Half Transfer callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
-}
-
-/**
- * @brief SPI error callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred
- */
-}
-
-/**
- * @brief SPI Abort Complete callback.
- * @param hspi SPI handle.
- * @retval None
- */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
- (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the SPI handle state.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI state
- */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI handle state */
- return hspi->State;
-}
-
-/**
- * @brief Return the SPI error code.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI error code in bitmap format
- */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
- /* Return SPI ErrorCode */
- return hspi->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @brief Private functions
- * @{
- */
-
-/**
- * @brief DMA SPI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t tickstart = 0U;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* DMA Normal Mode */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->TxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_TxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-#if (USE_SPI_CRC != 0U)
- uint32_t tickstart = 0U;
- __IO uint16_t tmpreg = 0U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-#endif /* USE_SPI_CRC */
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until RXNE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- /* Error on the CRC reception */
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- /* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_RxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
- {
-#if (USE_SPI_CRC != 0U)
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait the CRC data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- }
- /* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
- }
-#endif /* USE_SPI_CRC */
- /* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Rx/Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0U;
- hspi->RxXferCount = 0U;
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
- }
- }
- HAL_SPI_TxRxCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-/* Stop the disable DMA transfer on SPI side */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hspi->hdmatx->XferAbortCallback = NULL;
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
-
- /* Wait until TXE flag is set */
- do
- {
- if(count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- }
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Check if an Abort process is still ongoing */
- if(hspi->hdmarx != NULL)
- {
- if(hspi->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- hspi->hdmarx->XferAbortCallback = NULL;
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Check if an Abort process is still ongoing */
- if(hspi->hdmatx != NULL)
- {
- if(hspi->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hspi->RxXferCount = 0U;
- hspi->TxXferCount = 0U;
-
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- /* Clear the Error flags in the SR register */
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
-
- /* Restore hspi->State to Ready */
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_SPI_AbortCpltCallback(hspi);
-}
-
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 8bit mode */
- *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
- hspi->RxXferCount--;
-
- /* check end of the reception */
- if(hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if(hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
-
- UNUSED(tmpreg);
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- if(hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
- /* check the end of the transmission */
- if(hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if(hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-/**
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
- if(hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if(hspi->TxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- SPI_CloseRxTx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if(hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- return;
- }
-#endif /* USE_SPI_CRC */
-
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
- if(hspi->RxXferCount == 0U)
- {
- SPI_CloseRxTx_ISR(hspi);
- }
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_8BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
-{
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- SPI_CloseRx_ISR(hspi);
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
-
- if(hspi->RxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->RxISR = SPI_RxISR_16BITCRC;
- return;
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseRx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
-{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
- if(hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
- /* Transmit data in 16 Bit mode */
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
-
- if(hspi->TxXferCount == 0U)
- {
-#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Enable CRC Transmission */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- SPI_CloseTx_ISR(hspi);
- }
-}
-
-/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param State: flag state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
-{
- while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State= HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-/**
- * @brief Handle to check BSY flag before start a new transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
-{
- /* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle the end of the RXTX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart = 0U;
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
- /* Wait until TXE flag is set */
- do
- {
- if(count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- }
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- hspi->State = HAL_SPI_STATE_READY;
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- }
- else
- {
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the RX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
-{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- hspi->State = HAL_SPI_STATE_READY;
-
-#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
-
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
- else
- {
-#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
-#if (USE_SPI_CRC != 0U)
- }
-#endif /* USE_SPI_CRC */
-}
-
-/**
- * @brief Handle the end of the TX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
-{
- uint32_t tickstart = 0U;
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
- /* Wait until TXE flag is set */
- do
- {
- if(count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- }
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Disable TXE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- HAL_SPI_TxCpltCallback(hspi);
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Handle abort a Tx or Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
-{
- __IO uint32_t tmpreg = 0U;
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
- /* Wait until TXE flag is set */
- do
- {
- if(count-- == 0U)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- break;
- }
- }
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
- /* Flush DR Register */
- tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
-}
-
-/**
- * @brief Handle abort a Tx or Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
-{
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
- /* Disable SPI Peripheral */
- __HAL_SPI_DISABLE(hspi);
-}
-
-/**
- * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
- * according to SPI instance, Device type, and revision ID.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
-*/
-__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- return (SPI_VALID_CRC_ERROR);
-}
-/**
- * @}
- */
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_spi_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_spi_ex.c deleted file mode 100644 index 6acbba33..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_spi_ex.c +++ /dev/null @@ -1,233 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_spi_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief Extended SPI HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities SPI extension peripheral:
- * + Extended Peripheral Control functions
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/** @defgroup SPI_Private_Variables SPI Private Variables
- * @{
- */
-#if (USE_SPI_CRC != 0U)
-/* Variable used to determine if device is impacted by implementation of workaround
- related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
- - STM32F101CDE/STM32F103CDE
- - Revision ID : Z
- - SPI2
- - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
- the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
- + If the value is 0, the complete data transfer is successful.
- + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
- If CRCERR is found reset, the complete data transfer is considered successful.
-*/
-uint8_t uCRCErrorWorkaroundCheck = 0U;
-#endif /* USE_SPI_CRC */
-/**
- * @}
- */
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- *
- * @{
- */
-
-/**
- * @brief Initializes the SPI according to the specified parameters
- * in the SPI_InitTypeDef and create the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
- /* Check the SPI handle allocation */
- if(hspi == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
- assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
- assert_param(IS_SPI_NSS(hspi->Init.NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-
-#if (USE_SPI_CRC != 0U)
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- }
-#else
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-#endif /* USE_SPI_CRC */
-
- if(hspi->State == HAL_SPI_STATE_RESET)
- {
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Disble the selected SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
- /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
- Communication speed, First bit and CRC calculation state */
- WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
-
- /* Configure : NSS management */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
-
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
- /* Configure : CRC Polynomial */
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
-
-#if defined(SPI_I2SCFGR_I2SMOD)
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2SCFGR_I2SMOD */
-
-#if (USE_SPI_CRC != 0U)
-#if defined (STM32F101xE) || defined (STM32F103xE)
- /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
- CRC errors wrongly detected */
- /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
- Revision ID information is only available in Debug mode, so Workaround could not be implemented
- to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
- So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
- uCRCErrorWorkaroundCheck = 0U;
-#else
- uCRCErrorWorkaroundCheck = 0U;
-#endif /* STM32F101xE || STM32F103xE */
-#endif /* USE_SPI_CRC */
-
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup SPI_Private_Functions
- * @{
- */
-#if (USE_SPI_CRC != 0U)
-/**
- * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
- * according to SPI instance, Device type, and revision ID.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
-*/
-uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
-{
-#if defined(STM32F101xE) || defined(STM32F103xE)
- /* Check how to handle this CRC error (workaround to be applied or not) */
- /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
- if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
- {
- if(hspi->Instance->RXCRCR == 0U)
- {
- return (SPI_INVALID_CRC_ERROR);
- }
- }
- return (SPI_VALID_CRC_ERROR);
-#else
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
-
- return (SPI_VALID_CRC_ERROR);
-#endif
-}
-#endif /* USE_SPI_CRC */
-
-/**
- * @}
- */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_sram.c b/lib/hal-stm32f1/source/stm32f1xx_hal_sram.c deleted file mode 100644 index ed95b6fc..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_sram.c +++ /dev/null @@ -1,692 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_sram.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SRAM HAL module driver.
- * This file provides a generic firmware to drive SRAM memories
- * mounted as external device.
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a generic layered driver which contains a set of APIs used to
- control SRAM memories. It uses the FSMC layer functions to interface
- with SRAM devices.
- The following sequence should be followed to configure the FSMC to interface
- with SRAM/PSRAM memories:
-
- (#) Declare a SRAM_HandleTypeDef handle structure, for example:
- SRAM_HandleTypeDef hsram; and:
-
- (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
- values of the structure member.
-
- (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
- base register instance for NOR or SRAM device
-
- (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
- base register instance for NOR or SRAM extended mode
-
- (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
- mode timings; for example:
- FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
- and fill its fields with the allowed values of the structure member.
-
- (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
- performs the following sequence:
-
- (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
- (##) Control register configuration using the FSMC NORSRAM interface function
- FSMC_NORSRAM_Init()
- (##) Timing register configuration using the FSMC NORSRAM interface function
- FSMC_NORSRAM_Timing_Init()
- (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
- FSMC_NORSRAM_Extended_Timing_Init()
- (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
-
- (#) At this stage you can perform read/write accesses from/to the memory connected
- to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
- following APIs:
- (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
- (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-
- (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
- HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
-
- (#) You can continuously monitor the SRAM device HAL state by calling the function
- HAL_SRAM_GetState()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-
-/** @defgroup SRAM SRAM
- * @brief SRAM driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
- @verbatim
- ==============================================================================
- ##### SRAM Initialization and de_initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to initialize/de-initialize
- the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param Timing: Pointer to SRAM control timing structure
- * @param ExtTiming: Pointer to SRAM extended mode timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
- /* Check the SRAM handle parameter */
- if(hsram == NULL)
- {
- return HAL_ERROR;
- }
-
- if(hsram->State == HAL_SRAM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hsram->Lock = HAL_UNLOCKED;
-
- /* Initialize the low level hardware (MSP) */
- HAL_SRAM_MspInit(hsram);
- }
-
- /* Initialize SRAM control Interface */
- FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
-
- /* Initialize SRAM timing Interface */
- FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
-
- /* Initialize SRAM extended mode timing Interface */
- FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
-
- /* Enable the NORSRAM device */
- __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
-
- return HAL_OK;
-}
-
-/**
- * @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{
- /* De-Initialize the low level hardware (MSP) */
- HAL_SRAM_MspDeInit(hsram);
-
- /* Configure the SRAM registers with their reset values */
- FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
-
- hsram->State = HAL_SRAM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief SRAM MSP Init.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief SRAM MSP DeInit.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hsram);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA transfer complete error callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval None
- */
-__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @brief Input Output and memory control functions
- *
- @verbatim
- ==============================================================================
- ##### SRAM Input and Output functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to use and control the SRAM memory
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint8_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint8_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint16_t *)psramaddress;
- pDstBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
-{
- __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint16_t *)psramaddress = *pSrcBuffer;
- pSrcBuffer++;
- psramaddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Read data from memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *pDstBuffer = *(__IO uint32_t *)pAddress;
- pDstBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Write data to memory */
- for(; BufferSize != 0U; BufferSize--)
- {
- *(__IO uint32_t *)pAddress = *pSrcBuffer;
- pSrcBuffer++;
- pAddress++;
- }
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
- /* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Configure DMA user callbacks */
- hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the SRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Enable write operation */
- FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
-{
- /* Process Locked */
- __HAL_LOCK(hsram);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_BUSY;
-
- /* Disable write operation */
- FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
-
- /* Update the SRAM controller state */
- hsram->State = HAL_SRAM_STATE_PROTECTED;
-
- /* Process unlocked */
- __HAL_UNLOCK(hsram);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### SRAM State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the SRAM controller
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the SRAM controller state
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
- * the configuration information for SRAM module.
- * @retval HAL state
- */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
-{
- return hsram->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_tim.c b/lib/hal-stm32f1/source/stm32f1xx_hal_tim.c deleted file mode 100644 index 831b79d6..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_tim.c +++ /dev/null @@ -1,5393 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief TIM HAL module driver
- * This file provides firmware functions to manage the following
- * functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
- * + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
- @verbatim
- ==============================================================================
- ##### TIMER Generic features #####
- ==============================================================================
- [..] The Timer features include:
- (#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
- counter clock frequency either by any factor between 1 and 65536.
- (#) Up to 4 independent channels for:
- (++) Input Capture
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Time Base : HAL_TIM_Base_MspInit()
- (++) Input Capture : HAL_TIM_IC_MspInit()
- (++) Output Compare : HAL_TIM_OC_MspInit()
- (++) PWM generation : HAL_TIM_PWM_MspInit()
- (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- Initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
- (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
- (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
- (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
- (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
- (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
- (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
- (#) The DMA Burst is managed with the two following functions:
- HAL_TIM_DMABurst_WriteStart()
- HAL_TIM_DMABurst_ReadStart()
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIM TIM
- * @brief TIM HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief Time Base functions
- *
-@verbatim
- ==============================================================================
- ##### Time Base functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
- (+) De-initialize the TIM base.
- (+) Start the Time Base.
- (+) Stop the Time Base.
- (+) Start the Time Base and enable interrupt.
- (+) Stop the Time Base and disable interrupt.
- (+) Start the Time Base and enable DMA transfer.
- (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim : TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Base peripheral
- * @param htim : TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Base MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Base MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Base_MspDeInit could be implemented in the user file
- */
-}
-
-
-/**
- * @brief Starts the TIM Base generation.
- * @param htim : TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation.
- * @param htim : TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable the TIM Update interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Base generation in DMA mode.
- * @param htim : TIM handle
- * @param pData : The source Buffer address.
- * @param Length : The length of data to be transferred from memory to peripheral.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
- /* Enable the TIM Update DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Base generation in DMA mode.
- * @param htim : TIM handle
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Time Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
- (+) De-initialize the TIM Output Compare.
- (+) Start the Time Output Compare.
- (+) Stop the Time Output Compare.
- (+) Start the Time Output Compare and enable interrupt.
- (+) Stop the Time Output Compare and disable interrupt.
- (+) Start the Time Output Compare and enable DMA transfer.
- (+) Stop the Time Output Compare and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim : TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim : TIM Output Compare handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Output Compare MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Output Compare MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData : The source Buffer address.
- * @param Length : The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Time PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM PWM.
- (+) De-initialize the TIM PWM.
- (+) Start the Time PWM.
- (+) Stop the Time PWM.
- (+) Start the Time PWM and enable interrupt.
- (+) Stop the Time PWM and disable interrupt.
- (+) Start the Time PWM and enable DMA transfer.
- (+) Stop the Time PWM and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim : TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim : TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM PWM MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData : The source Buffer address.
- * @param Length : The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Capture/Compare 3 request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
- *
-@verbatim
- ==============================================================================
- ##### Time Input Capture functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
- (+) De-initialize the TIM Input Capture.
- (+) Start the Time Input Capture.
- (+) Stop the Time Input Capture.
- (+) Start the Time Input Capture and enable interrupt.
- (+) Stop the Time Input Capture and disable interrupt.
- (+) Start the Time Input Capture and enable DMA transfer.
- (+) Stop the Time Input Capture and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim : TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM peripheral
- * @param htim : TIM Input Capture handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_IC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Input Capture MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_IC_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData : The destination Buffer address.
- * @param Length : The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Time One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
- (+) De-initialize the TIM One Pulse.
- (+) Start the Time One Pulse.
- (+) Stop the Time One Pulse.
- (+) Start the Time One Pulse and enable interrupt.
- (+) Stop the Time One Pulse and disable interrupt.
- (+) Start the Time One Pulse and enable DMA transfer.
- (+) Stop the Time One Pulse and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim : TIM OnePulse handle
- * @param OnePulseMode : Select the One pulse mode.
- * This parameter can be one of the following values:
- * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_OnePulse_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the One Pulse Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Reset the OPM Bit */
- htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
- /* Configure the OPM Mode */
- htim->Instance->CR1 |= OnePulseMode;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM One Pulse
- * @param htim : TIM One Pulse handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_OnePulse_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM One Pulse MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Enable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
- No need to enable the counter, it's enabled automatically by hardware
- (the counter starts in response to a stimulus and generate a pulse */
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the Capture compare and the Input Capture channels
- (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
- if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- {
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
- *
-@verbatim
- ==============================================================================
- ##### Time Encoder functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
- (+) De-initialize the TIM Encoder.
- (+) Start the Time Encoder.
- (+) Stop the Time Encoder.
- (+) Start the Time Encoder and enable interrupt.
- (+) Stop the Time Encoder and disable interrupt.
- (+) Start the Time Encoder and enable DMA transfer.
- (+) Stop the Time Encoder and disable DMA transfer.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim : TIM Encoder Interface handle
- * @param sConfig : TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
-{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
- assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
-
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim : TIM Encoder handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIM_Encoder_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Encoder Interface MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
- }
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
- }
- }
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts 1 and 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1 : The destination Buffer address for IC1.
- * @param pData2 : The destination Buffer address for IC2.
- * @param Length : The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- }
- break;
-
- case TIM_CHANNEL_ALL:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the TIM Input Capture DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- default:
- break;
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- else
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- /* Disable the capture compare DMA Request 1 and 2 */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- *
-@verbatim
- ==============================================================================
- ##### IRQ handler management #####
- ==============================================================================
- [..]
- This section provides Timer IRQ handler function.
-
-@endverbatim
- * @{
- */
-/**
- * @brief This function handles TIM interrupts requests.
- * @param htim : TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- /* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- }
- /* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- /* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- HAL_TIM_PeriodElapsedCallback(htim);
- }
- }
- /* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- HAL_TIMEx_BreakCallback(htim);
- }
- }
- /* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- HAL_TIM_TriggerCallback(htim);
- }
- }
- /* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- {
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- HAL_TIMEx_CommutationCallback(htim);
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM Output Compare Channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim : TIM Output Compare handle
- * @param sConfig : TIM Output Compare configuration structure
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 1 in Output Compare */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 2 in Output Compare */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 3 in Output Compare */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- }
- break;
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Input Capture Channels according to the specified
- * parameters in the TIM_IC_InitTypeDef.
- * @param htim : TIM IC handle
- * @param sConfig : TIM Input Capture configuration structure
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
- assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- if (Channel == TIM_CHANNEL_1)
- {
- /* TI1 Configuration */
- TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->ICPrescaler;
- }
- else if (Channel == TIM_CHANNEL_2)
- {
- /* TI2 Configuration */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
- }
- else if (Channel == TIM_CHANNEL_3)
- {
- /* TI3 Configuration */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC3PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
- /* Set the IC3PSC value */
- htim->Instance->CCMR2 |= sConfig->ICPrescaler;
- }
- else
- {
- /* TI4 Configuration */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
-
- /* Reset the IC4PSC Bits */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
- /* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM PWM channels according to the specified
- * parameters in the TIM_OC_InitTypeDef.
- * @param htim : TIM handle
- * @param sConfig : TIM PWM configuration structure
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
- __HAL_LOCK(htim);
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM One Pulse Channels according to the specified
- * parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim : TIM One Pulse handle
- * @param sConfig : TIM One Pulse configuration structure
- * @param OutputChannel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
-{
- TIM_OC_InitTypeDef temp1;
-
- /* Check the parameters */
- assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
- assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
- if(OutputChannel != InputChannel)
- {
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Extract the Ouput compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
- switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_OC2_SetConfig(htim->Instance, &temp1);
- }
- break;
- default:
- break;
- }
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
- {
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
-
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim : TIM handle
- * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc : TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer : The Buffer address.
- * @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((BurstBuffer == 0U) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
- }
- break;
- default:
- break;
- }
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM DMA Burst mode
- * @param htim : TIM handle
- * @param BurstRequestSrc : TIM DMA Request sources to disable
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim : TIM handle
- * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc : TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer : The Buffer address.
- * @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
- assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if((BurstBuffer == 0U) && (BurstLength > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_CC4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_COM:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
- }
- break;
- default:
- break;
- }
-
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stop the DMA burst reading
- * @param htim : TIM handle
- * @param BurstRequestSrc : TIM DMA Request sources to disable.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
- {
- case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
- }
- break;
- case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
- }
- break;
- case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
- }
- break;
- case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
- }
- break;
- case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
- }
- break;
- case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
- }
- break;
- case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
- }
- break;
- default:
- break;
- }
-
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Generate a software event
- * @param htim : TIM handle
- * @param EventSource : specifies the event source.
- * This parameter can be one of the following values:
- * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
- * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
- * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
- * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
- * @retval HAL status
- */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Set the event sources */
- htim->Instance->EGR = EventSource;
-
- /* Change the TIM state */
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Configures the OCRef clear feature
- * @param htim : TIM handle
- * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel : specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- }
- break;
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the clock source to be used
- * @param htim : TIM handle
- * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- htim->Instance->SMCR = tmpsmcr;
-
- switch (sClockSourceConfig->ClockSource)
- {
- case TIM_CLOCKSOURCE_INTERNAL:
- {
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE1:
- {
- /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- /* Select the External clock mode1 and the ETRF trigger */
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLOCKSOURCE_ETRMODE2:
- {
- /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
- /* Check ETR input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- /* Enable the External clock mode2 */
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- }
- break;
-
- case TIM_CLOCKSOURCE_TI1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- }
- break;
- case TIM_CLOCKSOURCE_TI2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI2 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- }
- break;
- case TIM_CLOCKSOURCE_TI1ED:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- /* Check TI1 input conditioning related parameters */
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- }
- break;
- case TIM_CLOCKSOURCE_ITR0:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
- }
- break;
- case TIM_CLOCKSOURCE_ITR1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
- case TIM_CLOCKSOURCE_ITR2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
- }
- break;
-
- default:
- break;
- }
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Selects the signal connected to the TI1 input: direct from CH1_input
- * or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim : TIM handle.
- * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
- * output of a XOR gate.
- * This parameter can be one of the following values:
- * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
- * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
- * pins are connected to the TI1 input (XOR combination)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
-
- /* Reset the TI1 selection */
- tmpcr2 &= ~TIM_CR2_TI1S;
-
- /* Set the the TI1 selection */
- tmpcr2 |= TI1_Selection;
-
- /* Write to TIMxCR2 */
- htim->Instance->CR2 = tmpcr2;
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the TIM in Slave mode
- * @param htim : TIM handle.
- * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Disable Trigger Interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
- }
-
-/**
- * @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim: TIM handle.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
- * contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
- {
- /* Check the parameters */
- assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
- assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
- assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
- /* Enable Trigger Interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
- /* Disable Trigger DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Read the captured value from Capture Compare unit
- * @param htim : TIM handle.
- * @param Channel : TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
- * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
- * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
- * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
- * @retval Captured value
- */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpreg = 0U;
-
- __HAL_LOCK(htim);
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
-
- break;
- }
- case TIM_CHANNEL_2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
-
- break;
- }
-
- case TIM_CHANNEL_3:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
-
- break;
- }
-
- case TIM_CHANNEL_4:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
-
- break;
- }
-
- default:
- break;
- }
-
- __HAL_UNLOCK(htim);
- return tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### TIM Callbacks functions #####
- ==============================================================================
- [..]
- This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
- */
-
-}
-/**
- * @brief Output Compare callback in non blocking mode
- * @param htim : TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
-/**
- * @brief Input Capture callback in non blocking mode
- * @param htim : TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Timer error callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Base state
- * @param htim : TIM Base handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM OC state
- * @param htim : TIM Ouput Compare handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM PWM state
- * @param htim : TIM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Input Capture state
- * @param htim : TIM IC handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode state
- * @param htim : TIM OPM handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM Encoder Mode state
- * @param htim : TIM Encoder handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-
-/**
- * @brief TIM DMA error callback
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_ErrorCallback(htim);
-}
-
-/**
- * @brief TIM DMA Delay Pulse complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_PWM_PulseFinishedCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-/**
- * @brief TIM DMA Capture complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- if (hdma == htim->hdma[TIM_DMA_ID_CC1])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- }
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- }
-
- HAL_TIM_IC_CaptureCallback(htim);
-
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
- * @brief TIM DMA Trigger callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIM_TriggerCallback(htim);
-}
-
-/**
- * @brief Time Base configuration
- * @param TIMx : TIM periheral
- * @param Structure : TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- uint32_t tmpcr1 = 0U;
- tmpcr1 = TIMx->CR1;
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
- }
-
- if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- }
-
- /* Set the auto-reload preload */
- tmpcr1 &= ~TIM_CR1_ARPE;
- tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
- TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
- * @brief Time Ouput Compare 1 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config : The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- tmpcr2 &= ~TIM_CR2_OIS1N;
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config : The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
-
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 3 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config : The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
-
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- }
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- tmpcr2 &= ~TIM_CR2_OIS3N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Time Ouput Compare 4 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config : The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- tmpccmrx &= ~TIM_CCMR2_CC4S;
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
-
- if(IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6);
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-
-/**
- * @brief Time Slave configuration
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sSlaveConfig: The slave configuration structure
- * @retval None
- */
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Reset the Trigger Selection Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source */
- tmpsmcr |= sSlaveConfig->InputTrigger;
-
- /* Reset the slave mode Bits */
- tmpsmcr &= ~TIM_SMCR_SMS;
- /* Set the slave mode */
- tmpsmcr |= sSlaveConfig->SlaveMode;
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
-
- /* Configure the trigger prescaler, filter, and polarity */
- switch (sSlaveConfig->InputTrigger)
- {
- case TIM_TS_ETRF:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- /* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI1F_ED:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = htim->Instance->CCER;
- htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
- }
- break;
-
- case TIM_TS_TI1FP1:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI1 Filter and Polarity */
- TIM_TI1_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_TI2FP2:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
- assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
- /* Configure TI2 Filter and Polarity */
- TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
- }
- break;
-
- case TIM_TS_ITR0:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection : specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
- {
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
- }
- else
- {
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
- }
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4U);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= TIM_ICPolarity;
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection : specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12U);
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4U);
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection : specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC3S;
- tmpccmr2 |= TIM_ICSelection;
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
-
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @param TIM_ICSelection : specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter : Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
-
- /* Select the Input */
- tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8U);
-
- /* Set the filter */
- tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
-
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~TIM_CCER_CC4P;
- tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
-
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer ;
-}
-
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
- * @param InputTriggerSource : The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0 : Internal Trigger 0
- * @arg TIM_TS_ITR1 : Internal Trigger 1
- * @arg TIM_TS_ITR2 : Internal Trigger 2
- * @arg TIM_TS_ITR3 : Internal Trigger 3
- * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
- * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
- * @arg TIM_TS_ETRF : External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
- * @param ExtTRGFilter : External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- uint32_t tmpsmcr = 0U;
-
- tmpsmcr = TIMx->SMCR;
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel : specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @param ChannelState : specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_tim_ex.c b/lib/hal-stm32f1/source/stm32f1xx_hal_tim_ex.c deleted file mode 100644 index 450da6eb..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_tim_ex.c +++ /dev/null @@ -1,1861 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim_ex.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Timer Extended peripheral:
- * + Time Hall Sensor Interface Initialization
- * + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
- * + Time Master and Slave synchronization configuration
- * + Timer remapping capabilities configuration
- @verbatim
- ==============================================================================
- ##### TIMER Extended features #####
- ==============================================================================
- [..]
- The Timer Extended features include:
- (#) Complementary outputs with programmable dead-time for :
- (++) Output Compare
- (++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
- interconnect several timers together.
- (#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
-
- (#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
- (##) TIM pins configuration
- (+++) Enable the clock for the TIM GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
- (#) The external Clock can be configured, if needed (the default clock is the
- internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
- any start function.
-
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
-
- (#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
- (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup TIMEx TIMEx
- * @brief TIM Extended HAL module driver
- * @{
- */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
- * @{
- */
-
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Hall Sensor functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
- (+) De-initialize TIM HAL Sensor.
- (+) Start the Hall Sensor Interface.
- (+) Stop the Hall Sensor Interface.
- (+) Start the Hall Sensor Interface and enable interrupts.
- (+) Stop the Hall Sensor Interface and disable interrupts.
- (+) Start the Hall Sensor Interface and enable DMA transfers.
- (+) Stop the Hall Sensor Interface and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim : TIM Encoder Interface handle
- * @param sConfig : TIM Hall Sensor configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
-{
- TIM_OC_InitTypeDef OC_Config;
-
- /* Check the TIM handle allocation */
- if(htim == NULL)
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-
- if(htim->State == HAL_TIM_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
- }
-
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
- /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
- TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Set the IC1PSC value */
- htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
- /* Enable the Hall sensor interface (XOR function of the three inputs) */
- htim->Instance->CR2 |= TIM_CR2_TI1S;
-
- /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
- /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
- OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
- OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
- OC_Config.OCMode = TIM_OCMODE_PWM2;
- OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
- TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
- /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
- /* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Disable the TIM Peripheral Clock */
- __HAL_TIM_DISABLE(htim);
-
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
- HAL_TIMEx_HallSensor_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the TIM Hall Sensor MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface.
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall sensor Interface.
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM Hall Sensor handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Enable the capture compare Interrupts 1 event */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
- /* Disable the capture compare Interrupts event */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM Hall Sensor handle
- * @param pData : The destination Buffer address.
- * @param Length : The length of data to be transferred from TIM peripheral to memory.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- /* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
- /* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the capture compare 1 Interrupt */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
-{
- /* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
- /* Disable the capture compare Interrupts 1 event */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary Output Compare/PWM.
- (+) Stop the Complementary Output Compare/PWM.
- (+) Start the Complementary Output Compare/PWM and enable interrupts.
- (+) Stop the Complementary Output Compare/PWM and disable interrupts.
- (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
- (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation on the complementary
- * output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData : The source Buffer address.
- * @param Length : The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
- * on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Output Compare DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary PWM.
- (+) Stop the Complementary PWM.
- (+) Start the Complementary PWM and enable interrupts.
- (+) Stop the Complementary PWM and disable interrupts.
- (+) Start the Complementary PWM and enable DMA transfers.
- (+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Enable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the PWM signal generation in interrupt mode on the
- * complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
- {
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
- }
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
- * complementary output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData : The source Buffer address.
- * @param Length : The length of data to be transferred from memory to TIM peripheral
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- if((htim->State == HAL_TIM_STATE_BUSY))
- {
- return HAL_BUSY;
- }
- else if((htim->State == HAL_TIM_STATE_READY))
- {
- if(((uint32_t)pData == 0U) && (Length > 0U))
- {
- return HAL_ERROR;
- }
- else
- {
- htim->State = HAL_TIM_STATE_BUSY;
- }
- }
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
- /* Enable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
- /* Enable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
- * output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- /* Disable the TIM Capture/Compare 1 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
- break;
-
- case TIM_CHANNEL_2:
- {
- /* Disable the TIM Capture/Compare 2 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
- break;
-
- case TIM_CHANNEL_3:
- {
- /* Disable the TIM Capture/Compare 3 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
- }
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
-
- default:
- break;
- }
-
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
- ==============================================================================
- ##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
- * output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
- * output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Enable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- /* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Return function status */
- return HAL_OK;
- }
-
-/**
- * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
- * complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
- /* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
- /* Disable the TIM Capture/Compare 2 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
- /* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master synchronization.
-
-@endverbatim
- * @{
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/**
- * @brief Configure the TIM commutation event sequence.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim : TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with interrupt.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim : TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation Interrupt Request */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configure the TIM commutation event sequence with DMA.
- * @note: this function is mandatory to use the commutation event in order to
- * update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
- * the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim : TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
- * This parameter can be one of the following values:
- * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
- * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
- assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
- __HAL_LOCK(htim);
-
- if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
- (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
- /* Select the Input trigger */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= InputTrigger;
- }
-
- /* Select the Capture Compare preload feature */
- htim->Instance->CR2 |= TIM_CR2_CCPC;
- /* Select the Commutation event source */
- htim->Instance->CR2 &= ~TIM_CR2_CCUS;
- htim->Instance->CR2 |= CommutationSource;
-
- /* Enable the Commutation DMA Request */
- /* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-
- /* Enable the Commutation DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param htim : TIM handle
- * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
-{
- uint32_t tmpbdtr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
- assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
- assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
- assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
- assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
- assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
- assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
- /* Process Locked */
- __HAL_LOCK(htim);
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
-
- /* Set TIMx_BDTR */
- htim->Instance->BDTR = tmpbdtr;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/**
- * @brief Configures the TIM in master mode.
- * @param htim : TIM handle.
- * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
-{
- /* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- /* Reset the MMS Bits */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
- /* Select the TRGO source */
- htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
-
- /* Reset the MSM Bit */
- htim->Instance->SMCR &= ~TIM_SMCR_MSM;
- /* Set or Reset the MSM Bit */
- htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
- * @brief Extension Callbacks functions
- *
-@verbatim
- ==============================================================================
- ##### Extension Callbacks functions #####
- ==============================================================================
- [..]
- This section provides Extension TIM callback functions:
- (+) Timer Commutation callback
- (+) Timer Break callback
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Hall commutation changed callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Hall Break detection callback in non blocking mode
- * @param htim : TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma : pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIMEx_CommutationCallback(htim);
-}
-
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
- * @brief Extension Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Extension Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Return the TIM Hall Sensor interface state
- * @param htim : TIM Hall Sensor handle
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/** @addtogroup TIMEx_Private_Functions
- * @{
- */
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
- * @param Channel : specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
- * @retval None
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-{
- uint32_t tmp = 0U;
-
- tmp = TIM_CCER_CC1NE << Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
-}
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_rtc_alarm_template.c b/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_rtc_alarm_template.c deleted file mode 100644 index 9c394f0c..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_rtc_alarm_template.c +++ /dev/null @@ -1,307 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_timebase_rtc_alarm_template.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief HAL time base based on the hardware RTC_ALARM.
- *
- * This file override the native HAL time base functions (defined as weak)
- * to use the RTC ALARM for time base generation:
- * + Intializes the RTC peripheral to increment the seconds registers each 1ms
- * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
- * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
- * + HSE (default), LSE or LSI can be selected as RTC clock source
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This file must be copied to the application folder and modified as follows:
- (#) Rename it to 'stm32f1xx_hal_timebase_rtc_alarm.c'
- (#) Add this file and the RTC HAL drivers to your project and uncomment
- HAL_RTC_MODULE_ENABLED define in stm32f1xx_hal_conf.h
-
- [..]
- (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
- The wake up capability of the RTC may be intrusive in case of prior low power mode
- configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
- (@) The stm32f1xx_hal_timebase_tim use is recommended for the Applications/Examples
- requiring low power modes
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Uncomment the line below to select the appropriate RTC Clock source for your application:
- + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
- + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
- precision.
- + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
- precision.
- */
-#define RTC_CLOCK_SOURCE_HSE
-/* #define RTC_CLOCK_SOURCE_LSE */
-/* #define RTC_CLOCK_SOURCE_LSI */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-RTC_HandleTypeDef hRTC_Handle;
-/* Private function prototypes -----------------------------------------------*/
-void RTC_Alarm_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief This function configures the RTC_ALARMA as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
- __IO uint32_t counter = 0U;
-
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
-#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
-#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV128;
-#else
-#error Please select the RTC Clock source
-#endif /* RTC_CLOCK_SOURCE_LSE */
-
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
- {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
- {
- /* Enable RTC Clock */
- __HAL_RCC_RTC_ENABLE();
-
- hRTC_Handle.Instance = RTC;
- /* Configure RTC time base to 10Khz */
- hRTC_Handle.Init.AsynchPrediv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC) / 10000) - 1;
- hRTC_Handle.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
- HAL_RTC_Init(&hRTC_Handle);
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
-
- counter = 0U;
- /* Wait till RTC ALRAF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF) != RESET)
- {
- if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
-
- /* Set RTC COUNTER MSB word */
- hRTC_Handle.Instance->ALRH = 0x00U;
- /* Set RTC COUNTER LSB word */
- hRTC_Handle.Instance->ALRL = 0x09U;
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Clear Second and overflow flags */
- CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
-
- /* Set RTC COUNTER MSB word */
- hRTC_Handle.Instance->CNTH = 0x00U;
- /* Set RTC COUNTER LSB word */
- hRTC_Handle.Instance->CNTL = 0x00U;
-
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- counter = 0U;
- while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
- {
- if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
-
- HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
- return HAL_OK;
- }
- }
- return HAL_ERROR;
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note Disable the tick increment by disabling RTC ALARM interrupt.
- * @param None
- * @retval None
- */
-void HAL_SuspendTick(void)
-{
- /* Disable RTC ALARM update Interrupt */
- __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note Enable the tick increment by Enabling RTC ALARM interrupt.
- * @param None
- * @retval None
- */
-void HAL_ResumeTick(void)
-{
- __IO uint32_t counter = 0U;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
-
- /* Set RTC COUNTER MSB word */
- hRTC_Handle.Instance->CNTH = 0x00U;
- /* Set RTC COUNTER LSB word */
- hRTC_Handle.Instance->CNTL = 0x00U;
-
- /* Clear Second and overflow flags */
- CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW | RTC_FLAG_ALRAF));
-
- /* Enable RTC ALARM Update interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
- {
- if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
- {
- break;
- }
- }
-}
-
-/**
- * @brief ALARM A Event Callback in non blocking mode
- * @note This function is called when RTC_ALARM interrupt took place, inside
- * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
- * a global variable "uwTick" used as application time base.
- * @param hrtc : RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- __IO uint32_t counter = 0U;
-
- HAL_IncTick();
-
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set RTC COUNTER MSB word */
- WRITE_REG(hrtc->Instance->CNTH, 0x00U);
- /* Set RTC COUNTER LSB word */
- WRITE_REG(hrtc->Instance->CNTL, 0x00U);
-
- /* Clear Second and overflow flags */
- CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
- {
- if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
- {
- break;
- }
- }
-}
-
-/**
- * @brief This function handles RTC ALARM interrupt request.
- * @retval None
- */
-void RTC_Alarm_IRQHandler(void)
-{
- HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_tim_template.c b/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_tim_template.c deleted file mode 100644 index ac0e7574..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_timebase_tim_template.c +++ /dev/null @@ -1,184 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_timebase_tim_template.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief HAL time base based on the hardware TIM Template.
- *
- * This file overrides the native HAL time base functions (defined as weak)
- * the TIM time base:
- * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
- * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL_TimeBase_TIM
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_HandleTypeDef TimHandle;
-/* Private function prototypes -----------------------------------------------*/
-void TIM2_IRQHandler(void);
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief This function configures the TIM2 as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
-{
- RCC_ClkInitTypeDef clkconfig;
- uint32_t uwTimclock, uwAPB1Prescaler = 0U;
- uint32_t uwPrescalerValue = 0U;
- uint32_t pFLatency;
-
- /*Configure the TIM2 IRQ priority */
- HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0U);
-
- /* Enable the TIM2 global Interrupt */
- HAL_NVIC_EnableIRQ(TIM2_IRQn);
-
- /* Enable TIM2 clock */
- __HAL_RCC_TIM2_CLK_ENABLE();
-
- /* Get clock configuration */
- HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
- /* Get APB1 prescaler */
- uwAPB1Prescaler = clkconfig.APB1CLKDivider;
-
- /* Compute TIM2 clock */
- if (uwAPB1Prescaler == RCC_HCLK_DIV1)
- {
- uwTimclock = HAL_RCC_GetPCLK1Freq();
- }
- else
- {
- uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
- }
-
- /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
- uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
-
- /* Initialize TIM2 */
- TimHandle.Instance = TIM2;
-
- /* Initialize TIMx peripheral as follow:
- + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
- + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
- + ClockDivision = 0
- + Counter direction = Up
- */
- TimHandle.Init.Period = (1000000U / 1000U) - 1U;
- TimHandle.Init.Prescaler = uwPrescalerValue;
- TimHandle.Init.ClockDivision = 0U;
- TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
- {
- /* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
- }
-
- /* Return function status */
- return HAL_ERROR;
-}
-
-/**
- * @brief Suspend Tick increment.
- * @note Disable the tick increment by disabling TIM2 update interrupt.
- * @retval None
- */
-void HAL_SuspendTick(void)
-{
- /* Disable TIM2 update Interrupt */
- __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
- * @brief Resume Tick increment.
- * @note Enable the tick increment by Enabling TIM2 update interrupt.
- * @retval None
- */
-void HAL_ResumeTick(void)
-{
- /* Enable TIM2 Update interrupt */
- __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
-}
-
-/**
- * @brief Period elapsed callback in non blocking mode
- * @note This function is called when TIM2 interrupt took place, inside
- * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
- * a global variable "uwTick" used as application time base.
- * @param htim : TIM handle
- * @retval None
- */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
- HAL_IncTick();
-}
-
-/**
- * @brief This function handles TIM interrupt request.
- * @retval None
- */
-void TIM2_IRQHandler(void)
-{
- HAL_TIM_IRQHandler(&TimHandle);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_uart.c b/lib/hal-stm32f1/source/stm32f1xx_hal_uart.c deleted file mode 100644 index 03162e0a..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_uart.c +++ /dev/null @@ -1,2558 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_uart.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief UART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure.
- (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) UART pins configuration:
- (+++) Enable the clock for the UART GPIOs.
- (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
- (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
- and HAL_UART_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
- and HAL_UART_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required
- Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Tx/Rx channel.
- (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the huart Init structure.
-
- (#) For the UART asynchronous mode, initialize the UART registers by calling
- the HAL_UART_Init() API.
-
- (#) For the UART Half duplex mode, initialize the UART registers by calling
- the HAL_HalfDuplex_Init() API.
-
- (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-
- (#) For the Multi-Processor mode, initialize the UART registers by calling
- the HAL_MultiProcessor_Init() API.
-
- [..]
- (@) The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
- and receive process.
-
- [..]
- (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
- low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
- HAL_UART_MspInit() API.
-
- [..]
- Three operation modes are available within this driver:
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_UART_DMAPause()
- (+) Resume the DMA Transfer using HAL_UART_DMAResume()
- (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
- *** UART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in UART HAL driver.
-
- (+) __HAL_UART_ENABLE: Enable the UART peripheral
- (+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
- (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
- (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-
- [..]
- (@) You can refer to the UART HAL driver header file for more useful macros
- @endverbatim
- [..]
- (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup UART UART
- * @brief HAL UART module driver
- * @{
- */
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup UART_Private_Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions
- * @{
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void UART_SetConfig (UART_HandleTypeDef *huart);
-/**
- * @}
- */
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in asynchronous mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible UART frame formats.
- (++) Hardware flow control
- (++) Receiver/transmitter modes
- (++) Over Sampling Method
- [..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
- follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
- configuration procedures (details for the procedures are available in reference manuals
- (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the UART mode according to the specified parameters in
- * the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
- {
- /* The hardware flow control is available only for USART1, USART2, USART3 */
- assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- }
- else
- {
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-#if defined(USART_CR1_OVER8)
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-#endif /* USART_CR1_OVER8 */
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- UART_SetConfig(huart);
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* Enable the peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Initialize the UART state */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-#if defined(USART_CR1_OVER8)
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-#endif /* USART_CR1_OVER8 */
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- UART_SetConfig(huart);
-
- /* In half-duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
- /* Enable the peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Initialize the UART state*/
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param BreakDetectLength: Specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
- * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the LIN UART instance */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Check the Break detection length parameter */
- assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
- assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
-#if defined(USART_CR1_OVER8)
- assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
-#endif /* USART_CR1_OVER8 */
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- UART_SetConfig(huart);
-
- /* In LIN mode, the following bits must be kept cleared:
- - CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
- /* Set the USART LIN Break detection length. */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
- /* Enable the peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Initialize the UART state*/
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the Multi-Processor mode according to the specified
- * parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param Address: USART address
- * @param WakeUpMethod: specifies the USART wake-up method.
- * This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
- * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check UART instance capabilities */
- assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));
-
- /* Check the Address & wake up method parameters */
- assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
- assert_param(IS_UART_ADDRESS(Address));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-#if defined(USART_CR1_OVER8)
- assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-#endif /* USART_CR1_OVER8 */
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- UART_SetConfig(huart);
-
- /* In Multi-Processor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register */
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* Set the USART address node */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address);
-
- /* Set the wake up method by setting the WAKE bit in the CR1 register */
- MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
- /* Enable the peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* Initialize the UART state */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the UART peripheral.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_UART_MspDeInit(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
-
- /* Process Unlock */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief UART MSP Init.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief UART MSP DeInit.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the UART asynchronous
- and Half duplex data transfers.
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non blocking mode: The communication is performed using Interrupts
- or DMA, these APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or receive process.
- The HAL_UART_ErrorCallback() user callback will be executed when
- a communication error is detected.
-
- (#) Blocking mode APIs are:
- (++) HAL_UART_Transmit()
- (++) HAL_UART_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are:
- (++) HAL_UART_Transmit_IT()
- (++) HAL_UART_Receive_IT()
- (++) HAL_UART_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are:
- (++) HAL_UART_Transmit_DMA()
- (++) HAL_UART_Receive_DMA()
- (++) HAL_UART_DMAPause()
- (++) HAL_UART_DMAResume()
- (++) HAL_UART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
- (++) HAL_UART_TxHalfCpltCallback()
- (++) HAL_UART_TxCpltCallback()
- (++) HAL_UART_RxHalfCpltCallback()
- (++) HAL_UART_RxCpltCallback()
- (++) HAL_UART_ErrorCallback()
-
- [..]
- (@) In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
- can't be useful.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends an amount of data in blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
- while(huart->TxXferCount > 0U)
- {
- huart->TxXferCount--;
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
- {
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pData;
- huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- pData +=2U;
- }
- else
- {
- pData +=1U;
- }
- }
- else
- {
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
- }
- }
-
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(huart->RxXferCount > 0U)
- {
- huart->RxXferCount--;
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
- {
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*)pData;
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- pData +=2U;
- }
- else
- {
- *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
- pData +=1U;
- }
-
- }
- else
- {
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
- }
-
- }
- }
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Transmit data register empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
- /* Enable the UART Data Register not empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_BUSY_TX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the UART transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
-
- /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
- __HAL_UART_CLEAR_OREFLAG(huart);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
- uint32_t dmarequest = 0x00U;
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
- {
- /* Disable the UART DMA Tx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
-
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
- {
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
- /* Process Locked */
- __HAL_LOCK(huart);
-
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- /* Enable the UART DMA Tx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- }
-
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_UART_CLEAR_OREFLAG(huart);
-
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the UART DMA Rx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
- uint32_t dmarequest = 0x00U;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
- */
-
- /* Stop UART DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
- {
- HAL_DMA_Abort(huart->hdmatx);
- }
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- HAL_DMA_Abort(huart->hdmarx);
- }
- UART_EndRxTransfer(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0x00U;
- huart->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Restore huart->RxState and huart->gState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmatx);
- }
- }
-
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0x00U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (blocking mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(huart->hdmarx);
- }
- }
-
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0x00U;
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfers (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
- uint32_t AbortCplt = 0x01U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(huart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
- }
- else
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(huart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
- }
- else
- {
- huart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at UART level */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
- {
- /* UART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- huart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
- {
- /* UART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- huart->hdmarx->XferAbortCallback = NULL;
- AbortCplt = 0x01U;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
- {
- /* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0x00U;
- huart->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Transmit transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
- {
- /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
- huart->hdmatx->XferAbortCallback(huart->hdmatx);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0x00U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Tx transfer counter */
- huart->TxXferCount = 0x00U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing Receive transfer (Interrupt mode).
- * @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0x00U;
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
- }
- else
- {
- /* Reset Rx transfer counter */
- huart->RxXferCount = 0x00U;
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles UART interrupt request.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- uint32_t isrflags = READ_REG(huart->Instance->SR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- uint32_t errorflags = 0x00U;
- uint32_t dmarequest = 0x00U;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
- {
- /* UART in mode Receiver -------------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- UART_Receive_IT(huart);
- return;
- }
- }
-
- /* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* UART parity error interrupt occurred ----------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART noise error interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* UART frame error interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART Over-Run interrupt occurred --------------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* UART in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- UART_Receive_IT(huart);
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
-
- /* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_UART_ErrorCallback(huart);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_UART_ErrorCallback(huart);
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- }
- }
- return;
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- UART_Transmit_IT(huart);
- return;
- }
-
- /* UART in mode Transmitter end --------------------------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- UART_EndTransmit_IT(huart);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief UART error callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortCpltCallback can be implemented in the user file.
- */
-}
-/**
- * @brief UART Abort Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @brief UART Abort Receive Complete callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control the UART:
- (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
- (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
- (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
- (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
- (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits break characters.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Send break characters */
- SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enters the UART in mute mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Exits the UART mute mode: wake up software.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
- uint32_t tmpreg = 0x00U;
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = huart->Instance->CR1;
-
- /* Clear TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
- /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- tmpreg |= (uint32_t)USART_CR1_TE;
-
- /* Write to USART CR1 */
- WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
- uint32_t tmpreg = 0x00U;
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = huart->Instance->CR1;
-
- /* Clear TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
- /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- tmpreg |= (uint32_t)USART_CR1_RE;
-
- /* Write to USART CR1 */
- WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief UART State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of
- UART communication process, return Peripheral Errors occurred during communication
- process
- (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
- (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the UART state.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL state
- */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = huart->gState;
- temp2 = huart->RxState;
-
- return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the UART error code
- * @param huart : pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
- * @retval UART Error Code
- */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
- return huart->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief DMA UART transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode*/
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- huart->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- }
- /* DMA Circular mode */
- else
- {
- HAL_UART_TxCpltCallback(huart);
- }
-}
-
-/**
- * @brief DMA UART transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode*/
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- {
- huart->RxXferCount = 0U;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- }
- HAL_UART_RxCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- HAL_UART_RxHalfCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
- uint32_t dmarequest = 0x00U;
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Stop UART DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
- {
- huart->TxXferCount = 0U;
- UART_EndTxTransfer(huart);
- }
-
- /* Stop UART DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
- {
- huart->RxXferCount = 0U;
- UART_EndRxTransfer(huart);
- }
-
- huart->ErrorCode |= HAL_UART_ERROR_DMA;
- HAL_UART_ErrorCallback(huart);
-}
-
-/**
- * @brief This function handles UART Communication Timeout.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param Flag: specifies the UART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
- * @param huart: UART handle.
- * @retval None
- */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-}
-
-/**
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart: UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-}
-
-/**
- * @brief DMA UART communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0x00U;
- huart->TxXferCount = 0x00U;
-
- HAL_UART_ErrorCallback(huart);
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmarx != NULL)
- {
- if(huart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0x00U;
- huart->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(huart->hdmatx != NULL)
- {
- if(huart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- huart->TxXferCount = 0x00U;
- huart->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Restore huart->gState and huart->RxState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->TxXferCount = 0x00U;
-
- /* Restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortTransmitCpltCallback(huart);
-}
-
-/**
- * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
- * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- huart->RxXferCount = 0x00U;
-
- /* Restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_UART_AbortReceiveCpltCallback(huart);
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
- {
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- huart->pTxBuffPtr += 2U;
- }
- else
- {
- huart->pTxBuffPtr += 1U;
- }
- }
- else
- {
- huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
- }
-
- if(--huart->TxXferCount == 0U)
- {
- /* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
- /* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
-
- /* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
- {
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) huart->pRxBuffPtr;
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- huart->pRxBuffPtr += 2U;
- }
- else
- {
- *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
- huart->pRxBuffPtr += 1U;
- }
- }
- else
- {
- if(huart->Init.Parity == UART_PARITY_NONE)
- {
- *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
- }
- }
-
- if(--huart->RxXferCount == 0U)
- {
- /* Disable the IRDA Data Register not empty Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
-
- HAL_UART_RxCpltCallback(huart);
-
- return HAL_OK;
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configures the UART peripheral.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
- uint32_t tmpreg = 0x00U;
-
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
-
- /*------- UART-associated USART registers setting : CR2 Configuration ------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*------- UART-associated USART registers setting : CR1 Configuration ------*/
- /* Configure the UART Word Length, Parity and mode:
- Set the M bits according to huart->Init.WordLength value
- Set PCE and PS bits according to huart->Init.Parity value
- Set TE and RE bits according to huart->Init.Mode value
- Set OVER8 bit according to huart->Init.OverSampling value */
-
-#if defined(USART_CR1_OVER8)
- tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
- MODIFY_REG(huart->Instance->CR1,
- (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
- tmpreg);
-#else
- tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
- MODIFY_REG(huart->Instance->CR1,
- (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
- tmpreg);
-#endif /* USART_CR1_OVER8 */
-
- /*------- UART-associated USART registers setting : CR3 Configuration ------*/
- /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
- MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
-
-#if defined(USART_CR1_OVER8)
- /* Check the Over Sampling */
- if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- /*-------------------------- USART BRR Configuration ---------------------*/
- if(huart->Instance == USART1)
- {
- huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
- }
- else
- {
- huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
- }
- }
- else
- {
- /*-------------------------- USART BRR Configuration ---------------------*/
- if(huart->Instance == USART1)
- {
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
- }
- else
- {
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
- }
- }
-#else
- /*-------------------------- USART BRR Configuration ---------------------*/
- if(huart->Instance == USART1)
- {
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
- }
- else
- {
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
- }
-#endif /* USART_CR1_OVER8 */
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_usart.c b/lib/hal-stm32f1/source/stm32f1xx_hal_usart.c deleted file mode 100644 index 0cd862ba..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_usart.c +++ /dev/null @@ -1,2310 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_usart.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The USART HAL driver can be used as follows:
-
- (#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
- (##) Enable the USARTx interface clock.
- (##) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
- (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Tx/Rx channel.
- (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
-
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the husart Init structure.
-
- (#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_USART_MspInit(&husart) API.
-
- -@@- The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_USART_DMAPause()
- (+) Resume the DMA Transfer using HAL_USART_DMAResume()
- (+) Stop the DMA Transfer using HAL_USART_DMAStop()
-
- *** USART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in USART HAL driver.
-
- (+) __HAL_USART_ENABLE: Enable the USART peripheral
- (+) __HAL_USART_DISABLE: Disable the USART peripheral
- (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
- (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
- (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
- (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-
- [..]
- (@) You can refer to the USART HAL driver header file for more useful macros
-
- @endverbatim
- [..]
- (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
- * @{
- */
-#ifdef HAL_USART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup USART_Private_Constants
- * @{
- */
-#define DUMMY_DATA 0xFFFFU
-#define USART_TIMEOUT_VALUE 22000U
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup USART_Private_Functions
- * @{
- */
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-static void USART_SetConfig (USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Stop Bit
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- please refer to Reference manual for possible USART frame formats.
- (++) USART polarity
- (++) USART phase
- (++) USART LastBit
- (++) Receiver/transmitter modes
-
- [..]
- The HAL_USART_Init() function follows the USART synchronous configuration
- procedure (details for the procedure are available in reference manuals
- (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the USART mode according to the specified
- * parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- if(husart->State == HAL_USART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- husart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_USART_MspInit(husart);
- }
-
- husart->State = HAL_USART_STATE_BUSY;
-
- /* Set the USART Communication parameters */
- USART_SetConfig(husart);
-
- /* In USART mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register */
- CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
- /* Enable the Peripheral */
- __HAL_USART_ENABLE(husart);
-
- /* Initialize the USART state */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State= HAL_USART_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the USART peripheral.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
- /* Check the USART handle allocation */
- if(husart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_USART_INSTANCE(husart->Instance));
-
- husart->State = HAL_USART_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_USART_MspDeInit(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief USART MSP Init.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @brief USART MSP DeInit.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART synchronous
- data transfers.
-
- [..]
- The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
-
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
- user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback() user callback will be executed when a communication
- error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_USART_Transmit() in simplex mode
- (++) HAL_USART_Receive() in full duplex receive only
- (++) HAL_USART_TransmitReceive() in full duplex mode
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_USART_Transmit_IT()in simplex mode
- (++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT() in full duplex mode
- (++) HAL_USART_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_USART_Transmit_DMA()in simplex mode
- (++) HAL_USART_Receive_DMA() in full duplex receive only
- (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
- (++) HAL_USART_DMAPause()
- (++) HAL_USART_DMAResume()
- (++) HAL_USART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_USART_TxHalfCpltCallback()
- (++) HAL_USART_TxCpltCallback()
- (++) HAL_USART_RxHalfCpltCallback()
- (++) HAL_USART_RxCpltCallback()
- (++) HAL_USART_ErrorCallback()
- (++) HAL_USART_TxRxCpltCallback()
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Simplex Send an amount of data in blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- /* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pTxData;
- WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- pTxData += 2U;
- }
- else
- {
- pTxData += 1U;
- }
- }
- else
- {
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF));
- }
- }
-
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
- /* Check the remain data to be received */
- while(husart->RxXferCount > 0U)
- {
- husart->RxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Send dummy byte in order to generate clock */
- WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pRxData ;
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- pRxData +=2U;
- }
- else
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- pRxData +=1U;
- }
- }
- else
- {
- /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Send Dummy Byte in order to generate clock */
- WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
-
- /* Wait until RXNE flag is set to receive the byte */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- /* Receive data */
- *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- /* Receive data */
- *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
- }
-
- }
- }
-
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment */
- tickstart = HAL_GetTick();
-
- husart->RxXferSize = Size;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
- husart->RxXferCount = Size;
-
- /* Check the remain data to be received */
- while(husart->TxXferCount > 0U)
- {
- husart->TxXferCount--;
- husart->RxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- /* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pTxData;
- WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- pTxData += 2U;
- }
- else
- {
- pTxData += 1U;
- }
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- tmp = (uint16_t*) pRxData ;
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- pRxData += 2U;
- }
- else
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- pRxData += 1U;
- }
- }
- else
- {
- /* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF));
-
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- /* Receive data */
- *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- /* Receive data */
- *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
- }
- }
- }
-
- husart->State = HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- * @note The USART errors are not managed to avoid the overrun error.
- */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
- are not managed by the USART transmit process to avoid the overrun interrupt
- when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
- to benefit for the frame error and noise interrupts the USART mode should be
- configured only for transmit "USART_MODE_TX"
- The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
- Noise error interrupt */
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Data Register not empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
- /* Enable the USART Parity Error Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Send dummy byte in order to generate the clock for the slave to send data */
- WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->RxXferCount = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Data Register not empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
- /* Enable the USART Parity Error Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
- husart->TxXferCount = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* Set the USART DMA transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Set the DMA abort callback */
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pRxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Set the DMA abort callback */
- husart->hdmarx->XferAbortCallback = NULL;
-
- /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- husart->hdmatx->XferHalfCpltCallback = NULL;
- husart->hdmatx->XferCpltCallback = NULL;
-
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Set the DMA AbortCpltCallback */
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
-
- /* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
- this mode isn't a simplex receive mode but a full-duplex receive one */
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
- /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
- __HAL_USART_CLEAR_OREFLAG(husart);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be received
- * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- /* Process Locked */
- __HAL_LOCK(husart);
-
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
-
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
- /* Set the USART DMA Tx transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
- /* Set the USART DMA Tx transfer error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
-
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
-
- /* Set the DMA abort callback */
- husart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
-
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-
- /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
- __HAL_USART_CLEAR_OREFLAG(husart);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- /* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Resumes the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
- /* Process Locked */
- __HAL_LOCK(husart);
-
- /* Enable the USART DMA Tx request */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stops the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
- uint32_t dmarequest = 0x00U;
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
- */
-
- /* Stop USART DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
- if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
- {
- USART_EndTxTransfer(husart);
-
- /* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
- {
- HAL_DMA_Abort(husart->hdmatx);
- }
-
- /* Disable the USART Tx DMA request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- }
-
- /* Stop USART DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
- {
- USART_EndRxTransfer(husart);
-
- /* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
- {
- HAL_DMA_Abort(husart->hdmarx);
- }
-
- /* Disable the USART Rx DMA request */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfer (blocking mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
- * as described by TransferType parameter) started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
- * - Set handle State to READY
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
-{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmatx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmatx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmatx);
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART DMA Abort callback to Null.
- No call back execution at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = NULL;
-
- HAL_DMA_Abort(husart->hdmarx);
- }
- }
-
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0x00U;
- husart->RxXferCount = 0x00U;
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Reset Handle ErrorCode to No Error */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- return HAL_OK;
-}
-
-/**
- * @brief Abort ongoing transfer (Interrupt mode).
- * @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
- * as described by TransferType parameter) started in Interrupt or DMA mode.
- * This procedure performs following operations :
- * - Disable PPP Interrupts (depending of transfer direction)
- * - Disable the DMA transfer in the peripheral register (if enabled)
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
- * - Set handle State to READY
- * - At abort completion, call user abort complete callback
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
- * considered as completed only when user abort complete callback is executed (not when exiting function).
- * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
-{
- uint32_t AbortCplt = 0x01U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
- /* DMA Tx Handle is valid */
- if(husart->hdmatx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
- }
- else
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- }
- /* DMA Rx Handle is valid */
- if(husart->hdmarx != NULL)
- {
- /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
- Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
- }
- else
- {
- husart->hdmarx->XferAbortCallback = NULL;
- }
- }
-
- /* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
- {
- /* Disable DMA Tx at USART level */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmatx != NULL)
- {
- /* USART Tx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
- {
- husart->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* Disable the USART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmarx != NULL)
- {
- /* USART Rx DMA Abort callback has already been initialised :
- will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- husart->hdmarx->XferAbortCallback = NULL;
- AbortCplt = 0x01U;
- }
- else
- {
- AbortCplt = 0x00U;
- }
- }
- }
-
- /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
- {
- /* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0x00U;
- husart->RxXferCount = 0x00U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* As no DMA to be aborted, call directly user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles USART interrupt request.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
- uint32_t isrflags = READ_REG(husart->Instance->SR);
- uint32_t cr1its = READ_REG(husart->Instance->CR1);
- uint32_t cr3its = READ_REG(husart->Instance->CR3);
- uint32_t errorflags = 0x00U;
- uint32_t dmarequest = 0x00U;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
- {
- /* USART in mode Receiver -------------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
- }
- /* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
- {
- /* USART parity error interrupt occurred ----------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_PE;
- }
-
- /* USART noise error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_NE;
- }
-
- /* USART frame error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_FE;
- }
-
- /* USART Over-Run interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_ORE;
- }
-
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
- {
- /* USART in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- }
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
- {
- /* Set the USART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- USART_EndRxTransfer(husart);
-
- /* Disable the USART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
- {
- /* Set the USART DMA Abort callback :
- will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
- husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- husart->hdmarx->XferAbortCallback(husart->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_USART_ErrorCallback(husart);
- husart->ErrorCode = HAL_USART_ERROR_NONE;
- }
- }
- return;
- }
-
- /* USART in mode Transmitter -----------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- USART_Transmit_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
- }
- return;
- }
-
- /* USART in mode Transmitter (transmission end) ----------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- USART_EndTransmit_IT(husart);
- return;
- }
-}
-
-/**
- * @brief Tx Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxRxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USART error callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief USART Abort Complete callback.
- * @param husart USART handle.
- * @retval None
- */
-__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(husart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_AbortCpltCallback can be implemented in the user file.
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief USART State and Errors functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of
- USART communication
- process, return Peripheral Errors occurred during communication process
- (+) HAL_USART_GetState() API can be helpful to check in run-time the state
- of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occurred during
- communication.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the USART state.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL state
- */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
- return husart->State;
-}
-
-/**
- * @brief Return the USART error code
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART Error Code
- */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
- return husart->ErrorCode;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup USART_Private_Functions USART Private Functions
- * @brief USART Private functions
- * @{
- */
-/**
- * @brief DMA USART transmit process complete callback.
- * @param hdma: DMA handle
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode */
- if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
- {
- husart->TxXferCount = 0U;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
- }
- }
- /* DMA Circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- HAL_USART_TxCpltCallback(husart);
- }
- }
-}
-
-/**
- * @brief DMA USART transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_USART_TxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* DMA Normal mode */
- if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
- {
- husart->RxXferCount = 0x00U;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- /* Disable the DMA transfer for the Transmit/Receiver requests by setting the DMAT/DMAR bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- husart->State= HAL_USART_STATE_READY;
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
-
- husart->State= HAL_USART_STATE_READY;
- HAL_USART_TxRxCpltCallback(husart);
- }
- }
- /* DMA circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- }
-}
-
-/**
- * @brief DMA USART receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_USART_RxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART communication error callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
- uint32_t dmarequest = 0x00U;
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- husart->RxXferCount = 0x00U;
- husart->TxXferCount = 0x00U;
-
- /* Stop USART DMA Tx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
- if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
- {
- USART_EndTxTransfer(husart);
- }
-
- /* Stop USART DMA Rx request if ongoing */
- dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
- {
- USART_EndRxTransfer(husart);
- }
-
- husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief This function handles USART Communication Timeout.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param Flag: specifies the USART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Tickstart: Tick start value.
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
- * @param husart: USART handle.
- * @retval None
- */
-static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-}
-
-/**
- * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
- * @param husart: USART handle.
- * @retval None
- */
-static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
-{
- /* Disable RXNE, PE and ERR interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-}
-
-/**
- * @brief DMA USART communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- husart->RxXferCount = 0x00U;
- husart->TxXferCount = 0x00U;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
- * @brief DMA USART Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- husart->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmarx != NULL)
- {
- if(husart->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0x00U;
- husart->RxXferCount = 0x00U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
- * @retval None
- */
-static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- husart->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(husart->hdmatx != NULL)
- {
- if(husart->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- husart->TxXferCount = 0x00U;
- husart->RxXferCount = 0x00U;
-
- /* Reset errorCode */
- husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_USART_AbortCpltCallback(husart);
-}
-
-/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- * @note The USART errors are not managed to avoid the overrun error.
- */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->pTxBuffPtr += 1U;
- }
- }
- else
- {
- WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
- }
-
- if(--husart->TxXferCount == 0U)
- {
- /* Disable the USART Transmit data register empty Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
- /* Disable the USART Transmit Complete Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxCpltCallback(husart);
-
- return HAL_OK;
-}
-
-/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- husart->pRxBuffPtr += 1U;
- }
- if(--husart->RxXferCount != 0x00U)
- {
- /* Send dummy byte in order to generate the clock for the slave to send the next data */
- WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
- }
- }
- else
- {
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
- }
-
- if(--husart->RxXferCount != 0x00U)
- {
- /* Send dummy byte in order to generate the clock for the slave to send the next data */
- WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
- }
- }
-
- if(husart->RxXferCount == 0U)
- {
- /* Disable the USART RXNE Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the USART Parity Error Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State = HAL_USART_STATE_READY;
- HAL_USART_RxCpltCallback(husart);
-
- return HAL_OK;
- }
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
- uint16_t* tmp;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- if(husart->TxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
- {
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->pTxBuffPtr += 1U;
- }
- }
- else
- {
- WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
- }
- husart->TxXferCount--;
-
- /* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
- {
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
- }
- }
- }
-
- if(husart->RxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
- {
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- husart->pRxBuffPtr += 1U;
- }
- }
- else
- {
- if(husart->Init.Parity == USART_PARITY_NONE)
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
- }
- }
- husart->RxXferCount--;
- }
- }
-
- /* Check the latest data received */
- if(husart->RxXferCount == 0U)
- {
- /* Disable the USART RXNE Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the USART Parity Error Interrupt */
- CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_TxRxCpltCallback(husart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configures the USART pferipheral.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-static void USART_SetConfig(USART_HandleTypeDef *husart)
-{
- /* Check the parameters */
- assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
- assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
- assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
- assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
- assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
- assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
- assert_param(IS_USART_PARITY(husart->Init.Parity));
- assert_param(IS_USART_MODE(husart->Init.Mode));
-
- /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
- receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
- CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE)));
-
- /*---------------------------- USART CR2 Configuration ---------------------*/
- /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
- /* Set CPOL bit according to husart->Init.CLKPolarity value */
- /* Set CPHA bit according to husart->Init.CLKPhase value */
- /* Set LBCL bit according to husart->Init.CLKLastBit value */
- /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
- /* Write to USART CR2 */
- MODIFY_REG(husart->Instance->CR2,
- (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP),
- ((uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits)));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Configure the USART Word Length, Parity and mode:
- Set the M bits according to husart->Init.WordLength value
- Set PCE and PS bits according to husart->Init.Parity value
- Set TE and RE bits according to husart->Init.Mode value */
- MODIFY_REG(husart->Instance->CR1,
- (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
- (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Clear CTSE and RTSE bits */
- CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- if((husart->Instance == USART1))
- {
- husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
- }
- else
- {
- husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
- }
-}
-
-/**
- * @}
- */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_hal_wwdg.c b/lib/hal-stm32f1/source/stm32f1xx_hal_wwdg.c deleted file mode 100644 index 719f4c8d..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_hal_wwdg.c +++ /dev/null @@ -1,314 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_hal_wwdg.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief WWDG HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State functions
- @verbatim
- ==============================================================================
- ##### WWDG specific features #####
- ==============================================================================
- [..]
- Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
-
- (+) An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
- (+) Once enabled the WWDG cannot be disabled except by a system reset.
- (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
- (+) The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
- (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
- (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
- (+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
-
- (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
- HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
-
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
-
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-/** @defgroup WWDG WWDG
- * @brief WWDG HAL module driver.
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and start the WWDG according to the specified parameters
- in the WWDG_InitTypeDef of associated handle.
- (+) Initialize the WWDG MSP.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the WWDG according to the specified.
- * parameters in the WWDG_InitTypeDef of associated handle.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check the WWDG handle allocation */
- if(hwwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
- assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
- assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
- assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
- assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
-
- /* Init the low level hardware */
- HAL_WWDG_MspInit(hwwdg);
-
- /* Set WWDG Counter */
- WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
-
- /* Set WWDG Prescaler and Window */
- WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the WWDG MSP.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @note When rewriting this function in user file, mechanism may be added
- * to avoid multiple initialize when HAL_WWDG_Init function is called
- * again to change parameters.
- * @retval None
- */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_MspInit could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Refresh the WWDG.
- (+) Handle WWDG interrupt request and associated function callback.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Refresh the WWDG.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
-{
- /* Write to WWDG CR the WWDG Counter value to refresh with */
- WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Handle WWDG interrupt request.
- * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
- * or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
- * EWIMode set to WWDG_EWI_ENABLE.
- * When the downcounter reaches the value 0x40, and EWI interrupt is
- * generated and the corresponding Interrupt Service Routine (ISR) can
- * be used to trigger specific actions (such as communications or data
- * logging), before resetting the device.
- * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
- {
- /* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
- {
- /* Clear the WWDG Early Wakeup flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Early Wakeup callback */
- HAL_WWDG_EarlyWakeupCallback(hwwdg);
- }
- }
-}
-
-/**
- * @brief WWDG Early Wakeup callback.
- * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
-
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_adc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_adc.c deleted file mode 100644 index d22b0bdf..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_adc.c +++ /dev/null @@ -1,903 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_adc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief ADC LL module driver
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_adc.h"
-#include "stm32f1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (ADC1) || defined (ADC2) || defined (ADC3)
-
-/** @addtogroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup ADC_LL_Private_Macros
- * @{
- */
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* common to several ADC instances. */
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC instance. */
-#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
- || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
- )
-
-#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
- ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
- || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
- )
-
-#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
- ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
- || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
- )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group regular */
-#if defined(ADC3)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
- ) \
- : \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
- ) \
- )
-#else
-#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
- )
-#else
-#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
- || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
- )
-#endif
-#endif
-#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
- || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
- )
-
-#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
- || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
- )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
- || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
- )
-
-#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
- || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
- )
-
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* ADC group injected */
-#if defined(ADC3)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
- ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
- ) \
- : \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
- ) \
- )
-#else
-#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
- )
-#else
-#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
- || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
- )
-#endif
-#endif
-#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
- || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
- )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
- || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
- )
-
-#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
- || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
- )
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/* Check of parameters for configuration of ADC hierarchical scope: */
-/* multimode. */
-#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
- || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
- )
-
-#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
- || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
- || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
- )
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of all ADC instances belonging to
- * the same ADC common instance to their default reset values.
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-
- /* Force reset of ADC clock (core clock) */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
-
- /* Release reset of ADC clock (core clock) */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize some features of ADC common parameters
- * (all ADC instances belonging to the same ADC common instance)
- * and multimode (for devices with several ADC instances available).
- * @note The setting of ADC common parameters is conditioned to
- * ADC instances state:
- * All ADC instances belonging to the same ADC common instance
- * must be disabled.
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC common registers are initialized
- * - ERROR: ADC common registers are not initialized
- */
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-#if defined(ADC_MULTIMODE_SUPPORT)
- assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
-#endif /* ADC_MULTIMODE_SUPPORT */
-
- /* Note: Hardware constraint (refer to description of functions */
- /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
- /* ADC state: */
- /* All ADC instances of the ADC common group must be disabled. */
- if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - common to several ADC */
- /* (all ADC instances belonging to the same ADC common instance) */
- /* - multimode (if several ADC instances available on the */
- /* selected device) */
- /* - Set ADC multimode configuration */
- /* - Set ADC multimode DMA transfer */
- /* - Set ADC multimode: delay between 2 sampling phases */
-#if defined(ADC_MULTIMODE_SUPPORT)
- if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
- {
- MODIFY_REG(ADCxy_COMMON->CR1,
- ADC_CR1_DUALMOD,
- ADC_CommonInitStruct->Multimode
- );
- }
- else
- {
- MODIFY_REG(ADCxy_COMMON->CR1,
- ADC_CR1_DUALMOD,
- LL_ADC_MULTI_INDEPENDENT
- );
- }
-#endif
- }
- else
- {
- /* Initialization error: One or several ADC instances belonging to */
- /* the same ADC common instance are not disabled. */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
- * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
-{
- /* Set ADC_CommonInitStruct fields to default values */
- /* Set fields of ADC common */
- /* (all ADC instances belonging to the same ADC common instance) */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
- /* Set fields of ADC multimode */
- ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
-#endif /* ADC_MULTIMODE_SUPPORT */
-}
-
-/**
- * @brief De-initialize registers of the selected ADC instance
- * to their default reset values.
- * @note To reset all ADC instances quickly (perform a hard reset),
- * use function @ref LL_ADC_CommonDeInit().
- * @param ADCx ADC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are de-initialized
- * - ERROR: ADC registers are not de-initialized
- */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- /* Disable ADC instance if not already disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 1U)
- {
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
- /* Disable the ADC instance */
- LL_ADC_Disable(ADCx);
- }
-
- /* Check whether ADC state is compliant with expected state */
- /* (hardware requirements of bits state to reset registers below) */
- if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
- {
- /* ========== Reset ADC registers ========== */
- /* Reset register SR */
- CLEAR_BIT(ADCx->SR,
- ( LL_ADC_FLAG_STRT
- | LL_ADC_FLAG_JSTRT
- | LL_ADC_FLAG_EOS
- | LL_ADC_FLAG_JEOS
- | LL_ADC_FLAG_AWD1 )
- );
-
- /* Reset register CR1 */
- #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-
- CLEAR_BIT(ADCx->CR1,
- ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD
- | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
- | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
- | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
- | ADC_CR1_AWDCH )
- );
- #else
-
- CLEAR_BIT(ADCx->CR1,
- ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM
- | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO
- | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE
- | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )
- );
- #endif
-
- /* Reset register CR2 */
- CLEAR_BIT(ADCx->CR2,
- ( ADC_CR2_TSVREFE
- | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
- | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
- | ADC_CR2_ALIGN | ADC_CR2_DMA
- | ADC_CR2_RSTCAL | ADC_CR2_CAL
- | ADC_CR2_CONT | ADC_CR2_ADON )
- );
-
- /* Reset register SMPR1 */
- CLEAR_BIT(ADCx->SMPR1,
- ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
- | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
- | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
- );
-
- /* Reset register SMPR2 */
- CLEAR_BIT(ADCx->SMPR2,
- ( ADC_SMPR2_SMP9
- | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
- | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
- | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
- );
-
- /* Reset register JOFR1 */
- CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
- /* Reset register JOFR2 */
- CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
- /* Reset register JOFR3 */
- CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
- /* Reset register JOFR4 */
- CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
-
- /* Reset register HTR */
- SET_BIT(ADCx->HTR, ADC_HTR_HT);
- /* Reset register LTR */
- CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
-
- /* Reset register SQR1 */
- CLEAR_BIT(ADCx->SQR1,
- ( ADC_SQR1_L
- | ADC_SQR1_SQ16
- | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
- );
-
- /* Reset register SQR2 */
- CLEAR_BIT(ADCx->SQR2,
- ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
- | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
- );
-
-
- /* Reset register JSQR */
- CLEAR_BIT(ADCx->JSQR,
- ( ADC_JSQR_JL
- | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
- | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
- );
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable */
-
- /* Reset registers JDR1, JDR2, JDR3, JDR4 */
- /* bits in access mode read only, no direct reset applicable */
-
- }
-
- return status;
-}
-
-/**
- * @brief Initialize some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, some other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-
- assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
- assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC instance */
- /* - Set ADC conversion data alignment */
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_SCAN
- ,
- ADC_InitStruct->SequencersScanMode
- );
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_ALIGN
- ,
- ADC_InitStruct->DataAlignment
- );
-
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
- * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
-{
- /* Set ADC_InitStruct fields to default values */
- /* Set fields of ADC instance */
- ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
-
- /* Enable scan mode to have a generic behavior with ADC of other */
- /* STM32 families, without this setting available: */
- /* ADC group regular sequencer and ADC group injected sequencer depend */
- /* only of their own configuration. */
- ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
-
-}
-
-/**
- * @brief Initialize some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group regular or group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-#if defined(ADC3)
- assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
-#else
- assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
-#endif
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
- assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group regular */
- /* - Set ADC group regular trigger source */
- /* - Set ADC group regular sequencer length */
- /* - Set ADC group regular sequencer discontinuous mode */
- /* - Set ADC group regular continuous mode */
- /* - Set ADC group regular conversion data transfer: no transfer or */
- /* transfer by DMA, and DMA requests mode */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
- if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_DISCEN
- | ADC_CR1_DISCNUM
- ,
- ADC_REG_InitStruct->SequencerLength
- | ADC_REG_InitStruct->SequencerDiscont
- );
- }
- else
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_DISCEN
- | ADC_CR1_DISCNUM
- ,
- ADC_REG_InitStruct->SequencerLength
- | LL_ADC_REG_SEQ_DISCONT_DISABLE
- );
- }
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_EXTSEL
- | ADC_CR2_CONT
- | ADC_CR2_DMA
- ,
- ADC_REG_InitStruct->TriggerSource
- | ADC_REG_InitStruct->ContinuousMode
- | ADC_REG_InitStruct->DMATransfer
- );
-
- /* Set ADC group regular sequencer length and scan direction */
- /* Note: Hardware constraint (refer to description of this function): */
- /* Note: If ADC instance feature scan mode is disabled */
- /* (refer to ADC instance initialization structure */
- /* parameter @ref SequencersScanMode */
- /* or function @ref LL_ADC_SetSequencersScanMode() ), */
- /* this parameter is discarded. */
- LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
- * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
-{
- /* Set ADC_REG_InitStruct fields to default values */
- /* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
- ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
- ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
- ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
- ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
- ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
-}
-
-/**
- * @brief Initialize some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- * @note After using this function, other features must be configured
- * using LL unitary functions.
- * The minimum configuration remaining to be done is:
- * - Set ADC group injected sequencer:
- * map channel on the selected sequencer rank.
- * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
- * - Set ADC channel sampling time
- * Refer to function LL_ADC_SetChannelSamplingTime();
- * @param ADCx ADC instance
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ADC registers are initialized
- * - ERROR: ADC registers are not initialized
- */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-#if defined(ADC3)
- assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
-#else
- assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
-#endif
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
- {
- assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
- }
- assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* ADC instance must be disabled. */
- if(LL_ADC_IsEnabled(ADCx) == 0U)
- {
- /* Configuration of ADC hierarchical scope: */
- /* - ADC group injected */
- /* - Set ADC group injected trigger source */
- /* - Set ADC group injected sequencer length */
- /* - Set ADC group injected sequencer discontinuous mode */
- /* - Set ADC group injected conversion trigger: independent or */
- /* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
- /* ADC conversion. */
- /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
- if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_JDISCEN
- | ADC_CR1_JAUTO
- ,
- ADC_INJ_InitStruct->SequencerDiscont
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
- else
- {
- MODIFY_REG(ADCx->CR1,
- ADC_CR1_JDISCEN
- | ADC_CR1_JAUTO
- ,
- LL_ADC_REG_SEQ_DISCONT_DISABLE
- | ADC_INJ_InitStruct->TrigAuto
- );
- }
-
- MODIFY_REG(ADCx->CR2,
- ADC_CR2_JEXTSEL
- ,
- ADC_INJ_InitStruct->TriggerSource
- );
-
- /* Note: Hardware constraint (refer to description of this function): */
- /* Note: If ADC instance feature scan mode is disabled */
- /* (refer to ADC instance initialization structure */
- /* parameter @ref SequencersScanMode */
- /* or function @ref LL_ADC_SetSequencersScanMode() ), */
- /* this parameter is discarded. */
- LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
- }
- else
- {
- /* Initialization error: ADC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
- * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
-{
- /* Set ADC_INJ_InitStruct fields to default values */
- /* Set fields of ADC group injected */
- ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
- ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
- ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
- ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 || ADC2 || ADC3 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_crc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_crc.c deleted file mode 100644 index c730c521..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_crc.c +++ /dev/null @@ -1,126 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_crc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief CRC LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_crc.h"
-#include "stm32f1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (CRC)
-
-/** @addtogroup CRC_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup CRC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize CRC registers (Registers restored to their default values).
- * @param CRCx CRC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: CRC registers are de-initialized
- * - ERROR: CRC registers are not de-initialized
- */
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_CRC_ALL_INSTANCE(CRCx));
-
- if (CRCx == CRC)
- {
-
- /* Reset the CRC calculation unit */
- LL_CRC_ResetCRCCalculationUnit(CRCx);
-
- /* Reset IDR register */
- LL_CRC_Write_IDR(CRCx, 0x00U);
- }
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (CRC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_dac.c b/lib/hal-stm32f1/source/stm32f1xx_ll_dac.c deleted file mode 100644 index 344499d1..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_dac.c +++ /dev/null @@ -1,274 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_dac.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief DAC LL module driver
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_dac.h"
-#include "stm32f1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DAC)
-
-/** @addtogroup DAC_LL DAC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @addtogroup DAC_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
- ( \
- ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
- )
-
-#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
- || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
- )
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- )
-
-#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
- ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
- )
-
-#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
- ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
- )
-
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize registers of the selected DAC instance
- * to their default reset values.
- * @param DACx DAC instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DAC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
-{
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(DACx));
-
- /* Force reset of DAC1 clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
-
- /* Release reset of DAC1 clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
- return SUCCESS;
-}
-
-/**
- * @brief Initialize some features of DAC instance.
- * @note The setting of these parameters by function @ref LL_DAC_Init()
- * is conditioned to DAC state:
- * DAC instance must be disabled.
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DAC registers are initialized
- * - ERROR: DAC registers are not initialized
- */
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALL_INSTANCE(DACx));
- assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
- assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
- assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
- assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
- if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
- {
- assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
- }
-
- /* Note: Hardware constraint (refer to description of this function) */
- /* DAC instance must be disabled. */
- if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
- {
- /* Configuration of DAC channel: */
- /* - TriggerSource */
- /* - WaveAutoGeneration */
- /* - OutputBuffer */
- if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
- {
- MODIFY_REG(DACx->CR,
- ( DAC_CR_TSEL1
- | DAC_CR_WAVE1
- | DAC_CR_MAMP1
- | DAC_CR_BOFF1
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- ,
- ( DAC_InitStruct->TriggerSource
- | DAC_InitStruct->WaveAutoGeneration
- | DAC_InitStruct->WaveAutoGenerationConfig
- | DAC_InitStruct->OutputBuffer
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
- }
- else
- {
- MODIFY_REG(DACx->CR,
- ( DAC_CR_TSEL1
- | DAC_CR_WAVE1
- | DAC_CR_BOFF1
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- ,
- ( DAC_InitStruct->TriggerSource
- | LL_DAC_WAVE_AUTO_GENERATION_NONE
- | DAC_InitStruct->OutputBuffer
- ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
- }
- }
- else
- {
- /* Initialization error: DAC instance is not disabled. */
- status = ERROR;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
- * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
-{
- /* Set DAC_InitStruct fields to default values */
- DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
- DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
- /* Note: Parameter discarded if wave auto generation is disabled, */
- /* set anyway to its default value. */
- DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
- DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_dma.c b/lib/hal-stm32f1/source/stm32f1xx_ll_dma.c deleted file mode 100644 index 8ac65cfe..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_dma.c +++ /dev/null @@ -1,331 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_dma.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief DMA LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_dma.h"
-#include "stm32f1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
- * @{
- */
-#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA2)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#endif
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the DMA registers to their default reset values.
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are de-initialized
- * - ERROR: DMA registers are not de-initialized
- */
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
- ErrorStatus status = SUCCESS;
-
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Disable the selected DMAx_Channely */
- CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
- /* Reset DMAx_Channely control register */
- LL_DMA_WriteReg(tmp, CCR, 0U);
-
- /* Reset DMAx_Channely remaining bytes register */
- LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
- /* Reset DMAx_Channely peripheral address register */
- LL_DMA_WriteReg(tmp, CPAR, 0U);
-
- /* Reset DMAx_Channely memory address register */
- LL_DMA_WriteReg(tmp, CMAR, 0U);
-
- if (Channel == LL_DMA_CHANNEL_1)
- {
- /* Reset interrupt pending bits for DMAx Channel1 */
- LL_DMA_ClearFlag_GI1(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_2)
- {
- /* Reset interrupt pending bits for DMAx Channel2 */
- LL_DMA_ClearFlag_GI2(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_3)
- {
- /* Reset interrupt pending bits for DMAx Channel3 */
- LL_DMA_ClearFlag_GI3(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_4)
- {
- /* Reset interrupt pending bits for DMAx Channel4 */
- LL_DMA_ClearFlag_GI4(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_5)
- {
- /* Reset interrupt pending bits for DMAx Channel5 */
- LL_DMA_ClearFlag_GI5(DMAx);
- }
-
- else if (Channel == LL_DMA_CHANNEL_6)
- {
- /* Reset interrupt pending bits for DMAx Channel6 */
- LL_DMA_ClearFlag_GI6(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_7)
- {
- /* Reset interrupt pending bits for DMAx Channel7 */
- LL_DMA_ClearFlag_GI7(DMAx);
- }
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
- * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
- * @arg @ref __LL_DMA_GET_INSTANCE
- * @arg @ref __LL_DMA_GET_CHANNEL
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Check the DMA parameters from DMA_InitStruct */
- assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
- assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
- assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
- assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
- assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
- assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
- assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
- assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
- /*---------------------------- DMAx CCR Configuration ------------------------
- * Configure DMAx_Channely: data transfer direction, data transfer mode,
- * peripheral and memory increment mode,
- * data size alignment and priority level with parameters :
- * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
- * - Mode: DMA_CCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
- * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
- * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
- * - Priority: DMA_CCR_PL[1:0] bits
- */
- LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
- DMA_InitStruct->Mode | \
- DMA_InitStruct->PeriphOrM2MSrcIncMode | \
- DMA_InitStruct->MemoryOrM2MDstIncMode | \
- DMA_InitStruct->PeriphOrM2MSrcDataSize | \
- DMA_InitStruct->MemoryOrM2MDstDataSize | \
- DMA_InitStruct->Priority);
-
- /*-------------------------- DMAx CMAR Configuration -------------------------
- * Configure the memory or destination base address with parameter :
- * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
- */
- LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
- /*-------------------------- DMAx CPAR Configuration -------------------------
- * Configure the peripheral or source base address with parameter :
- * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
- */
- LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
- /*--------------------------- DMAx CNDTR Configuration -----------------------
- * Configure the peripheral base address with parameter :
- * - NbData: DMA_CNDTR_NDT[15:0] bits
- */
- LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
- * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval None
- */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
- DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
- DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
- DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
- DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = 0x00000000U;
- DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_exti.c b/lib/hal-stm32f1/source/stm32f1xx_ll_exti.c deleted file mode 100644 index 5ee57b14..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_exti.c +++ /dev/null @@ -1,232 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_exti.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief EXTI LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_exti.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
-#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the EXTI registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are de-initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_DeInit(void)
-{
- /* Interrupt mask register set to default reset values */
- LL_EXTI_WriteReg(IMR, 0x00000000U);
- /* Event mask register set to default reset values */
- LL_EXTI_WriteReg(EMR, 0x00000000U);
- /* Rising Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(RTSR, 0x00000000U);
- /* Falling Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(FTSR, 0x00000000U);
- /* Software interrupt event register set to default reset values */
- LL_EXTI_WriteReg(SWIER, 0x00000000U);
- /* Pending register clear */
- LL_EXTI_WriteReg(PR, 0x000FFFFFU);
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
- * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- ErrorStatus status = SUCCESS;
- /* Check the parameters */
- assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
- assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
- /* ENABLE LineCommand */
- if (EXTI_InitStruct->LineCommand != DISABLE)
- {
- assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
- /* Configure EXTI Lines in range from 0 to 31 */
- if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
- {
- switch (EXTI_InitStruct->Mode)
- {
- case LL_EXTI_MODE_IT:
- /* First Disable Event on provided Lines */
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_EVENT:
- /* First Disable IT on provided Lines */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Event on provided Lines */
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_IT_EVENT:
- /* Directly Enable IT & Event on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
- {
- switch (EXTI_InitStruct->Trigger)
- {
- case LL_EXTI_TRIGGER_RISING:
- /* First Disable Falling Trigger on provided Lines */
- LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Rising Trigger on provided Lines */
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_FALLING:
- /* First Disable Rising Trigger on provided Lines */
- LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Falling Trigger on provided Lines */
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_RISING_FALLING:
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- }
- }
- }
- /* DISABLE LineCommand */
- else
- {
- /* De-configure EXTI Lines in range from 0 to 31 */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
- * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval None
- */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
- EXTI_InitStruct->LineCommand = DISABLE;
- EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
- EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (EXTI) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_fsmc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_fsmc.c deleted file mode 100644 index 73cf7667..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_fsmc.c +++ /dev/null @@ -1,931 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_fsmc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief FSMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
- * + Initialization/de-initialization functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- =============================================================================
- ##### FSMC peripheral features #####
- =============================================================================
- [..] The Flexible static memory controller (FSMC) includes following memory controllers:
- (+) The NOR/PSRAM memory controller
- (+) The PC Card memory controller
- (+) The NAND memory controller
- (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
-
- [..] The FSMC functional block makes the interface with synchronous and asynchronous static
- memories and 16-bit PC memory cards. Its main purposes are:
- (+) to translate AHB transactions into the appropriate external device protocol.
- (+) to meet the access time requirements of the external memory devices.
-
- [..] All external memories share the addresses, data and control signals with the controller.
- Each external device is accessed by means of a unique Chip Select. The FSMC performs
- only one access at a time to an external device.
- The main features of the FSMC controller are the following:
- (+) Interface with static-memory mapped devices including:
- (++) Static random access memory (SRAM).
- (++) NOR Flash memory.
- (++) PSRAM (4 memory banks).
- (++) 16-bit PC Card compatible devices.
- (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
- data.
- (+) Independent Chip Select control for each memory bank.
- (+) Independent configuration for each memory bank.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined(FSMC_BANK1)
-
-#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
-
-/** @defgroup FSMC_LL FSMC Low Layer
- * @brief FSMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
- * @brief NORSRAM Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NORSRAM device driver #####
- ==============================================================================
-
- [..]
- This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
- to run the NORSRAM external devices.
-
- (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
- (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
- (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
- (+) FSMC NORSRAM bank extended timing configuration using the function
- FSMC_NORSRAM_Extended_Timing_Init()
- (+) FSMC NORSRAM bank enable/disable write operation using the functions
- FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
-
-@endverbatim
- * @{
- */
-
-/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
- * @brief Initialization and Configuration functions
- *
- @verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FSMC NORSRAM interface
- (+) De-initialize the FSMC NORSRAM interface
- (+) Configure the FSMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initialize the FSMC_NORSRAM device according to the specified
- * control parameters in the FSMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
- assert_param(IS_FSMC_MUX(Init->DataAddressMux));
- assert_param(IS_FSMC_MEMORY(Init->MemoryType));
- assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
- assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
- assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
- assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
- assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
- assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
- assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
- assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
-
- /* Disable NORSRAM Device */
- __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
-
- /* Set NORSRAM device control parameters */
- if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
- {
- MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
- | Init->DataAddressMux
- | Init->MemoryType
- | Init->MemoryDataWidth
- | Init->BurstAccessMode
- | Init->WaitSignalPolarity
- | Init->WrapMode
- | Init->WaitSignalActive
- | Init->WriteOperation
- | Init->WaitSignal
- | Init->ExtendedMode
- | Init->AsynchronousWait
- | Init->WriteBurst
- )
- );
- }
- else
- {
- MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
- | Init->DataAddressMux
- | Init->MemoryType
- | Init->MemoryDataWidth
- | Init->BurstAccessMode
- | Init->WaitSignalPolarity
- | Init->WrapMode
- | Init->WaitSignalActive
- | Init->WriteOperation
- | Init->WaitSignal
- | Init->ExtendedMode
- | Init->AsynchronousWait
- | Init->WriteBurst
- )
- );
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitialize the FSMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
- assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
- /* Disable the FSMC_NORSRAM device */
- __FSMC_NORSRAM_DISABLE(Device, Bank);
-
- /* De-initialize the FSMC_NORSRAM device */
- /* FSMC_NORSRAM_BANK1 */
- if(Bank == FSMC_NORSRAM_BANK1)
- {
- Device->BTCR[Bank] = 0x000030DBU;
- }
- /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
- else
- {
- Device->BTCR[Bank] = 0x000030D2U;
- }
-
- Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
- ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Initialize the FSMC_NORSRAM Timing according to the specified
- * parameters in the FSMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
- assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
- assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
- /* Set FSMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1U], \
- BTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | \
- ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | \
- ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | \
- (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
- (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | \
- (Timing->AccessMode)));
-
- return HAL_OK;
-}
-
-/**
- * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
- * parameters in the FSMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
- * @param ExtendedMode FSMC Extended Mode
- * This parameter can be one of the following values:
- * @arg FSMC_EXTENDED_MODE_DISABLE
- * @arg FSMC_EXTENDED_MODE_ENABLE
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
-
- /* Set NORSRAM device timing register for write configuration, if extended mode is used */
- if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
- {
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
- assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
- assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-#else
- assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
- assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
- /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
- MODIFY_REG(Device->BWTR[Bank], \
- BWTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
- ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
- Timing->AccessMode | \
- ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
-#else
- MODIFY_REG(Device->BWTR[Bank], \
- BWTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
- ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
- Timing->AccessMode | \
- (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
- (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
- }
- else
- {
- Device->BWTR[Bank] = 0x0FFFFFFFU;
- }
-
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Group2 Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FSMC_NORSRAM Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FSMC NORSRAM interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically FSMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
- /* Enable write operation */
- SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FSMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
- assert_param(IS_FSMC_NORSRAM_BANK(Bank));
-
- /* Disable write operation */
- CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
-
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_NAND FSMC NAND Controller functions
- * @brief NAND Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use NAND device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FSMC NAND banks in order
- to run the NAND external devices.
-
- (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
- (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
- (+) FSMC NAND bank common space timing configuration using the function
- FSMC_NAND_CommonSpace_Timing_Init()
- (+) FSMC NAND bank attribute space timing configuration using the function
- FSMC_NAND_AttributeSpace_Timing_Init()
- (+) FSMC NAND bank enable/disable ECC correction feature using the functions
- FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
- (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FSMC NAND interface
- (+) De-initialize the FSMC NAND interface
- (+) Configure the FSMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FSMC_NAND device according to the specified
- * control parameters in the FSMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
- assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
- assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
- assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
- assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
- assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
-
- /* Set NAND device control parameters */
- if (Init->NandBank == FSMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
- FSMC_PCR_MEMORY_TYPE_NAND |
- Init->MemoryDataWidth |
- Init->EccComputation |
- Init->ECCPageSize |
- ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
- ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
- FSMC_PCR_MEMORY_TYPE_NAND |
- Init->MemoryDataWidth |
- Init->EccComputation |
- Init->ECCPageSize |
- ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
- ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FSMC_NAND Common space Timing according to the specified
- * parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Set FMC_NAND device timing parameters */
- if(Bank == FSMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
- ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
- ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
- ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
- ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
- * parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Set FMC_NAND device timing parameters */
- if(Bank == FSMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
- ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
- ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
- }
- else
- {
- /* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
- ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
- ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
- }
-
- return HAL_OK;
-}
-
-
-/**
- * @brief DeInitializes the FSMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Disable the NAND Bank */
- __FSMC_NAND_DISABLE(Device, Bank);
-
- /* De-initialize the NAND Bank */
- if(Bank == FSMC_NAND_BANK2)
- {
- /* Set the FSMC_NAND_BANK2 registers to their reset values */
- WRITE_REG(Device->PCR2, 0x00000018U);
- WRITE_REG(Device->SR2, 0x00000040U);
- WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
- WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
- }
- /* FSMC_Bank3_NAND */
- else
- {
- /* Set the FSMC_NAND_BANK3 registers to their reset values */
- WRITE_REG(Device->PCR3, 0x00000018U);
- WRITE_REG(Device->SR3, 0x00000040U);
- WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
- WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ==============================================================================
- ##### FSMC_NAND Control functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to control dynamically
- the FSMC NAND interface.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Enable ECC feature */
- if(Bank == FSMC_NAND_BANK2)
- {
- SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
- }
- else
- {
- SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Disable ECC feature */
- if(Bank == FSMC_NAND_BANK2)
- {
- CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
- }
- else
- {
- CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Disables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_FSMC_NAND_DEVICE(Device));
- assert_param(IS_FSMC_NAND_BANK(Bank));
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until FIFO is empty */
- while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
-
- if(Bank == FSMC_NAND_BANK2)
- {
- /* Get the ECCR2 register value */
- *ECCval = (uint32_t)Device->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- *ECCval = (uint32_t)Device->ECCR3;
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
- @verbatim
- ==============================================================================
- ##### How to use PCCARD device driver #####
- ==============================================================================
- [..]
- This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
- to run the PCCARD/compact flash external devices.
-
- (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
- (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
- (+) FSMC PCCARD bank common space timing configuration using the function
- FSMC_PCCARD_CommonSpace_Timing_Init()
- (+) FSMC PCCARD bank attribute space timing configuration using the function
- FSMC_PCCARD_AttributeSpace_Timing_Init()
- (+) FSMC PCCARD bank IO space timing configuration using the function
- FSMC_PCCARD_IOSpace_Timing_Init()
-
-@endverbatim
- * @{
- */
-
-/** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de_initialization functions #####
- ==============================================================================
- [..]
- This section provides functions allowing to:
- (+) Initialize and configure the FSMC PCCARD interface
- (+) De-initialize the FSMC PCCARD interface
- (+) Configure the FSMC clock and associated GPIOs
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the FSMC_PCCARD device according to the specified
- * control parameters in the FSMC_PCCARD_HandleTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Init: Pointer to PCCARD Initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_PCCARD_DEVICE(Device));
- assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
- assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
-
- /* Set FSMC_PCCARD device control parameters */
- MODIFY_REG(Device->PCR4,
- (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID |
- FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
- (FSMC_PCR_MEMORY_TYPE_PCCARD |
- Init->Waitfeature |
- FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
- (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) |
- (Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
- * parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_PCCARD_DEVICE(Device));
- assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set PCCARD timing parameters */
- MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
- (Timing->SetupTime |
- ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
- ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
- ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
- * parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_PCCARD_DEVICE(Device));
- assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set PCCARD timing parameters */
- MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
- (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
- ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
- ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
-
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
- * parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_PCCARD_DEVICE(Device));
- assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
-
- /* Set FSMC_PCCARD device timing parameters */
- MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
- (Timing->SetupTime | \
- (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | \
- (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | \
- (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
-
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the FSMC_PCCARD device
- * @param Device: Pointer to PCCARD device instance
- * @retval HAL status
- */
-HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
-{
- /* Check the parameters */
- assert_param(IS_FSMC_PCCARD_DEVICE(Device));
-
- /* Disable the FSMC_PCCARD device */
- __FSMC_PCCARD_DISABLE(Device);
-
- /* De-initialize the FSMC_PCCARD device */
- WRITE_REG(Device->PCR4, 0x00000018U);
- WRITE_REG(Device->SR4, 0x00000040U);
- WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
- WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
- WRITE_REG(Device->PIO4, 0xFCFCFCFCU);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
-
-#endif /* FSMC_BANK1 */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_gpio.c b/lib/hal-stm32f1/source/stm32f1xx_ll_gpio.c deleted file mode 100644 index 2f8cb971..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_gpio.c +++ /dev/null @@ -1,265 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_gpio.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief GPIO LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_gpio.h"
-#include "stm32f1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
-
-/** @addtogroup GPIO_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
- * @{
- */
-#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
- ((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
- ((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
-
-#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
- ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
- ((__VALUE__) == LL_GPIO_PULL_UP))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize GPIO registers (Registers restored to their default values).
- * @param GPIOx GPIO Port
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are de-initialized
- * - ERROR: Wrong GPIO Port
- */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
- /* Force and Release reset on clock of GPIOx Port */
- if (GPIOx == GPIOA)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
- }
- else if (GPIOx == GPIOB)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
- }
- else if (GPIOx == GPIOC)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
- }
- else if (GPIOx == GPIOD)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
- }
-#if defined(GPIOE)
- else if (GPIOx == GPIOE)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
- }
-#endif
-#if defined(GPIOF)
- else if (GPIOx == GPIOF)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
- }
-#endif
-#if defined(GPIOG)
- else if (GPIOx == GPIOG)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
- }
-#endif
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
- * @param GPIOx GPIO Port
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
- * that contains the configuration information for the specified GPIO peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
- * - ERROR: Not applicable
- */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00000000U;
- uint32_t currentpin = 0x00000000U;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
- assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
- assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
- /* ------------------------- Configure the port pins ---------------- */
- /* Initialize pinpos on first pin set */
- pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
-
- /* Configure the port pins */
- while ((((GPIO_InitStruct->Pin) & 0x0000FFFFU) >> pinpos) != 0x00000000U)
- {
- /* Get current io position */
- if(pinpos <8 )
- {
- currentpin = (GPIO_InitStruct->Pin) & (0x00000101U << pinpos);
- }
- else
- {
- currentpin = (GPIO_InitStruct->Pin) & ((0x00010001U << (pinpos-8)) | 0x04000000U);
- }
-
- if (currentpin)
- {
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
- /* Pull-up Pull down resistor configuration*/
- LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
- {
- /* Speed mode configuration */
- LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
- }
- }
- pinpos++;
- }
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
- }
- return (SUCCESS);
-}
-
-/**
- * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
- GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
- GPIO_InitStruct->Speed = 0x00000000U;
- GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
- GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_i2c.c b/lib/hal-stm32f1/source/stm32f1xx_ll_i2c.c deleted file mode 100644 index b8668cf6..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_i2c.c +++ /dev/null @@ -1,239 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_i2c.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief I2C LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_i2c.h"
-#include "stm32f1xx_ll_bus.h"
-#include "stm32f1xx_ll_rcc.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (I2C1) || defined (I2C2)
-
-/** @defgroup I2C_LL I2C
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup I2C_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
- ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-
-#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
-
-#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
- ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
-
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
-
-#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
- ((__VALUE__) == LL_I2C_NACK))
-
-#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
- ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the I2C registers to their default reset values.
- * @param I2Cx I2C Instance.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are de-initialized
- * - ERROR: I2C registers are not de-initialized
- */
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the I2C Instance I2Cx */
- assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Force reset of I2C clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
-
- /* Release reset of I2C clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
- }
-#if defined(I2C2)
- else if (I2Cx == I2C2)
- {
- /* Force reset of I2C clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
-
- /* Release reset of I2C clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
-
- }
-#endif /* I2C2 */
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
- * @param I2Cx I2C Instance.
- * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
-{
- LL_RCC_ClocksTypeDef rcc_clocks;
-
- /* Check the I2C Instance I2Cx */
- assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
- /* Check the I2C parameters from I2C_InitStruct */
- assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
- assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
- assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
- assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
-
- /* Disable the selected I2Cx Peripheral */
- LL_I2C_Disable(I2Cx);
-
- /* Retrieve Clock frequencies */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
- /*---------------------------- I2Cx SCL Clock Speed Configuration ------------
- * Configure the SCL speed :
- * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
- * and I2C_CCR_CCR[11:0] bits
- * - DutyCycle: I2C_CCR_DUTY[7:0] bits
- */
- LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
-
- /*---------------------------- I2Cx OAR1 Configuration -----------------------
- * Disable, Configure and Enable I2Cx device own address 1 with parameters :
- * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
- * - OwnAddrSize: I2C_OAR1_ADDMODE bit
- */
- LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-
- /*---------------------------- I2Cx MODE Configuration -----------------------
- * Configure I2Cx peripheral mode with parameter :
- * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
- */
- LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
-
- /* Enable the selected I2Cx Peripheral */
- LL_I2C_Enable(I2Cx);
-
- /*---------------------------- I2Cx CR2 Configuration ------------------------
- * Configure the ACKnowledge or Non ACKnowledge condition
- * after the address receive match code or next received byte with parameter :
- * - TypeAcknowledge: I2C_CR2_NACK bit
- */
- LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
- * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
- * @retval None
- */
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
-{
- /* Set I2C_InitStruct fields to default values */
- I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
- I2C_InitStruct->ClockSpeed = 5000U;
- I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
- I2C_InitStruct->OwnAddress1 = 0U;
- I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
- I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* I2C1 || I2C2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_pwr.c b/lib/hal-stm32f1/source/stm32f1xx_ll_pwr.c deleted file mode 100644 index 34acbdd8..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_pwr.c +++ /dev/null @@ -1,103 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_pwr.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief PWR LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_pwr.h"
-#include "stm32f1xx_ll_bus.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup PWR_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the PWR registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PWR registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_PWR_DeInit(void)
-{
- /* Force reset of PWR clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
- /* Release reset of PWR clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(PWR) */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_rcc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_rcc.c deleted file mode 100644 index e73cfcd0..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_rcc.c +++ /dev/null @@ -1,507 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_rcc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief RCC LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_rcc.h"
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
- * @{
- */
-#if defined(RCC_PLLI2S_SUPPORT)
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(USB) || defined(USB_OTG_FS)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* USB */
-
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
- * @{
- */
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-#if defined(RCC_PLLI2S_SUPPORT)
-uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLL2_SUPPORT)
-uint32_t RCC_PLL2_GetFreqClockFreq(void);
-#endif /* RCC_PLL2_SUPPORT */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE PLL, PLL2, PLL3 OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RCC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_RCC_DeInit(void)
-{
- uint32_t vl_mask = 0U;
-
- /* Set HSION bit */
- LL_RCC_HSI_Enable();
-
- /* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
- RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
-
-#if defined(USB)
- /* Reset USBPRE bit */
- CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
-#elif defined(USB_OTG_FS)
- /* Reset OTGFSPRE bit */
- CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
-#endif /* USB */
-
-#if defined(RCC_CFGR_PLLMULL2)
- /* Set PLL multiplication factor to 2 */
- vl_mask |= RCC_CFGR_PLLMULL2;
-#else
- /* Set PLL multiplication factor to 4 */
- vl_mask |= RCC_CFGR_PLLMULL4;
-#endif /* RCC_CFGR_PLLMULL2 */
-
- LL_RCC_WriteReg(CFGR, vl_mask);
-
- /* Reset HSEON, HSEBYP, CSSON, PLLON bits */
- vl_mask = 0xFFFFFFFFU;
- CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
-
-#if defined(RCC_CR_PLL2ON)
- /* Reset PLL2ON bit */
- CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
-#endif /* RCC_CR_PLL2ON */
-
-#if defined(RCC_CR_PLL3ON)
- /* Reset PLL3ON bit */
- CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
-#endif /* RCC_CR_PLL3ON */
-
- LL_RCC_WriteReg(CR, vl_mask);
-
- /* Set HSITRIM bits to the reset value */
- LL_RCC_HSI_SetCalibTrimming(0x10U);
-
-#if defined(RCC_CFGR2_PREDIV1)
- /* Reset CFGR2 register */
- vl_mask = 0x00000000U;
-
-#if defined(RCC_PLL2_SUPPORT)
- /* Set PLL2 multiplication factor to 8 */
- vl_mask |= RCC_CFGR2_PLL2MUL8;
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
- /* Set PLL3 multiplication factor to 8 */
- vl_mask |= RCC_CFGR2_PLL3MUL8;
-#endif /* RCC_PLLI2S_SUPPORT */
-
- LL_RCC_WriteReg(CFGR2, vl_mask);
-#endif /* RCC_CFGR2_PREDIV1 */
-
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * and different peripheral clocks available on the device.
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
- * @note If SYSCLK source is PLL, function returns values based on
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- * @note (**) HSI_VALUE is a defined constant but the real value may vary
- * depending on the variations in voltage and temperature.
- * @note (***) HSE_VALUE is a defined constant, user has to ensure that
- * HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- * @note The result of this function could be incorrect when using fractional
- * value for HSE crystal.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- * @{
- */
-
-/**
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update structure fields. Otherwise, any
- * configuration based on this function will be incorrect.
- * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
- * @retval None
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
- /* Get SYSCLK frequency */
- RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Return I2Sx clock frequency
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE
- * @arg @ref LL_RCC_I2S3_CLKSOURCE
- * @retval I2S clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
- uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
- /* I2S1CLK clock frequency */
- switch (LL_RCC_GetI2SClockSource(I2SxSource))
- {
- case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
- case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
- i2s_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
- case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
- default:
- i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
- break;
- }
-
- return i2s_frequency;
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB) || defined(USB_OTG_FS)
-/**
- * @brief Return USBx clock frequency
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval USB clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
- */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
- uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
- /* USBCLK clock frequency */
- switch (LL_RCC_GetUSBClockSource(USBxSource))
- {
-#if defined(RCC_CFGR_USBPRE)
- case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
- default:
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
- }
- break;
-#endif /* RCC_CFGR_USBPRE */
-#if defined(RCC_CFGR_OTGFSPRE)
- /* USBCLK = PLLVCO/2
- = (2 x PLLCLK) / 2
- = PLLCLK */
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
- /* USBCLK = PLLVCO/3
- = (2 x PLLCLK) / 3 */
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
- default:
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
- }
- break;
-#endif /* RCC_CFGR_OTGFSPRE */
- }
-
- return usb_frequency;
-}
-#endif /* USB */
-
-/**
- * @brief Return ADCx clock frequency
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE
- * @retval ADC clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
-{
- uint32_t adc_prescaler = 0U;
- uint32_t adc_frequency = 0U;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
-
- /* Get ADC prescaler */
- adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
-
- /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
- adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
- / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
-
- return adc_frequency;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Return SYSTEM clock frequency
- * @retval SYSTEM clock frequency (in Hz)
- */
-uint32_t RCC_GetSystemClockFreq(void)
-{
- uint32_t frequency = 0U;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (LL_RCC_GetSysClkSource())
- {
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- frequency = HSI_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- frequency = HSE_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
- frequency = RCC_PLL_GetFreqDomain_SYS();
- break;
-
- default:
- frequency = HSI_VALUE;
- break;
- }
-
- return frequency;
-}
-
-/**
- * @brief Return HCLK clock frequency
- * @param SYSCLK_Frequency SYSCLK clock frequency
- * @retval HCLK clock frequency (in Hz)
- */
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
- /* HCLK clock frequency */
- return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
- * @brief Return PCLK1 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK1 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK1 clock frequency */
- return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-
-/**
- * @brief Return PCLK2 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK2 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK2 clock frequency */
- return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
-}
-
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
- uint32_t pllinputfreq = 0U, pllsource = 0U;
-
- /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
-
- /* Get PLL source */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
- case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE / 2U;
- break;
-
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
- break;
-
-#if defined(RCC_PLL2_SUPPORT)
- case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
- pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
- break;
-#endif /* RCC_PLL2_SUPPORT */
-
- default:
- pllinputfreq = HSI_VALUE / 2U;
- break;
- }
- return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
-}
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL2_GetFreqClockFreq(void)
-{
- return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
-{
- return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_rtc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_rtc.c deleted file mode 100644 index dc5ceae1..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_rtc.c +++ /dev/null @@ -1,558 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_rtc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief RTC LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_rtc.h"
-#include "stm32f1xx_ll_cortex.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RTC)
-
-/** @addtogroup RTC_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Constants
- * @{
- */
-/* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU
-
-/* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RTC_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU)
-
-#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
- || ((__VALUE__) == LL_RTC_FORMAT_BCD))
-
-#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
-#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
-#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
-#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \
- ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \
- ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \
- ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND))
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RTC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-Initializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are de-initialized
- * - ERROR: RTC registers are not de-initialized
- */
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- LL_RTC_WriteReg(RTCx,CNTL, 0x0000);
- LL_RTC_WriteReg(RTCx,CNTH, 0x0000);
- LL_RTC_WriteReg(RTCx,PRLH, 0x0000);
- LL_RTC_WriteReg(RTCx,PRLL, 0x8000);
- LL_RTC_WriteReg(RTCx,CRH, 0x0000);
- LL_RTC_WriteReg(RTCx,CRL, 0x0020);
-
- /* Reset Tamper and alternate functions configuration register */
- LL_RTC_WriteReg(BKP,RTCCR, 0x00000000U);
- LL_RTC_WriteReg(BKP,CR, 0x00000000U);
- LL_RTC_WriteReg(BKP,CSR, 0x00000000U);
-
- /* Exit Initialization Mode */
- if(LL_RTC_ExitInitMode(RTCx) == ERROR)
- {
- return ERROR;
- }
-
- /* Wait till the RTC RSF flag is set */
- status = LL_RTC_WaitForSynchro(RTCx);
-
- /* Clear RSF Flag */
- LL_RTC_ClearFlag_RS(RTCx);
- }
-
- /* Enable the write protection for RTC registers */
- LL_RTC_EnableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTCx RTC Instance
- * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @note the user should call LL_RTC_StructInit() or the structure of Prescaler
- * need to be initialized before RTC init()
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
- assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource));
- /* Waiting for synchro */
- if(LL_RTC_WaitForSynchro(RTCx) != ERROR)
- {
- /* Set Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Clear Flag Bits */
- LL_RTC_ClearFlag_ALR(RTCx);
- LL_RTC_ClearFlag_OW(RTCx);
- LL_RTC_ClearFlag_SEC(RTCx);
-
- if(RTC_InitStruct->OutPutSource != LL_RTC_CALIB_OUTPUT_NONE)
- {
- /* Disable the selected Tamper Pin */
- LL_RTC_TAMPER_Disable(BKP);
- }
- /* Set the signal which will be routed to RTC Tamper Pin */
- LL_RTC_SetOutputSource(BKP, RTC_InitStruct->OutPutSource);
-
- /* Configure Synchronous and Asynchronous prescaler factor */
- LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
-
- /* Exit Initialization Mode */
- LL_RTC_ExitInitMode(RTCx);
-
- status = SUCCESS;
- }
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
- * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
-{
- /* Set RTC_InitStruct fields to default values */
- RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
- RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE;
-}
-
-/**
- * @brief Set the RTC current time.
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @note The user should call LL_RTC_TIME_StructInit() or the structure
- * of time need to be initialized before time init()
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
- ErrorStatus status = ERROR;
- uint32_t counter_time = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
- assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
- assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
- }
- else
- {
- assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
- assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
- assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
- }
-
- /* Enter Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Check the input parameters format */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \
- ((uint32_t)RTC_TimeStruct->Minutes * 60U) + \
- ((uint32_t)RTC_TimeStruct->Seconds));
- LL_RTC_TIME_Set(RTCx, counter_time);
- }
- else
- {
- counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \
- ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \
- ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))));
- LL_RTC_TIME_Set(RTCx, counter_time);
- }
- status = SUCCESS;
- }
- /* Exit Initialization mode */
- LL_RTC_ExitInitMode(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->Hours = 0U;
- RTC_TimeStruct->Minutes = 0U;
- RTC_TimeStruct->Seconds = 0U;
-}
-
-/**
- * @brief Set the RTC Alarm.
- * @param RTCx RTC Instance
- * @param RTC_Format This parameter can be one of the following values:
- * @arg @ref LL_RTC_FORMAT_BIN
- * @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @note the user should call LL_RTC_ALARM_StructInit() or the structure
- * of Alarm need to be initialized before Alarm init()
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: ALARM registers are configured
- * - ERROR: ALARM registers are not configured
- */
-ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- ErrorStatus status = ERROR;
- uint32_t counter_alarm = 0U;
- /* Check the parameters */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
- assert_param(IS_LL_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == LL_RTC_FORMAT_BIN)
- {
- assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
- assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
- assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
- }
- else
- {
- assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
- assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
- assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
- }
-
- /* Enter Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- /* Check the input parameters format */
- if (RTC_Format != LL_RTC_FORMAT_BIN)
- {
- counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \
- ((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \
- ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds));
- LL_RTC_ALARM_Set(RTCx, counter_alarm);
- }
- else
- {
- counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \
- ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \
- ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))));
- LL_RTC_ALARM_Set(RTCx, counter_alarm);
- }
- status = SUCCESS;
- }
- /* Exit Initialization mode */
- LL_RTC_ExitInitMode(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec /
- * Day = 1st day of the month/Mask = all fields are masked).
- * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
- * @retval None
- */
-void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->AlarmTime.Hours = 0U;
- RTC_AlarmStruct->AlarmTime.Minutes = 0U;
- RTC_AlarmStruct->AlarmTime.Seconds = 0U;
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
-{
- __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
- ErrorStatus status = SUCCESS;
- uint32_t tmp = 0U;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout --;
- }
- tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
-
- /* Disable the write protection for RTC registers */
- LL_RTC_DisableWriteProtection(RTCx);
-
- return status;
-}
-
-/**
- * @brief Exit the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC exited from in Init mode
- * - ERROR: Not applicable
- */
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
-{
- __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
- ErrorStatus status = SUCCESS;
- uint32_t tmp = 0U;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Disable initialization mode */
- LL_RTC_EnableWriteProtection(RTCx);
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout --;
- }
- tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
- return status;
-}
-
-/**
- * @brief Set the Time Counter
- * @param RTCx RTC Instance
- * @param TimeCounter this value can be from 0 to 0xFFFFFFFF
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Counter register configured
- * - ERROR: Not applicable
- */
-ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter)
-{
- ErrorStatus status = ERROR;
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Enter Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- LL_RTC_TIME_Set(RTCx, TimeCounter);
- status = SUCCESS;
- }
- /* Exit Initialization mode */
- LL_RTC_ExitInitMode(RTCx);
-
- return status;
-}
-
-/**
- * @brief Set Alarm Counter.
- * @param RTCx RTC Instance
- * @param AlarmCounter this value can be from 0 to 0xFFFFFFFF
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC exited from in Init mode
- * - ERROR: Not applicable
- */
-ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
-{
- ErrorStatus status = ERROR;
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Enter Initialization mode */
- if (LL_RTC_EnterInitMode(RTCx) != ERROR)
- {
- LL_RTC_ALARM_Set(RTCx, AlarmCounter);
- status = SUCCESS;
- }
- /* Exit Initialization mode */
- LL_RTC_ExitInitMode(RTCx);
-
- return status;
-}
-
-/**
- * @brief Waits until the RTC registers are synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * @ref LL_RTC_DisableWriteProtection before calling this function.
- * @param RTCx RTC Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
-{
- __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
- ErrorStatus status = SUCCESS;
- uint32_t tmp = 0U;
-
- /* Check the parameter */
- assert_param(IS_RTC_ALL_INSTANCE(RTCx));
-
- /* Clear RSF flag */
- LL_RTC_ClearFlag_RS(RTCx);
-
- /* Wait the registers to be synchronised */
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 0U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout--;
- }
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
-
- return (status);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RTC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_sdmmc.c b/lib/hal-stm32f1/source/stm32f1xx_ll_sdmmc.c deleted file mode 100644 index f1b254e5..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_sdmmc.c +++ /dev/null @@ -1,1502 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_sdmmc.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SDIO Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the SDIO peripheral:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### SDMMC peripheral features #####
- ==============================================================================
- [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
- peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
- devices.
-
- [..] The SDMMC features include the following:
- (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
- for three different databus modes: 1-bit (default), 4-bit and 8-bit
- (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
- (+) Full compliance with SD Memory Card Specifications Version 2.0
- (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
- different data bus modes: 1-bit (default) and 4-bit
- (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
- Rev1.1)
- (+) Data transfer up to 48 MHz for the 8 bit mode
- (+) Data and command output enable signals to control external bidirectional drivers.
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- This driver is a considered as a driver of service for external devices drivers
- that interfaces with the SDMMC peripheral.
- According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
- is used in the device's driver to perform SDMMC operations and functionalities.
-
- This driver is almost transparent for the final user, it is only used to implement other
- functionalities of the external device.
-
- [..]
- (+) The SDIO peripheral uses two clock signals:
- (++) SDIO adapter clock (SDIOCLK = HCLK)
- (++) AHB bus clock (HCLK/2)
-
- -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
- Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
-
- (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
- peripheral.
-
- (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
- function and disable it using the function SDIO_PowerState_OFF(SDIOx).
-
- (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
-
- (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
- and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
-
- (+) When using the DMA mode
- (++) Configure the DMA in the MSP layer of the external device
- (++) Active the needed channel Request
- (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
- __SDIO_DMA_DISABLE().
-
- (+) To control the CPSM (Command Path State Machine) and send
- commands to the card use the SDIO_SendCommand(),
- SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
- to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
- to the selected command to be sent.
- The parameters that should be filled are:
- (++) Command Argument
- (++) Command Index
- (++) Command Response type
- (++) Command Wait
- (++) CPSM Status (Enable or Disable).
-
- -@@- To check if the command is well received, read the SDIO_CMDRESP
- register using the SDIO_GetCommandResponse().
- The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
- SDIO_GetResponse() function.
-
- (+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),
- SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
-
- *** Read Operations ***
- =======================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDIO_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be from card (To SDMMC)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDMMC resources to receive the data from the card
- according to selected transfer mode (Refer to Step 8, 9 and 10).
-
- (#) Send the selected Read command (refer to step 11).
-
- (#) Use the SDIO flags/interrupts to check the transfer status.
-
- *** Write Operations ***
- ========================
- [..]
- (#) First, user has to fill the data structure (pointer to
- SDIO_DataInitTypeDef) according to the selected data type to be received.
- The parameters that should be filled are:
- (++) Data TimeOut
- (++) Data Length
- (++) Data Block size
- (++) Data Transfer direction: should be to card (To CARD)
- (++) Data Transfer mode
- (++) DPSM Status (Enable or Disable)
-
- (#) Configure the SDMMC resources to send the data to the card according to
- selected transfer mode.
-
- (#) Send the selected Write command.
-
- (#) Use the SDIO flags/interrupts to check the transfer status.
-
- *** Command management operations ***
- =====================================
- [..]
- (#) The commands used for Read/Write//Erase operations are managed in
- separate functions.
- Each function allows to send the needed command with the related argument,
- then check the response.
- By the same approach, you could implement a command and check the response.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SDMMC_LL SDMMC Low Layer
- * @brief Low layer module for SD
- * @{
- */
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
-static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
-static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization/de-initialization functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the SDMMC according to the specified
- * parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDIOx: Pointer to SDMMC register base
- * @param Init: SDMMC initialization structure
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
- assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
- assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
- assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
- assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
-
- /* Set SDMMC configuration parameters */
- tmpreg |= (Init.ClockEdge |\
- Init.ClockBypass |\
- Init.ClockPowerSave |\
- Init.BusWide |\
- Init.HardwareFlowControl |\
- Init.ClockDiv
- );
-
- /* Write to SDMMC CLKCR */
- MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### I/O operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SDMMC data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
-{
- /* Read data from Rx FIFO */
- return (SDIOx->FIFO);
-}
-
-/**
- * @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDMMC register base
- * @param pWriteData: pointer to data to write
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
-{
- /* Write data to FIFO */
- SDIOx->FIFO = *pWriteData;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the SDMMC data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set SDMMC Power state to ON.
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
-{
- /* Set power state to ON */
- SDIOx->POWER = SDIO_POWER_PWRCTRL;
-
- return HAL_OK;
-}
-
-/**
- * @brief Set SDMMC Power state to OFF.
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
-{
- /* Set power state to OFF */
- SDIOx->POWER = 0x00000000U;
-
- return HAL_OK;
-}
-
-/**
- * @brief Get SDMMC Power state.
- * @param SDIOx: Pointer to SDMMC register base
- * @retval Power status of the controller. The returned value can be one of the
- * following values:
- * - 0x00: Power OFF
- * - 0x02: Power UP
- * - 0x03: Power ON
- */
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
-{
- return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
-}
-
-/**
- * @brief Configure the SDMMC command path according to the specified parameters in
- * SDIO_CmdInitTypeDef structure and send the command
- * @param SDIOx: Pointer to SDMMC register base
- * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
- * the configuration information for the SDMMC command
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
- assert_param(IS_SDIO_RESPONSE(Command->Response));
- assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
- assert_param(IS_SDIO_CPSM(Command->CPSM));
-
- /* Set the SDMMC Argument value */
- SDIOx->ARG = Command->Argument;
-
- /* Set SDMMC command parameters */
- tmpreg |= (uint32_t)(Command->CmdIndex |\
- Command->Response |\
- Command->WaitForInterrupt |\
- Command->CPSM);
-
- /* Write to SDMMC CMD register */
- MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-}
-
-/**
- * @brief Return the command index of last command for which response received
- * @param SDIOx: Pointer to SDMMC register base
- * @retval Command index of the last command response received
- */
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
-{
- return (uint8_t)(SDIOx->RESPCMD);
-}
-
-
-/**
- * @brief Return the response received from the card for the last command
- * @param SDIOx: Pointer to SDMMC register base
- * @param Response: Specifies the SDMMC response register.
- * This parameter can be one of the following values:
- * @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP2: Response Register 2
- * @arg SDIO_RESP3: Response Register 3
- * @arg SDIO_RESP4: Response Register 4
- * @retval The Corresponding response register value
- */
-uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
-{
- __IO uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_SDIO_RESP(Response));
-
- /* Get the response */
- tmp = (uint32_t)&(SDIOx->RESP1) + Response;
-
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @brief Configure the SDMMC data path according to the specified
- * parameters in the SDIO_DataInitTypeDef.
- * @param SDIOx: Pointer to SDMMC register base
- * @param Data : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDMMC data.
- * @retval HAL status
- */
-HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
-{
- uint32_t tmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
- assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
- assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
- assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
- assert_param(IS_SDIO_DPSM(Data->DPSM));
-
- /* Set the SDMMC Data TimeOut value */
- SDIOx->DTIMER = Data->DataTimeOut;
-
- /* Set the SDMMC DataLength value */
- SDIOx->DLEN = Data->DataLength;
-
- /* Set the SDMMC data configuration parameters */
- tmpreg |= (uint32_t)(Data->DataBlockSize |\
- Data->TransferDir |\
- Data->TransferMode |\
- Data->DPSM);
-
- /* Write to SDMMC DCTRL */
- MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
- return HAL_OK;
-
-}
-
-/**
- * @brief Returns number of remaining data bytes to be transferred.
- * @param SDIOx: Pointer to SDMMC register base
- * @retval Number of remaining data bytes to be transferred
- */
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
-{
- return (SDIOx->DCOUNT);
-}
-
-/**
- * @brief Get the FIFO data
- * @param SDIOx: Pointer to SDMMC register base
- * @retval Data received
- */
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
-{
- return (SDIOx->FIFO);
-}
-
-/**
- * @brief Sets one of the two options of inserting read wait interval.
- * @param SDIOx: Pointer to SDMMC register base
- * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
- * This parameter can be:
- * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
- * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
- * @retval None
- */
-HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
-{
- /* Check the parameters */
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- /* Set SDMMC read wait mode */
- MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Commands management functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the needed commands.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Send the Data Block Lenght command and check the response
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Read Single Block command and check the response
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Read Multi Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Write Single Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Write Multi Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Start Address Erase command for SD and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the End Address Erase command for SD and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Start Address Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the End Address Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Set Block Size for Card */
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Stop Transfer command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD12 STOP_TRANSMISSION */
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Select Deselect command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @param addr: Address of the card to be selected
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD7 SDMMC_SEL_DESEL_CARD */
- sdmmc_cmdinit.Argument = (uint32_t)Addr;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Go Idle State command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdError(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Operating Condition command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD8 to verify SD card interface operating condition */
- /* Argument: - [31:12]: Reserved (shall be set to '0')
- - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
- - [7:0]: Check Pattern (recommended 0xAA) */
- /* CMD Response: R7 */
- sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp7(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Application command to verify that that the next command
- * is an application specific com-mand rather than a standard command
- * and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- /* If there is a HAL_ERROR, it is a MMC card, else
- it is a SD card: SD card 2.0 (voltage range mismatch)
- or SD card 1.x */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the command asking the accessed card to send its operating
- * condition register (OCR)
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp3(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Bus Width command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send SCR command and check the response.
- * @param SDIOx: Pointer to SDMMC register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD51 SD_APP_SEND_SCR */
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CID command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD2 ALL_SEND_CID */
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp2(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CSD command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD9 SEND_CSD */
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp2(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Send CSD command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- /* Send CMD3 SD_CMD_SET_REL_ADDR */
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Status command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Send the Status register command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @retval HAL status
- */
-uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = 0U;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @brief Sends host capacity support information and activates the card's
- * initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
- * @retval HAL status
- */
-uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp3(SDIOx);
-
- return errorstate;
-}
-
-/**
- * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
- * @retval HAL status
- */
-uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
-{
- SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
- sdmmc_cmdinit.Argument = Argument;
- sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
- sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
- sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
- sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
-
- /* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
-
- return errorstate;
-}
-
-/**
- * @}
- */
-
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
- * @{
- */
-
-/**
- * @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
-
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R1 response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
-{
- uint32_t response_r1;
-
- /* 8 is the number of required instructions cycles for the below loop statement.
- The Timeout is expressed in ms */
- register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
- if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* Check response received is of desired command */
- if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
- {
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
-
- /* We have received response, retrieve it for analysis */
- response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
-
- if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
- {
- return SDMMC_ERROR_NONE;
- }
- else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
- {
- return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
- }
- else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
- {
- return SDMMC_ERROR_ADDR_MISALIGNED;
- }
- else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
- {
- return SDMMC_ERROR_BLOCK_LEN_ERR;
- }
- else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
- {
- return SDMMC_ERROR_ERASE_SEQ_ERR;
- }
- else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
- {
- return SDMMC_ERROR_BAD_ERASE_PARAM;
- }
- else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
- {
- return SDMMC_ERROR_WRITE_PROT_VIOLATION;
- }
- else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
- {
- return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
- {
- return SDMMC_ERROR_COM_CRC_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
- {
- return SDMMC_ERROR_ILLEGAL_CMD;
- }
- else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
- {
- return SDMMC_ERROR_CARD_ECC_FAILED;
- }
- else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
- {
- return SDMMC_ERROR_CC_ERR;
- }
- else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
- {
- return SDMMC_ERROR_STREAM_READ_UNDERRUN;
- }
- else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
- {
- return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
- }
- else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
- {
- return SDMMC_ERROR_CID_CSD_OVERWRITE;
- }
- else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
- {
- return SDMMC_ERROR_WP_ERASE_SKIP;
- }
- else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
- {
- return SDMMC_ERROR_CARD_ECC_DISABLED;
- }
- else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
- {
- return SDMMC_ERROR_ERASE_RESET;
- }
- else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
- {
- return SDMMC_ERROR_AKE_SEQ_ERR;
- }
- else
- {
- return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
-}
-
-/**
- * @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
- if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
- else
- {
- /* No error flag set */
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
- }
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
- if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else
-
- {
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
- }
-
- return SDMMC_ERROR_NONE;
-}
-
-/**
- * @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
- * address RCA
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
-{
- uint32_t response_r1;
-
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
- if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
- else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
- {
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
-
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* Check response received is of desired command */
- if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
- {
- return SDMMC_ERROR_CMD_CRC_FAIL;
- }
-
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
-
- /* We have received response, retrieve it. */
- response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
-
- if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
- {
- *pRCA = (uint16_t) (response_r1 >> 16);
-
- return SDMMC_ERROR_NONE;
- }
- else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
- {
- return SDMMC_ERROR_ILLEGAL_CMD;
- }
- else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
- {
- return SDMMC_ERROR_COM_CRC_FAILED;
- }
- else
- {
- return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
-}
-
-/**
- * @brief Checks for error conditions for R7 response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDIO_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
- if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
- {
- /* Card is SD V2.0 compliant */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
-
- return SDMMC_ERROR_CMD_RSP_TIMEOUT;
- }
-
- if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
- {
- /* Card is SD V2.0 compliant */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
- }
-
- return SDMMC_ERROR_NONE;
-
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_spi.c b/lib/hal-stm32f1/source/stm32f1xx_ll_spi.c deleted file mode 100644 index 332fdb36..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_spi.c +++ /dev/null @@ -1,562 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_spi.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief SPI LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_spi.h"
-#include "stm32f1xx_ll_bus.h"
-#include "stm32f1xx_ll_rcc.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @addtogroup SPI_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
- * @{
- */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
- SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
- SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
- SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
- SPI_CR1_BIDIMODE)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
- * @{
- */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
- if (SPIx == SPI1)
- {
- /* Force reset of SPI clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- /* Release reset of SPI clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- status = SUCCESS;
- }
-#endif /* SPI1 */
-#if defined(SPI2)
- if (SPIx == SPI2)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- status = SUCCESS;
- }
-#endif /* SPI2 */
-#if defined(SPI3)
- if (SPIx == SPI3)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- status = SUCCESS;
- }
-#endif /* SPI3 */
-
- return status;
-}
-
-/**
- * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
- */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the SPI Instance SPIx*/
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
- /* Check the SPI parameters from SPI_InitStruct*/
- assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
- assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
- assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
- assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
- assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
- assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
- assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
- assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
- assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
- if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx CR1 Configuration ------------------------
- * Configure SPIx CR1 with parameters:
- * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
- * - Master/Slave Mode: SPI_CR1_MSTR bit
- * - DataWidth: SPI_CR1_DFF bit
- * - ClockPolarity: SPI_CR1_CPOL bit
- * - ClockPhase: SPI_CR1_CPHA bit
- * - NSS management: SPI_CR1_SSM bit
- * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
- * - BitOrder: SPI_CR1_LSBFIRST bit
- * - CRCCalculation: SPI_CR1_CRCEN bit
- */
- MODIFY_REG(SPIx->CR1,
- SPI_CR1_CLEAR_MASK,
- SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
- SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
- SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
- SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
- /*---------------------------- SPIx CR2 Configuration ------------------------
- * Configure SPIx CR2 with parameters:
- * - NSS management: SSOE bit
- */
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
-
- /*---------------------------- SPIx CRCPR Configuration ----------------------
- * Configure SPIx CRCPR with parameters:
- * - CRCPoly: CRCPOLY[15:0] bits
- */
- if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
- LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
- }
- status = SUCCESS;
- }
-
-#if defined (SPI_I2S_SUPPORT)
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
- return status;
-}
-
-/**
- * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- /* Set SPI_InitStruct fields to default values */
- SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
- SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
- SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
- SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
- SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
- SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
- SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
- SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
- SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
- SPI_InitStruct->CRCPoly = 7U;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
- * @{
- */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
- SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK 0x0002U
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
- * @{
- */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI/I2S registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
- return LL_SPI_DeInit(SPIx);
-}
-
-/**
- * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are Initialized
- * - ERROR: SPI registers are not Initialized
- */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- uint32_t sourceclock = 0U;
-#if defined(I2S2_I2S3_CLOCK_FEATURE)
-#else
- LL_RCC_ClocksTypeDef rcc_clocks;
-#endif /* I2S2_I2S3_CLOCK_FEATURE */
- ErrorStatus status = ERROR;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
- assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
- assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
- assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
- assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
- assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
- if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx I2SCFGR Configuration --------------------
- * Configure SPIx I2SCFGR with parameters:
- * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
- * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
- * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
- * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
- */
-
- /* Write to SPIx I2SCFGR */
- MODIFY_REG(SPIx->I2SCFGR,
- I2S_I2SCFGR_CLEAR_MASK,
- I2S_InitStruct->Mode | I2S_InitStruct->Standard |
- I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
- SPI_I2SCFGR_I2SMOD);
-
- /*---------------------------- SPIx I2SPR Configuration ----------------------
- * Configure SPIx I2SPR with parameters:
- * - MCLKOutput: SPI_I2SPR_MCKOE bit
- * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
- */
-
- /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
- * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
- */
- if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing)
- * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
- */
- if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 2U;
- }
-#if defined(I2S2_I2S3_CLOCK_FEATURE)
- /* If an external I2S clock has to be used, the specific define should be set
- in the project configuration or in the stm32f1xx_ll_rcc.h file */
- if(SPIx == SPI2)
- {
- /* Get the I2S source clock value */
- sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
- }
- else /* SPI3 */
- {
- /* Get the I2S source clock value */
- sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S3_CLKSOURCE);
- }
-#else
- /* I2S Clock source is System clock: Get System Clock frequency */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = rcc_clocks.SYSCLK_Frequency;
-#endif /* I2S2_I2S3_CLOCK_FEATURE */
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
- status = SUCCESS;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- /*--------------- Reset I2S init structure parameters values -----------------*/
- I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
- I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
- I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
- I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
- I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
- I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
-}
-
-/**
- * @brief Set linear and parity prescaler.
- * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
- * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
- * @param SPIx SPI Instance
- * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
- assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
- /* Write to SPIx I2SPR */
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_tim.c b/lib/hal-stm32f1/source/stm32f1xx_ll_tim.c deleted file mode 100644 index 3fac99db..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_tim.c +++ /dev/null @@ -1,1216 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_tim.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief TIM LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_tim.h"
-#include "stm32f1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
-
-/** @addtogroup TIM_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
- * @{
- */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
-
-#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
-
-#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
-
-#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
-
-#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
-
-#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
- * @{
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Set TIMx registers to their reset values.
- * @param TIMx Timer instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: invalid TIMx instance
- */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
- ErrorStatus result = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
-
- if (TIMx == TIM2)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
- }
-#if defined(TIM1)
- else if (TIMx == TIM1)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
- }
-#endif
-#if defined(TIM3)
- else if (TIMx == TIM3)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
- }
-#endif
-#if defined(TIM4)
- else if (TIMx == TIM4)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
- }
-#endif
-#if defined(TIM5)
- else if (TIMx == TIM5)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
- }
-#endif
-#if defined(TIM6)
- else if (TIMx == TIM6)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
- }
-#endif
-#if defined (TIM7)
- else if (TIMx == TIM7)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
- }
-#endif
-#if defined(TIM8)
- else if (TIMx == TIM8)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
- }
-#endif
-#if defined(TIM9)
- else if (TIMx == TIM9)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
- }
-#endif
-#if defined(TIM10)
- else if (TIMx == TIM10)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
- }
-#endif
-#if defined(TIM11)
- else if (TIMx == TIM11)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
- }
-#endif
-#if defined(TIM12)
- else if (TIMx == TIM12)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
- }
-#endif
-#if defined(TIM13)
- else if (TIMx == TIM13)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
- }
-#endif
-#if defined(TIM14)
- else if (TIMx == TIM14)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
- }
-#endif
-#if defined(TIM15)
- else if (TIMx == TIM15)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
- }
-#endif
-#if defined(TIM16)
- else if (TIMx == TIM16)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
- }
-#endif
-#if defined(TIM17)
- else if (TIMx == TIM17)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
- }
-#endif
- else
- {
- result = ERROR;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the time base unit configuration data structure
- * to their default values.
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
- * @retval None
- */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- /* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000;
- TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
- TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
-}
-
-/**
- * @brief Configure the TIMx time base unit.
- * @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- uint32_t tmpcr1 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
- assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
- tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
- }
-
- /* Write to TIMx CR1 */
- LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
- /* Set the Autoreload value */
- LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
- /* Set the Prescaler value */
- LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter value (if applicable) immediately */
- LL_TIM_GenerateEvent_UPDATE(TIMx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx output channel configuration data
- * structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
- * @retval None
- */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- /* Set the default configuration */
- TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
- TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->CompareValue = 0x00000000U;
- TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
-}
-
-/**
- * @brief Configure the TIMx output channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = OC1Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = OC2Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = OC3Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = OC4Config(TIMx, TIM_OC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the TIMx input channel configuration data
- * structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
- * @retval None
- */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
- TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
- TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the TIMx input channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = IC1Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = IC2Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = IC3Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = IC4Config(TIMx, TIM_IC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
- * @retval None
- */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- /* Set the default configuration */
- TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
- TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the encoder interface of the timer instance.
- * @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Configure TI1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
- /* Configure TI2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
- /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Set encoder mode */
- LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx Hall sensor interface configuration data
- * structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
- * @retval None
- */
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- /* Set the default configuration */
- TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_HallSensorInitStruct->CommutationDelay = 0U;
-}
-
-/**
- * @brief Configure the Hall sensor interface of the timer instance.
- * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
- * to the TI1 input channel
- * @note TIMx slave mode controller is configured in reset mode.
- Selected internal trigger is TI1F_ED.
- * @note Channel 1 is configured as input, IC1 is mapped on TRC.
- * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
- * between 2 changes on the inputs. It gives information about motor speed.
- * @note Channel 2 is configured in output PWM 2 mode.
- * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
- * @note OC2REF is selected as trigger output on TRGO.
- * @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
-
- /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
- tmpcr2 |= TIM_CR2_TI1S;
-
- /* OC2REF signal is used as trigger output (TRGO) */
- tmpcr2 |= LL_TIM_TRGO_OC2REF;
-
- /* Configure the slave mode controller */
- tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
- tmpsmcr |= LL_TIM_TS_TI1F_ED;
- tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
-
- /* Configure input channel 1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
-
- /* Configure input channel 2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
- tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
-
- /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx SMCR */
- LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- /* Write to TIMx CCR2 */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the Break and Dead Time configuration data structure
- * to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
- * @retval None
- */
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
- TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
- TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
- TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
- TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
- TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
-}
-
-/**
- * @brief Configure the Break and Dead Time feature of the timer instance.
- * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
- * depending on the LOCK configuration, it can be necessary to configure all of
- * them during the first write access to the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Break and Dead Time is initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- uint32_t tmpbdtr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
- assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
- assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
- assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
- assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
- assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-
- /* Set TIMx_BDTR */
- LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
- return SUCCESS;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
- * @{
- */
-/**
- * @brief Configure the TIMx output channel 1.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
- /* Set the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 2.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 3.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 4.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-
-/**
- * @brief Configure the TIMx input channel 1.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC1E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC1P | TIM_CCER_CC1NP),
- (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 2.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC2P | TIM_CCER_CC2NP),
- ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 3.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC3E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC3P | TIM_CCER_CC3NP),
- ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 4.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC4E Bit */
- MODIFY_REG(TIMx->CCER,
- TIM_CCER_CC4P,
- ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
- return SUCCESS;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_usart.c b/lib/hal-stm32f1/source/stm32f1xx_ll_usart.c deleted file mode 100644 index 7635afdd..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_usart.c +++ /dev/null @@ -1,451 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_usart.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief USART LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_usart.h"
-#include "stm32f1xx_ll_rcc.h"
-#include "stm32f1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @addtogroup USART_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
- * @{
- */
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- * divided by the smallest oversampling used on the USART (i.e. 8) */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize USART registers (Registers restored to their default values).
- * @param USARTx USART Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are de-initialized
- * - ERROR: USART registers are not de-initialized
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
-
- if (USARTx == USART1)
- {
- /* Force reset of USART clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
-
- /* Release reset of USART clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
- }
- else if (USARTx == USART2)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
- }
-#if defined(USART3)
- else if (USARTx == USART3)
- {
- /* Force reset of USART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
-
- /* Release reset of USART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
- }
-#endif /* USART3 */
-#if defined(UART4)
- else if (USARTx == UART4)
- {
- /* Force reset of UART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
-
- /* Release reset of UART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
- }
-#endif /* UART4 */
-#if defined(UART5)
- else if (USARTx == UART5)
- {
- /* Force reset of UART clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
-
- /* Release reset of UART clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
- }
-#endif /* UART5 */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize USART registers according to the specified
- * parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
- * @param USARTx USART Instance
- * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
- * that contains the configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers are initialized according to USART_InitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
- ErrorStatus status = ERROR;
- uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
- LL_RCC_ClocksTypeDef rcc_clocks;
-
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
- assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
- assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
- assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
- assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
- assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
-#if defined(USART_CR1_OVER8)
- assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-#endif /* USART_OverSampling_Feature */
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR1 Configuration -----------------------
- * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
- * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
- * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
- * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
- * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
- */
-#if defined(USART_CR1_OVER8)
- MODIFY_REG(USARTx->CR1,
- (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
- (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
- USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-#else
- MODIFY_REG(USARTx->CR1,
- (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
- USART_CR1_TE | USART_CR1_RE),
- (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
- USART_InitStruct->TransferDirection));
-#endif /* USART_OverSampling_Feature */
-
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Stop bits) with parameters:
- * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
- * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
- */
- LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
- /*---------------------------- USART CR3 Configuration -----------------------
- * Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
- */
- LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
- /*---------------------------- USART BRR Configuration -----------------------
- * Retrieve Clock frequency used for USART Peripheral
- */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
- if (USARTx == USART1)
- {
- periphclk = rcc_clocks.PCLK2_Frequency;
- }
- else if (USARTx == USART2)
- {
- periphclk = rcc_clocks.PCLK1_Frequency;
- }
-#if defined(USART3)
- else if (USARTx == USART3)
- {
- periphclk = rcc_clocks.PCLK1_Frequency;
- }
-#endif /* USART3 */
-#if defined(UART4)
- else if (USARTx == UART4)
- {
- periphclk = rcc_clocks.PCLK1_Frequency;
- }
-#endif /* UART4 */
-#if defined(UART5)
- else if (USARTx == UART5)
- {
- periphclk = rcc_clocks.PCLK1_Frequency;
- }
-#endif /* UART5 */
- else
- {
- /* Nothing to do, as error code is already assigned to ERROR value */
- }
-
- /* Configure the USART Baud Rate :
- - valid baud rate value (different from 0) is required
- - Peripheral clock as returned by RCC service, should be valid (different from 0).
- */
- if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
- && (USART_InitStruct->BaudRate != 0U))
- {
- status = SUCCESS;
-#if defined(USART_CR1_OVER8)
- LL_USART_SetBaudRate(USARTx,
- periphclk,
- USART_InitStruct->OverSampling,
- USART_InitStruct->BaudRate);
-#else
- LL_USART_SetBaudRate(USARTx,
- periphclk,
- USART_InitStruct->BaudRate);
-#endif /* USART_OverSampling_Feature */
- }
- }
- /* Endif (=> USART not in Disabled state => return ERROR) */
-
- return (status);
-}
-
-/**
- * @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
- /* Set USART_InitStruct fields to default values */
- USART_InitStruct->BaudRate = 9600U;
- USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
- USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
- USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
- USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
- USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
-#if defined(USART_CR1_OVER8)
- USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
-#endif /* USART_OverSampling_Feature */
-}
-
-/**
- * @brief Initialize USART Clock related settings according to the
- * specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param USARTx USART Instance
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
- * that contains the Clock configuration information for the specified USART peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
- * - ERROR: Problem occurred during USART Registers initialization
- */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check USART Instance and Clock signal output parameters */
- assert_param(IS_UART_INSTANCE(USARTx));
- assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
- /* USART needs to be in disabled state, in order to be able to configure some bits in
- CRx registers */
- if (LL_USART_IsEnabled(USARTx) == 0U)
- {
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
-
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
- }
- /* Else (USART not in Disabled state => return ERROR */
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
- /* Set LL_USART_ClockInitStruct fields with default values */
- USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_usb.c b/lib/hal-stm32f1/source/stm32f1xx_ll_usb.c deleted file mode 100644 index 956e5fad..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_usb.c +++ /dev/null @@ -1,2338 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_usb.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief USB Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the USB Peripheral Controller:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
- (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
- (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup USB_LL USB Low Layer
- * @brief Low layer module for USB_FS and USB_OTG_FS drivers
- * @{
- */
-
-#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-#if defined (USB_OTG_FS)
-/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions
- * @{
- */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-/**
- * @}
- */
-#endif /* USB_OTG_FS */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
- * @{
- */
-
-/** @defgroup USB_LL_Exported_Functions_Group1 Peripheral Control functions
- * @brief management functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the PCD data
- transfers.
-
-@endverbatim
- * @{
- */
-
-/*==============================================================================
- USB OTG FS peripheral available on STM32F105xx and STM32F107xx devices
-==============================================================================*/
-#if defined (USB_OTG_FS)
-
-/**
- * @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(cfg);
-
- /* Select FS Embedded PHY */
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-
- /* Reset after a PHY select and set Host mode */
- USB_CoreReset(USBx);
-
- /* Deactivate the power down*/
- USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EnableGlobalInt
- * Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
- USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
- return HAL_OK;
-}
-
-/**
- * @brief USB_DisableGlobalInt
- * Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
-{
- USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
- * This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE: Peripheral mode mode
- * @arg USB_HOST_MODE: Host mode
- * @arg USB_DRD_MODE: Dual Role Device mode
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode)
-{
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
-
- if ( mode == USB_HOST_MODE)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
- }
- else if (mode == USB_DEVICE_MODE)
- {
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
- }
- HAL_Delay(50);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevInit : Initializes the USB_OTG controller registers
- * for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- uint32_t index = 0;
-
- for (index = 0; index < 15 ; index++)
- {
- USBx->DIEPTXF[index] = 0;
- }
-
- /*Activate VBUS Sensing B */
- USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-
- /* Restart the Phy Clock */
- USBx_PCGCCTL = 0;
-
- /* Device mode configuration */
- USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-
- /* Set Full speed phy */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
-
- /* Flush the FIFOs */
- USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
-
- /* Clear all pending Device Interrupts */
- USBx_DEVICE->DIEPMSK = 0;
- USBx_DEVICE->DOEPMSK = 0;
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
- USBx_DEVICE->DAINTMSK = 0;
-
- for (index = 0; index < cfg.dev_endpoints; index++)
- {
- if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
- {
- USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
- }
- else
- {
- USBx_INEP(index)->DIEPCTL = 0;
- }
-
- USBx_INEP(index)->DIEPTSIZ = 0;
- USBx_INEP(index)->DIEPINT = 0xFF;
- }
-
- for (index = 0; index < cfg.dev_endpoints; index++)
- {
- if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
- {
- USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
- }
- else
- {
- USBx_OUTEP(index)->DOEPCTL = 0;
- }
-
- USBx_OUTEP(index)->DOEPTSIZ = 0;
- USBx_OUTEP(index)->DOEPINT = 0xFF;
- }
-
- USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-
- /* Disable all interrupts. */
- USBx->GINTMSK = 0;
-
- /* Clear any pending interrupts */
- USBx->GINTSTS = 0xBFFFFFFF;
-
- /* Enable the common interrupts */
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-
- /* Enable interrupts matching to the Device mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
- USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
- USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
- USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
- if(cfg.Sof_enable)
- {
- USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
- }
-
- if (cfg.vbus_sensing_enable == ENABLE)
- {
- USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
- * This parameter can be a value from 1 to 15
- 15 means Flush all Tx FIFOs
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
-{
- uint32_t count = 0;
-
- USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)(num << 6));
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t count = 0;
-
- USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
- * depending the PHY type and the enumeration speed of the device.
- * @param USBx : Selected device
- * @param speed : device speed
- * This parameter can be one of the these values:
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- * @retval Hal status
- */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- USBx_DEVICE->DCFG |= speed;
- return HAL_OK;
-}
-
-/**
- * @brief USB_GetDevSpeed :Return the Dev Speed
- * @param USBx : Selected device
- * @retval speed : device speed
- * This parameter can be one of the these values:
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
-{
- uint8_t speed = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
- ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
- {
- speed = USB_OTG_SPEED_FULL;
- }
- else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- speed = USB_OTG_SPEED_LOW;
- }
-
- return speed;
-}
-
-/**
- * @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- if (ep->is_in)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
- /* Set initial data PID. */
- if (ep->type == EP_TYPE_BULK )
- {
- ep->data_pid_start = 0;
- }
-
- if (ep->is_in == 1)
- {
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
- }
- }
- else
- {
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* Read DEPCTLn register */
- if (ep->is_in == 1)
- {
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
- }
- else
- {
- USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
- uint16_t pktcnt = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
- }
- }
-
- if (ep->type != EP_TYPE_ISOC)
- {
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
- }
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
- }
- else
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
- }
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
- if (ep->type == EP_TYPE_ISOC)
- {
- USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len);
- }
- }
- else /* OUT endpoint */
- {
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
- if (ep->xfer_len == 0)
- {
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
- }
- else
- {
- pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
- }
- else
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
- }
- }
- /* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19));
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- }
- else
- {
- /* Program the transfer size and packet count
- * as follows: xfersize = N * maxpacket +
- * short_packet pktcnt = N + (short_packet
- * exist ? 1 : 0)
- */
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-
- if(ep->xfer_len > ep->maxpacket)
- {
- ep->xfer_len = ep->maxpacket;
- }
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19));
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
- }
-
- /* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
- {
- USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
- }
- else /* OUT endpoint */
- {
- /* Program the transfer size and packet count as follows:
- * pktcnt = N
- * xfersize = N * maxpacket
- */
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
- if (ep->xfer_len > 0)
- {
- ep->xfer_len = ep->maxpacket;
- }
-
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
- /* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
-{
- uint32_t count32b = 0 , index = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- count32b = (len + 3) / 4;
- for (index = 0; index < count32b; index++, src += 4)
- {
- USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param dest : destination pointer
- * @param len : Number of bytes to read
- * @retval pointer to destination buffer
- */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
-{
- uint32_t index = 0;
- uint32_t count32b = (len + 3) / 4;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- for ( index = 0; index < count32b; index++, dest += 4 )
- {
- *(__packed uint32_t *)dest = USBx_DFIFO(0);
-
- }
- return ((void *)dest);
-}
-
-/**
- * @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- if (ep->is_in == 1)
- {
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
- {
- USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
- }
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
- }
- else
- {
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
- {
- USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
- }
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- if (ep->is_in == 1)
- {
- USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
- }
- else
- {
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
- {
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t index = 0;
-
- /* Clear Pending interrupt */
- for (index = 0; index < 15 ; index++)
- {
- USBx_INEP(index)->DIEPINT = 0xFF;
- USBx_OUTEP(index)->DOEPINT = 0xFF;
- }
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
-
- /* Clear interrupt masks */
- USBx_DEVICE->DIEPMSK = 0;
- USBx_DEVICE->DOEPMSK = 0;
- USBx_DEVICE->DAINTMSK = 0;
-
- /* Flush the FIFO */
- USB_FlushRxFifo(USBx);
- USB_FlushTxFifo(USBx , 0x10 );
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
- * This parameter can be a value from 0 to 255
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(address);
- USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
- USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
- HAL_Delay(3);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
- HAL_Delay(3);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t tmpreg = 0;
-
- tmpreg = USBx->GINTSTS;
- tmpreg &= USBx->GINTMSK;
- return tmpreg;
-}
-
-/**
- * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t tmpreg = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- tmpreg = USBx_DEVICE->DAINT;
- tmpreg &= USBx_DEVICE->DAINTMSK;
- return ((tmpreg & 0xffff0000) >> 16);
-}
-
-/**
- * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t tmpreg = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- tmpreg = USBx_DEVICE->DAINT;
- tmpreg &= USBx_DEVICE->DAINTMSK;
- return ((tmpreg & 0xFFFF));
-}
-
-/**
- * @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device OUT EP Interrupt register
- */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- uint32_t tmpreg = 0;
- tmpreg = USBx_OUTEP(epnum)->DOEPINT;
- tmpreg &= USBx_DEVICE->DOEPMSK;
- return tmpreg;
-}
-
-/**
- * @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device IN EP Interrupt register
- */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
-{
- uint32_t tmpreg = 0, msk = 0, emp = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- msk = USBx_DEVICE->DIEPMSK;
- emp = USBx_DEVICE->DIEPEMPMSK;
- msk |= ((emp >> epnum) & 0x1) << 7;
- tmpreg = USBx_INEP(epnum)->DIEPINT & msk;
- return tmpreg;
-}
-
-/**
- * @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx : Selected device
- * @param interrupt : interrupt flag
- * @retval None
- */
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
-{
- USBx->GINTSTS |= interrupt;
-}
-
-/**
- * @brief Returns USB core mode
- * @param USBx : Selected device
- * @retval return core mode : Host or Device
- * This parameter can be one of the these values:
- * 0 : Host
- * 1 : Device
- */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- return ((USBx->GINTSTS ) & 0x1);
-}
-
-/**
- * @brief Activate EP0 for Setup transactions
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* Set the MPS of the IN EP based on the enumeration speed */
- USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
- {
- USBx_INEP(0)->DIEPCTL |= 3;
- }
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
-
- return HAL_OK;
-}
-
-/**
- * @brief Prepare the EP0 to start the first control setup
- * @param USBx : Selected device
- * @param psetup : pointer to setup packet
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(psetup);
- USBx_OUTEP(0)->DOEPTSIZ = 0;
- USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
- USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
- USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_HostInit : Initializes the USB OTG controller registers
- * for Host mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
-{
- uint32_t index = 0;
-
- /* Restart the Phy Clock */
- USBx_PCGCCTL = 0;
-
- /* no VBUS sensing*/
- USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
- USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
-
- /* Disable the FS/LS support mode only */
- if((cfg.speed == USB_OTG_SPEED_FULL)&&
- (USBx != USB_OTG_FS))
- {
- USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
- }
- else
- {
- USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
- }
-
- /* Make sure the FIFOs are flushed. */
- USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
-
- /* Clear all pending HC Interrupts */
- for (index = 0; index < cfg.Host_channels; index++)
- {
- USBx_HC(index)->HCINT = 0xFFFFFFFF;
- USBx_HC(index)->HCINTMSK = 0;
- }
-
- /* Enable VBUS driving */
- USB_DriveVbus(USBx, 1);
-
- HAL_Delay(200);
-
- /* Disable all interrupts. */
- USBx->GINTMSK = 0;
-
- /* Clear any pending interrupts */
- USBx->GINTSTS = 0xFFFFFFFF;
-
- if(USBx == USB_OTG_FS)
- {
- /* set Rx FIFO size */
- USBx->GRXFSIZ = (uint32_t )0x80;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
- USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
- }
-
- /* Enable the common interrupts */
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-
- /* Enable interrupts matching to the Host mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
- USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
- USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
- * HCFG register on the PHY type and set the right frame interval
- * @param USBx : Selected device
- * @param freq : clock frequency
- * This parameter can be one of the these values:
- * HCFG_48_MHZ : Full Speed 48 MHz Clock
- * HCFG_6_MHZ : Low Speed 6 MHz Clock
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
- USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-
- if (freq == HCFG_48_MHZ)
- {
- USBx_HOST->HFIR = (uint32_t)48000;
- }
- else if (freq == HCFG_6_MHZ)
- {
- USBx_HOST->HFIR = (uint32_t)6000;
- }
- return HAL_OK;
-}
-
-/**
-* @brief USB_OTG_ResetPort : Reset Host Port
- * @param USBx : Selected device
- * @retval HAL status
- * @note : (1)The application must wait at least 10 ms
- * before clearing the reset bit.
- */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
-{
- __IO uint32_t hprt0 = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- hprt0 = USBx_HPRT0;
-
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
- HAL_Delay (10); /* See Note #1 */
- USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
- return HAL_OK;
-}
-
-/**
- * @brief USB_DriveVbus : activate or de-activate vbus
- * @param state : VBUS state
- * This parameter can be one of the these values:
- * 0 : VBUS Active
- * 1 : VBUS Inactive
- * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
-{
- __IO uint32_t hprt0 = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- hprt0 = USBx_HPRT0;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
- {
- USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
- }
- if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
- {
- USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
- }
- return HAL_OK;
-}
-
-/**
- * @brief Return Host Core speed
- * @param USBx : Selected device
- * @retval speed : Host speed
- * This parameter can be one of the these values:
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
-{
- __IO uint32_t hprt0 = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- hprt0 = USBx_HPRT0;
- return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
-}
-
-/**
- * @brief Return Host Current Frame number
- * @param USBx : Selected device
- * @retval current frame number
-*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
-}
-
-/**
- * @brief Initialize a host channel
- * @param USBx : Selected device
- * @param ch_num : Channel number
- * This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
- * This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
- * This parameter can be a value from 0 to 255
- * @param speed : Current device speed
- * This parameter can be one of the these values:
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochronous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
- * This parameter can be a value from 0 to32K
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
- /* Clear old interrupt conditions for this host channel. */
- USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-
- /* Enable channel interrupts required for this transfer. */
- switch (ep_type)
- {
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_NAKM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- break;
-
- case EP_TYPE_INTR:
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_NAKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
-
- break;
-
- case EP_TYPE_ISOC:
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_ACKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
- {
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
- }
- break;
- }
-
- /* Enable the top level host channel interrupt. */
- USBx_HOST->HAINTMSK |= (1 << ch_num);
-
- /* Make sure host channel interrupts are enabled. */
- USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-
- /* Program the HCCHAR register */
- USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
- (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
- ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
- (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
- ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
- (mps & USB_OTG_HCCHAR_MPSIZ));
-
- if (ep_type == EP_TYPE_INTR)
- {
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Start a transfer over a host channel
- * @param USBx : Selected device
- * @param hc : pointer to host channel structure
- * @retval HAL state
- */
-#if defined (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc)
-{
- uint8_t is_oddframe = 0;
- uint16_t len_words = 0;
- uint16_t num_packets = 0;
- uint16_t max_hc_pkt_count = 256;
- uint32_t tmpreg = 0;
-
- /* Compute the expected number of packets associated to the transfer */
- if (hc->xfer_len > 0)
- {
- num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-
- if (num_packets > max_hc_pkt_count)
- {
- num_packets = max_hc_pkt_count;
- hc->xfer_len = num_packets * hc->max_packet;
- }
- }
- else
- {
- num_packets = 1;
- }
- if (hc->ep_is_in)
- {
- hc->xfer_len = num_packets * hc->max_packet;
- }
-
- /* Initialize the HCTSIZn register */
- USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
- ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
- (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-
- is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
- USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-
- /* Set host channel enable */
- tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-
- if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
- {
- switch(hc->ep_type)
- {
- /* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- len_words = (hc->xfer_len + 3) / 4;
-
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx->HNPTXSTS & 0xFFFF))
- {
- /* need to process data in nptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
- }
- break;
-
- /* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- len_words = (hc->xfer_len + 3) / 4;
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
- }
- break;
-
- default:
- break;
- }
-
- /* Write packet into the Tx FIFO. */
- USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Read all host channel interrupts status
- * @param USBx : Selected device
- * @retval HAL state
- */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- return ((USBx_HOST->HAINT) & 0xFFFF);
-}
-
-/**
- * @brief Halt a host channel
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
- * This parameter can be a value from 1 to 15
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
-{
- uint32_t count = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* Check for space in the request queue to issue the halt. */
- if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) ||
- (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
- if ((USBx->HNPTXSTS & 0xFFFF) == 0)
- {
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- }
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
- if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
- {
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Initiate Do Ping protocol
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
- * This parameter can be a value from 1 to 15
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
-{
- uint8_t num_packets = 1;
- uint32_t tmpreg = 0;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
- USB_OTG_HCTSIZ_DOPING;
-
- /* Set host channel enable */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop Host Core
- * @param USBx : Selected device
- * @retval HAL state
- */
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
-{
- uint8_t index;
- uint32_t count = 0;
- uint32_t value = 0;
-
- USB_DisableGlobalInt(USBx);
-
- /* Flush FIFO */
- USB_FlushTxFifo(USBx, 0x10);
- USB_FlushRxFifo(USBx);
-
- /* Flush out any leftover queued requests. */
- for (index = 0; index <= 15; index++)
- {
- value = USBx_HC(index)->HCCHAR;
- value |= USB_OTG_HCCHAR_CHDIS;
- value &= ~USB_OTG_HCCHAR_CHENA;
- value &= ~USB_OTG_HCCHAR_EPDIR;
- USBx_HC(index)->HCCHAR = value;
- }
-
- /* Halt all channels to put them into a known state. */
- for (index = 0; index <= 15; index++)
- {
- value = USBx_HC(index)->HCCHAR ;
- value |= USB_OTG_HCCHAR_CHDIS;
- value |= USB_OTG_HCCHAR_CHENA;
- value &= ~USB_OTG_HCCHAR_EPDIR;
- USBx_HC(index)->HCCHAR = value;
-
- do
- {
- if (++count > 1000)
- {
- break;
- }
- }
- while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
-
- /* Clear any pending Host interrupts */
- USBx_HOST->HAINT = 0xFFFFFFFF;
- USBx->GINTSTS = 0xFFFFFFFF;
- USB_EnableGlobalInt(USBx);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
- /* active Remote wakeup signalling */
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* active Remote wakeup signalling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
- return HAL_OK;
-}
-
-#endif /* USB_OTG_FS */
-
-/*==============================================================================
- USB Device FS peripheral available on STM32F102xx and STM32F103xx devices
-==============================================================================*/
-#if defined (USB)
-/**
- * @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(cfg);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_EnableGlobalInt
- * Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
-{
- uint32_t winterruptmask = 0;
-
- /* Set winterruptmask variable */
- winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /* Set interrupt mask */
- USBx->CNTR |= winterruptmask;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DisableGlobalInt
- * Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
- * @retval HAL status
-*/
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
-{
- uint32_t winterruptmask = 0;
-
- /* Set winterruptmask variable */
- winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /* Clear interrupt mask */
- USBx->CNTR &= ~winterruptmask;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
- * This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE: Peripheral mode mode
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(mode);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevInit : Initializes the USB controller registers
- * for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
- * the configuration information for the specified USBx peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(cfg);
-
- /* Init Device */
- /*CNTR_FRES = 1*/
- USBx->CNTR = USB_CNTR_FRES;
-
- /*CNTR_FRES = 0*/
- USBx->CNTR = 0;
-
- /*Clear pending interrupts*/
- USBx->ISTR = 0;
-
- /*Set Btable Address*/
- USBx->BTABLE = BTABLE_ADDRESS;
-
- /* Enable USB Device Interrupt mask */
- USB_EnableGlobalInt(USBx);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
- * This parameter can be a value from 1 to 15
- 15 means Flush all Tx FIFOs
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(num);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
- /* initialize Endpoint */
- switch (ep->type)
- {
- case EP_TYPE_CTRL:
- PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL);
- break;
- case EP_TYPE_BULK:
- PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK);
- break;
- case EP_TYPE_INTR:
- PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT);
- break;
- case EP_TYPE_ISOC:
- PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS);
- break;
- default:
- break;
- }
-
- PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
-
- if (ep->doublebuffer == 0)
- {
- if (ep->is_in)
- {
- /*Set the endpoint Transmit buffer address */
- PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Configure NAK status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
- }
- else
- {
- /*Set the endpoint Receive buffer address */
- PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
- /*Set the endpoint Receive buffer counter*/
- PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
- }
- /*Double Buffer*/
- else
- {
- /*Set the endpoint as double buffered*/
- PCD_SET_EP_DBUF(USBx, ep->num);
- /*Set buffer address for double buffered mode*/
- PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1);
-
- if (ep->is_in==0)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(USBx, ep->num);
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- PCD_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
- if (ep->doublebuffer == 0)
- {
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
- else
- {
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
- /*Double Buffer*/
- else
- {
- if (ep->is_in==0)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(USBx, ep->num);
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- PCD_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep)
-{
- uint16_t pmabuffer = 0;
- uint32_t len = ep->xfer_len;
-
- /* IN endpoint */
- if (ep->is_in == 1)
- {
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0;
- }
-
- /* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0)
- {
- USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len);
- PCD_SET_EP_TX_CNT(USBx, ep->num, len);
- }
- else
- {
- /* Write the data to the USB endpoint */
- if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX)
- {
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
- }
- else
- {
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
- }
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len);
- PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
- }
-
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
- }
- else /* OUT endpoint */
- {
- /* Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0;
- }
-
- /* configure and validate Rx endpoint */
- if (ep->doublebuffer == 0)
- {
- /*Set RX buffer count*/
- PCD_SET_EP_RX_CNT(USBx, ep->num, len);
- }
- else
- {
- /*Set the Double buffer counter*/
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
- }
-
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(src);
- UNUSED(ch_ep_num);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param dest : destination pointer
- * @param len : Number of bytes to read
- * @retval pointer to destination buffer
- */
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(dest);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return ((void *)NULL);
-}
-
-/**
- * @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep)
-{
- if (ep->num == 0)
- {
- /* This macro sets STALL status for RX & TX*/
- PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
- }
- else
- {
- if (ep->is_in)
- {
- PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL);
- }
- else
- {
- PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL);
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
-{
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(USBx, ep->num);
- PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
- }
- else
- {
- PCD_CLEAR_RX_DTOG(USBx, ep->num);
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
- }
- return HAL_OK;
-}
-
-/**
- * @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
-{
- /* disable all interrupts and force USB reset */
- USBx->CNTR = USB_CNTR_FRES;
-
- /* clear interrupt status register */
- USBx->ISTR = 0;
-
- /* switch-off device */
- USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
- * This parameter can be a value from 0 to 255
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address)
-{
- if(address == 0)
- {
- /* set device address and enable function */
- USBx->DADDR = USB_DADDR_EF;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadInterrupts (USB_TypeDef *USBx)
-{
- uint32_t tmpreg = 0;
-
- tmpreg = USBx->ISTR;
- return tmpreg;
-}
-
-/**
- * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device OUT EP Interrupt register
- */
-uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device IN EP Interrupt register
- */
-uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx : Selected device
- * @param interrupt : interrupt flag
- * @retval None
- */
-void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(interrupt);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-}
-
-/**
- * @brief Prepare the EP0 to start the first control setup
- * @param USBx : Selected device
- * @param psetup : pointer to setup packet
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(psetup);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
- * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
-{
- USBx->CNTR |= USB_CNTR_RESUME;
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
-{
- USBx->CNTR &= ~(USB_CNTR_RESUME);
- return HAL_OK;
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx : pointer to USB register.
- * @param pbUsrBuf : pointer to user memory area.
- * @param wPMABufAddr : address into PMA.
- * @param wNBytes : number of bytes to be copied.
- * @retval None
- */
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t nbytes = (wNBytes + 1) >> 1; /* nbytes = (wNBytes + 1) / 2 */
- uint32_t index = 0, temp1 = 0, temp2 = 0;
- uint16_t *pdwVal = NULL;
-
- pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
- for (index = nbytes; index != 0; index--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
- *pdwVal++ = temp2;
- pdwVal++;
- pbUsrBuf++;
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx : pointer to USB register.
-* @param pbUsrBuf : pointer to user memory area.
- * @param wPMABufAddr : address into PMA.
- * @param wNBytes : number of bytes to be copied.
- * @retval None
- */
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t nbytes = (wNBytes + 1) >> 1;/* /2*/
- uint32_t index = 0;
- uint32_t *pdwVal = NULL;
-
- pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
- for (index = nbytes; index != 0; index--)
- {
- *(uint16_t*)pbUsrBuf++ = *pdwVal++;
- pbUsrBuf++;
- }
-}
-
-#endif /* USB */
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-#if defined (USB_OTG_FS)
-/** @addtogroup USB_LL_Private_Functions
- * @{
- */
-/**
- * @brief Reset the USB Core (needed after USB clock settings change)
- * @param USBx : Selected device
- * @retval HAL status
- */
-static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
-{
- uint32_t count = 0;
-
- /* Wait for AHB master IDLE state. */
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-
- /* Core Soft Reset */
- count = 0;
- USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-
- do
- {
- if (++count > 200000)
- {
- return HAL_TIMEOUT;
- }
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-
- return HAL_OK;
-}
-/**
- * @}
- */
-#endif /* USB_OTG_FS */
-
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/lib/hal-stm32f1/source/stm32f1xx_ll_utils.c b/lib/hal-stm32f1/source/stm32f1xx_ll_utils.c deleted file mode 100644 index 5693993e..00000000 --- a/lib/hal-stm32f1/source/stm32f1xx_ll_utils.c +++ /dev/null @@ -1,623 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f1xx_ll_utils.c
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief UTILS LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_rcc.h"
-#include "stm32f1xx_ll_utils.h"
-#include "stm32f1xx_ll_system.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @addtogroup UTILS_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
- * @{
- */
-
-/* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#if defined(FLASH_ACR_LATENCY)
-#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
-#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
-#else
- /*!< No Latency Configuration in this device */
-#endif
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
- * @{
- */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_16))
-
-#if defined(RCC_CFGR_PLLMULL6_5)
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
-#else
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_16))
-#endif /* RCC_CFGR_PLLMULL6_5 */
-
-#if defined(RCC_CFGR2_PREDIV1)
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
-#else
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
-#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
-
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
- || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
- * @{
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
-#endif /* FLASH_ACR_LATENCY */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup UTILS_LL_EF_DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
- * @note When a RTOS is used, it is recommended to avoid changing the Systick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param HCLKFrequency HCLK frequency in Hz
- * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
- * @retval None
- */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
- /* Use frequency provided in argument */
- LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
- * @brief This function provides accurate delay (in milliseconds) based
- * on SysTick counter flag
- * @note When a RTOS is used, it is recommended to avoid using blocking delay
- * and use rather osDelay service.
- * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
- * will configure Systick to 1ms
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-void LL_mDelay(uint32_t Delay)
-{
- __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- /* Add this code to indicate that local variable is not used */
- ((void)tmp);
-
- /* Add a period to guaranty minimum wait */
- if (Delay < LL_MAX_DELAY)
- {
- Delay++;
- }
-
- while (Delay)
- {
- if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- {
- Delay--;
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_EF_SYSTEM
- * @brief System Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### System Configuration functions #####
- ===============================================================================
- [..]
- System, AHB and APB buses clocks configuration
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
- @endverbatim
- @internal
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
- (++) +-----------------------------------------------+
- (++) | Latency | SYSCLK clock frequency (MHz) |
- (++) |---------------|-------------------------------|
- (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- (++) |---------------|-------------------------------|
- (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- (++) |---------------|-------------------------------|
- (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- (++) +-----------------------------------------------+
- @endinternal
- * @{
- */
-
-/**
- * @brief This function sets directly SystemCoreClock CMSIS variable.
- * @note Variable can be calculated also through SystemCoreClockUpdate function.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @retval None
- */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
- /* HCLK clock frequency */
- SystemCoreClock = HCLKFrequency;
-}
-
-/**
- * @brief This function configures system clock with HSI as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed 72MHz
- * @note FLASH latency can be modified through this function.
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- /* Check PREDIV value */
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- /* Force PREDIV value to 2 */
- UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
- /* Enable HSI if not enabled */
- if (LL_RCC_HSI_IsReady() != 1U)
- {
- LL_RCC_HSI_Enable();
- while (LL_RCC_HSI_IsReady() != 1U)
- {
- /* Wait for HSI ready */
- }
- }
-
- /* Configure PLL */
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief This function configures system clock with HSE as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed @ref UTILS_PLL_OUTPUT_MAX
- * @note FLASH latency can be modified through this function.
- * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
- * @param HSEBypass This parameter can be one of the following values:
- * @arg @ref LL_UTILS_HSEBYPASS_ON
- * @arg @ref LL_UTILS_HSEBYPASS_OFF
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
- assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
-
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
- /* Enable HSE if not enabled */
- if (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Check if need to enable HSE bypass feature or not */
- if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- {
- LL_RCC_HSE_EnableBypass();
- }
- else
- {
- LL_RCC_HSE_DisableBypass();
- }
-
- /* Enable HSE */
- LL_RCC_HSE_Enable();
- while (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Wait for HSE ready */
- }
- }
-
- /* Configure PLL */
- LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param Frequency SYSCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if (Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if (Frequency > UTILS_LATENCY2_FREQ)
- {
- /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if (Frequency > UTILS_LATENCY1_FREQ)
- {
- /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
- }
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/**
- * @brief Function to check that PLL can be modified
- * @param PLL_InputFrequency PLL input frequency (in Hz)
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @retval PLL output frequency (in Hz)
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-
- /* Check different PLL parameters according to RM */
-#if defined (RCC_CFGR2_PREDIV1)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
-#elif defined(RCC_CFGR2_PREDIV1SRC)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_CFGR2_PREDIV1SRC*/
- assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
- return pllfreq;
-}
-
-/**
- * @brief Function to check that PLL can be modified
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PLL modification can be done
- * - ERROR: PLL is busy
- */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check if PLL is busy*/
- if (LL_RCC_PLL_IsReady() != 0U)
- {
- /* PLL configuration cannot be modified */
- status = ERROR;
- }
-#if defined(RCC_PLL2_SUPPORT)
- /* Check if PLL2 is busy*/
- if (LL_RCC_PLL2_IsReady() != 0U)
- {
- /* PLL2 configuration cannot be modified */
- status = ERROR;
- }
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
- /* Check if PLLI2S is busy*/
- if (LL_RCC_PLLI2S_IsReady() != 0U)
- {
- /* PLLI2S configuration cannot be modified */
- status = ERROR;
- }
-#endif /* RCC_PLLI2S_SUPPORT */
-
- return status;
-}
-
-/**
- * @brief Function to enable PLL and switch system clock to PLL
- * @param SYSCLK_Frequency SYSCLK frequency
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: No problem to switch system to PLL
- * - ERROR: Problem to switch system to PLL
- */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
-#if defined(FLASH_ACR_LATENCY)
- uint32_t sysclk_frequency_current = 0U;
-#endif /* FLASH_ACR_LATENCY */
-
- assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
- assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
- assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
-
-#if defined(FLASH_ACR_LATENCY)
- /* Calculate current SYSCLK frequency */
- sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
-#endif /* FLASH_ACR_LATENCY */
-
- /* Increasing the number of wait states because of higher CPU frequency */
-#if defined (FLASH_ACR_LATENCY)
- if (sysclk_frequency_current < SYSCLK_Frequency)
- {
- /* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-#endif /* FLASH_ACR_LATENCY */
-
- /* Update system clock configuration */
- if (status == SUCCESS)
- {
-#if defined(RCC_PLL2_SUPPORT)
- /* Enable PLL2 */
- LL_RCC_PLL2_Enable();
- while (LL_RCC_PLL2_IsReady() != 1U)
- {
- /* Wait for PLL2 ready */
- }
-
-#endif /* RCC_PLL2_SUPPORT */
- /* Enable PLL */
- LL_RCC_PLL_Enable();
- while (LL_RCC_PLL_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Sysclk activation on the main PLL */
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- {
- /* Wait for system clock switch to PLL */
- }
-
- /* Set APB1 & APB2 prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
-#if defined (FLASH_ACR_LATENCY)
- if (sysclk_frequency_current > SYSCLK_Frequency)
- {
- /* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-#endif /* FLASH_ACR_LATENCY */
-
- /* Update SystemCoreClock variable */
- if (status == SUCCESS)
- {
- LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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