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author | Kevin O'Connor <kevin@koconnor.net> | 2018-12-26 15:46:25 -0500 |
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committer | Kevin O'Connor <kevin@koconnor.net> | 2019-01-07 19:33:26 -0500 |
commit | e278552d44e2d795e335ec33f898c9d6e1413688 (patch) | |
tree | 1abf075ce7c6d8f9b2de64126cb0b7e2076748f1 /lib/cmsis-sam4e/include/instance/smc.h | |
parent | 70bbdf93347c814ae39b1cd04d04fd66706a8b7e (diff) | |
download | kutter-e278552d44e2d795e335ec33f898c9d6e1413688.tar.gz kutter-e278552d44e2d795e335ec33f898c9d6e1413688.tar.xz kutter-e278552d44e2d795e335ec33f898c9d6e1413688.zip |
lib: Rename lib/cmsis-sam4e/ to lib/sam4e/
This is in preparation for merging the sam3 and sam4 code.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'lib/cmsis-sam4e/include/instance/smc.h')
-rw-r--r-- | lib/cmsis-sam4e/include/instance/smc.h | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/lib/cmsis-sam4e/include/instance/smc.h b/lib/cmsis-sam4e/include/instance/smc.h deleted file mode 100644 index a94d2a78..00000000 --- a/lib/cmsis-sam4e/include/instance/smc.h +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* SAM Software Package License */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) %copyright_year%, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ - -#ifndef _SAM4E_SMC_INSTANCE_ -#define _SAM4E_SMC_INSTANCE_ - -/* ========== Register definition for SMC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SMC_SETUP0 (0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 (0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 (0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 (0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 (0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 (0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 (0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 (0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 (0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 (0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 (0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 (0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 (0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 (0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 (0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 (0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_OCMS (0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 (0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 (0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR (0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR (0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -#else -#define REG_SMC_SETUP0 (*(RwReg*)0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 (*(RwReg*)0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 (*(RwReg*)0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 (*(RwReg*)0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 (*(RwReg*)0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 (*(RwReg*)0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 (*(RwReg*)0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 (*(RwReg*)0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 (*(RwReg*)0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 (*(RwReg*)0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 (*(RwReg*)0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 (*(RwReg*)0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 (*(RwReg*)0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 (*(RwReg*)0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 (*(RwReg*)0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 (*(RwReg*)0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_OCMS (*(RwReg*)0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 (*(WoReg*)0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 (*(WoReg*)0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR (*(RwReg*)0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR (*(RoReg*)0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _SAM4E_SMC_INSTANCE_ */ |