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authorKevin O'Connor <kevin@koconnor.net>2018-07-31 11:01:24 -0400
committerKevin O'Connor <kevin@koconnor.net>2018-08-06 23:36:05 -0400
commit742048a08d11982e98a1dc00c67a3974e6b5618c (patch)
treef7ff056f3484db64245e629b4e2ca7505559662c /lib/cmsis-sam3x8e/include/instance/instance_spi0.h
parente1146c04fd4b8d3f1de0c4fe202513c843868acb (diff)
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lib: Remove the (now unused) cmsis-sam3x8e directory
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'lib/cmsis-sam3x8e/include/instance/instance_spi0.h')
-rw-r--r--lib/cmsis-sam3x8e/include/instance/instance_spi0.h60
1 files changed, 0 insertions, 60 deletions
diff --git a/lib/cmsis-sam3x8e/include/instance/instance_spi0.h b/lib/cmsis-sam3x8e/include/instance/instance_spi0.h
deleted file mode 100644
index aca3ffb2..00000000
--- a/lib/cmsis-sam3x8e/include/instance/instance_spi0.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* ----------------------------------------------------------------------------
- * SAM Software Package License
- * ----------------------------------------------------------------------------
- * Copyright (c) 2012, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following condition is met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef _SAM3XA_SPI0_INSTANCE_
-#define _SAM3XA_SPI0_INSTANCE_
-
-/* ========== Register definition for SPI0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */
-#define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */
-#define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */
-#define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
-#define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */
-#define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
-#define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
-#define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
-#define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */
-#define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
-#define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#else
-#define REG_SPI0_CR (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */
-#define REG_SPI0_MR (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */
-#define REG_SPI0_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
-#define REG_SPI0_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
-#define REG_SPI0_SR (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */
-#define REG_SPI0_IER (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
-#define REG_SPI0_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
-#define REG_SPI0_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
-#define REG_SPI0_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
-#define REG_SPI0_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
-#define REG_SPI0_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAM3XA_SPI0_INSTANCE_ */