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| author | Kevin O'Connor <kevin@koconnor.net> | 2019-07-25 23:50:12 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2019-07-26 07:51:12 -0400 |
| commit | f3d7287a282f205fd0914e35872b036b4c46ddf5 (patch) | |
| tree | ff2938026cbac021abfc754008068199098422ac | |
| parent | 658088b7533bb088422fcb239a6f50ed72e13322 (diff) | |
| download | kutter-f3d7287a282f205fd0914e35872b036b4c46ddf5.tar.gz kutter-f3d7287a282f205fd0914e35872b036b4c46ddf5.tar.xz kutter-f3d7287a282f205fd0914e35872b036b4c46ddf5.zip | |
stm32f4: Add support for external 8Mhz crystal
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
| -rw-r--r-- | src/stm32f4/Kconfig | 8 | ||||
| -rw-r--r-- | src/stm32f4/clock.c | 20 |
2 files changed, 23 insertions, 5 deletions
diff --git a/src/stm32f4/Kconfig b/src/stm32f4/Kconfig index 9d78eb94..df22d36c 100644 --- a/src/stm32f4/Kconfig +++ b/src/stm32f4/Kconfig @@ -15,6 +15,14 @@ config CLOCK_FREQ int default 180000000 +choice + prompt "Clock Reference" + config STM32F4_CLOCK_REF_8M + bool "8Mhz crystal" + config STM32F4_CLOCK_REF_INTERNAL + bool "Internal clock" +endchoice + config SERIAL bool default y diff --git a/src/stm32f4/clock.c b/src/stm32f4/clock.c index 339a7fde..5b98722a 100644 --- a/src/stm32f4/clock.c +++ b/src/stm32f4/clock.c @@ -4,6 +4,7 @@ // // This file may be distributed under the terms of the GNU GPLv3 license. +#include "autoconf.h" // CONFIG_STM32F4_CLOCK_REF_8M #include "internal.h" // enable_pclock #define FREQ_PERIPH 45000000 @@ -38,11 +39,20 @@ get_pclock_frequency(uint32_t periph_base) void clock_setup(void) { - // Configure 180Mhz PLL from internal oscillator (HSI) - RCC->PLLCFGR = ( - RCC_PLLCFGR_PLLSRC_HSI | (16 << RCC_PLLCFGR_PLLM_Pos) - | (360 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos) - | (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos)); + if (CONFIG_STM32F4_CLOCK_REF_8M) { + // Configure 180Mhz PLL from external 8Mhz crystal (HSE) + RCC->CR |= RCC_CR_HSEON; + RCC->PLLCFGR = ( + RCC_PLLCFGR_PLLSRC_HSE | (4 << RCC_PLLCFGR_PLLM_Pos) + | (180 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos) + | (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos)); + } else { + // Configure 180Mhz PLL from internal 16Mhz oscillator (HSI) + RCC->PLLCFGR = ( + RCC_PLLCFGR_PLLSRC_HSI | (8 << RCC_PLLCFGR_PLLM_Pos) + | (180 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos) + | (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos)); + } RCC->CR |= RCC_CR_PLLON; // Enable "over drive" |