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| author | Eric Callahan <arksine.code@gmail.com> | 2021-11-06 11:17:08 -0400 |
|---|---|---|
| committer | KevinOConnor <kevin@koconnor.net> | 2021-11-08 20:10:51 -0500 |
| commit | a0615e5e17d701ada93acd59031193a1b231dd7c (patch) | |
| tree | b7083c68d493fe724d01c7566a99539e745d59df | |
| parent | bf9d497ab0ee437429e7abbe11cc059ca63c9823 (diff) | |
| download | kutter-a0615e5e17d701ada93acd59031193a1b231dd7c.tar.gz kutter-a0615e5e17d701ada93acd59031193a1b231dd7c.tar.xz kutter-a0615e5e17d701ada93acd59031193a1b231dd7c.zip | |
stm32f4: reset peripherals in enable_pcclock()
Reset peripherals to after enabling to clear stale
registers set by the bootloader.
Signed-off-by: Eric Callahan <arksine.code@gmail.com>
| -rw-r--r-- | src/stm32/stm32f4.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index b185d983..3e5fc2d2 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -24,10 +24,17 @@ enable_pclock(uint32_t periph_base) uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400; RCC->APB1ENR |= (1<<pos); RCC->APB1ENR; + RCC->APB1RSTR |= (1<<pos); + RCC->APB1RSTR &= ~(1<<pos); } else if (periph_base < AHB1PERIPH_BASE) { uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400; RCC->APB2ENR |= (1<<pos); RCC->APB2ENR; + // Skip ADC peripheral reset as they share a bit + if (pos < 8 || pos > 10) { + RCC->APB2RSTR |= (1<<pos); + RCC->APB2RSTR &= ~(1<<pos); + } } else if (periph_base < AHB2PERIPH_BASE) { uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400; RCC->AHB1ENR |= (1<<pos); |