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| author | Kevin O'Connor <kevin@koconnor.net> | 2021-10-12 13:38:33 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2021-10-12 13:43:31 -0400 |
| commit | 97d36ac4518d67b4c589f45c203e75b574f09238 (patch) | |
| tree | ec5585a63f5a52497f9d3f19f5e505fe96fefd14 | |
| parent | 1b801508baf58b8053bb30d101efce018b159a5e (diff) | |
| download | kutter-97d36ac4518d67b4c589f45c203e75b574f09238.tar.gz kutter-97d36ac4518d67b4c589f45c203e75b574f09238.tar.xz kutter-97d36ac4518d67b4c589f45c203e75b574f09238.zip | |
stm32: Change stm32f0 OSPEEDR to "medium" speed
The previous OSPEEDR value of 0x2 was copied from the stm32f4.c code,
but the stm32f0 interprets that value the same as 0x0 - which is "low"
speed. Change the OSPEEDR value to "medium" speed so that it matches
the configuration of stm32f1 chips.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
| -rw-r--r-- | src/stm32/stm32f0.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index 06b5d3ab..701346c5 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -64,7 +64,7 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHBENR; } -#define STM_OSPEED 0x2 // ~2Mhz at 50pF +#define STM_OSPEED 0x1 // ~10Mhz at 50pF // Set the mode and extended function of a pin void |