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authorKevin O'Connor <kevin@koconnor.net>2024-09-22 21:18:34 -0400
committerKevin O'Connor <kevin@koconnor.net>2024-09-22 21:18:34 -0400
commit8b7cc439529d727944589b751bd3a00305976bd0 (patch)
tree7cefc1c80b1a7faf74f0dd01f37a0c0b86460ba7
parent9426485bb6c3855b117e05b1927e0b7c1937e0a9 (diff)
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stm32: Reduce peripheral clock speed on stm32g4 chips
A 170mhz (or 150mhz) peripheral clock is too fast for some peripherals. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
-rw-r--r--src/stm32/stm32g4.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c
index 5255cb19..6d6d1c0d 100644
--- a/src/stm32/stm32g4.c
+++ b/src/stm32/stm32g4.c
@@ -12,7 +12,7 @@
#include "internal.h" // enable_pclock
#include "sched.h" // sched_main
-#define FREQ_PERIPH_DIV 1
+#define FREQ_PERIPH_DIV 2
#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
// Map a peripheral address to its enable bits
@@ -142,7 +142,7 @@ clock_setup(void)
RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;
// Switch system clock to PLL
- RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1
+ RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2
| RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
;