#ifndef MK20DX256_REG_UART_H #define MK20DX256_REG_UART_H #include "regdefs.h" /* * K10 Sub-Family Reference Manual §3.9.5.1 excerpt: * * 1. Standard features of all UARTs: * • RS-485 support * • Hardware flow control (RTS/CTS) * • 9-bit UART to support address mark with parity * • MSB/LSB configuration on data * 2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on * the bus clock. The maximum baud rate is 1/16 of related source clock frequency. * 3. IrDA is available on all UARTs * 4. UART0 contains the standard features plus ISO7816 * 5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports * open-drain for all I/O. * 6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs * 7. All other UARTs contain a 1-entry transmit and receive FIFOs * 8. CEA709.1-B (LON) is available in UART0 */ // Standard Features // UART Baud Rate Registers: High #define UART_BDH(base) REG_8((base) + 0x0) enum { BDH_LBKDIE = 7, // LIN Break Detect Interrupt Enable BDH_RXEDGIE = 6, // RxD Input Active Edge Interrupt Enable BDH_SBR = 0, // UART Baud Rate Bits BDH_SBR_M = REG_8_M(BDH_SBR, 4), }; // UART Baud Rate Registers: Low #define UART_BDL(base) REG_8((base) + 0x1) enum { BDL_SBR = 0, // UART Baud Rate Bits BDL_SBR_M = REG_8_M(BDL_SBR, 8), }; // UART Control Register 1 #define UART_C1(base) REG_8((base) + 0x2) enum { C1_LOOPS = 7, // Loop Mode Select C1_UARTSWAI = 6, // UART Stops in Wait Mode C1_RSRC = 5, // Receiver Source Select C1_M = 4, // 9-bit or 8-bit Mode Select C1_WAKE = 3, // Receiver Wakeup Method Select C1_ILT = 2, // Idle Line Type Select C1_PE = 1, // Parity Enable C1_PT = 0, // Parity Type }; // UART Control Register 2 #define UART_C2(base) REG_8((base) + 0x3) enum { C2_TIE = 7, // Transmitter Interrupt or DMA Transfer Enable. C2_TCIE = 6, // Transmission Complete Interrupt Enable C2_RIE = 5, // Receiver Full Interrupt or DMA Transfer Enable C2_ILIE = 4, // Idle Line Interrupt Enable C2_TE = 3, // Transmitter Enable C2_RE = 2, // Receiver Enable C2_RWU = 1, // Receiver Wakeup Control C2_SBK = 0, // Send Break }; // UART Status Register 1 #define UART_S1(base) REG_8((base) + 0x4) enum { S1_TDRE = 7, // Transmit Data Register Empty Flag S1_TC = 6, // Transmit Complete Flag S1_RDRF = 5, // Receive Data Register Full Flag S1_IDLE = 4, // Idle Line Flag S1_OR = 3, // Receiver Overrun Flag S1_NF = 2, // Noise Flag S1_FE = 1, // Framing Error Flag S1_PF = 0, // Parity Error Flag }; // UART Status Register 2 #define UART_S2(base) REG_8((base) + 0x5) enum { S2_LBKDIF = 7, // LIN Break Detect Interrupt Flag S2_RXEDGIF = 6, // RxD Pin Active Edge Interrupt Flag S2_MSBF = 5, // Most Significant Bit First S2_RXINV = 4, // Receive Data Inversion S2_RWUID = 3, // Receive Wakeup Idle Detect S2_BRK13 = 2, // Break Transmit Character Length S2_LBKDE = 1, // LIN Break Detection Enable S2_RAF = 0, // Receiver Active Flag }; // UART Control Register 3 #define UART_C3(base) REG_8((base) + 0x6) enum { C3_R8 = 7, // Received Bit 8 C3_T8 = 6, // Transmit Bit 8 C3_TXDIR = 5, // Transmitter Pin Data Direction in Single-Wire mode C3_TXINV = 4, // Transmit Data Inversion. C3_ORIE = 3, // Overrun Error Interrupt Enable C3_NEIE = 2, // Noise Error Interrupt Enable C3_FEIE = 1, // Framing Error Interrupt Enable C3_PEIE = 0, // Parity Error Interrupt Enable }; // UART Data Register #define UART_D(base) REG_8((base) + 0x7) enum { D_RT = 0, D_RT_M = REG_8_M(D_RT, 8), }; // UART Match Address Registers 1 #define UART_MA1(base) REG_8((base) + 0x8) enum { MA1_MA = 0, // Match Address MA1_MA_M = REG_8_M(MA1_MA, 8), }; // UART Match Address Registers 2 #define UART_MA2(base) REG_8((base) + 0x9) enum { MA2_MA = 0, // Match Address MA2_MA_M = REG_8_M(MA2_MA, 8), }; // UART Control Register 4 #define UART_C4(base) REG_8((base) + 0xA) enum { C4_MAEN1 = 7, // Match Address Mode Enable 1 C4_MAEN2 = 6, // Match Address Mode Enable 2 C4_M10 = 5, // 10-bit Mode Select C4_BRFA = 0, // Baud Rate Fine Adjust C4_BRFA_M = REG_8_M(C4_BRFA, 5), }; // UART Control Register 5 #define UART_C5(base) REG_8((base) + 0xB) enum { C5_TDMAS = 7, // Transmitter DMA Select C5_RDMAS = 5, // Receiver Full DMA Select }; // UART Extended Data Register #define UART_ED(base) REG_8((base) + 0xC) enum { ED_NOISY = 7, // Dataword contained in D and C3[R8] received with noise. ED_PARITYE = 6, // Dataword contained in D and C3[R8] received with a parity error. }; // UART Modem Register #define UART_MODEM(base) REG_8((base) + 0xD) enum { MODEM_RXRTSE = 3, // Receiver request-to-send enable MODEM_TXRTSPOL = 2, // Transmitter request-to-send polarity MODEM_TXRTSE = 1, // Transmitter request-to-send enable MODEM_TXCTSE = 0, // Transmitter clear-to-send enable }; // UART Infrared Register #define UART_IR(base) REG_8((base) + 0xE) enum { IR_IREN = 2, // Infrared enable IR_TNP = 0, // Transmitter narrow pulse IR_TNP_M = REG_8_M(IR_TNP, 2), }; // UART FIFO Parameters #define UART_PFIFO(base) REG_8((base) + 0x10) enum { PFIFO_TXFE = 7, // Transmit FIFO Enable PFIFO_TXFIFOSIZE = 4, // Transmit FIFO, Buffer Depth PFIFO_TXFIFOSIZE_M = REG_8_M(PFIFO_TXFIFOSIZE, 3), PFIFO_RXFE = 3, // Receive FIFO Enable PFIFO_RXFIFOSIZE = 0, // Receive FIFO, Buffer Depth PFIFO_RXFIFOSIZE_M = REG_8_M(PFIFO_RXFIFOSIZE, 3), }; // UART FIFO Control Register #define UART_CFIFO(base) REG_8((base) + 0x11) enum { CFIFO_TXFLUSH = 7, // Transmit FIFO/Buffer Flush CFIFO_RXFLUSH = 6, // Receive FIFO/Buffer Flush CFIFO_RXOFE = 2, // Receive FIFO Overflow Interrupt Enable CFIFO_TXOFE = 1, // Transmit FIFO Overflow Interrupt Enable CFIFO_RXUFE = 0, // Receive FIFO Underflow Interrupt Enable }; // UART FIFO Status Register #define UART_SFIFO(base) REG_8((base) + 0x12) enum { SFIFO_TXEMPT = 7, // Transmit Buffer/FIFO Empty SFIFO_RXEMPT = 6, // Receive Buffer/FIFO Empty SFIFO_RXOF = 2, // Receiver Buffer Overflow Flag SFIFO_TXOF = 1, // Transmitter Buffer Overflow Flag SFIFO_RXUF = 0, // Receiver Buffer Underflow Flag }; // UART FIFO Transmit Watermark #define UART_TWFIFO(base) REG_8((base) + 0x13) enum { TWFIFO_TXWATER = 0, // Transmit Watermark TWFIFO_TXWATER_M = REG_8_M(TWFIFO_TXWATER, 8), }; // UART FIFO Transmit Count #define UART_TCFIFO(base) REG_8((base) + 0x14) enum { TCFIFO_TXCOUNT = 0, // Transmit Counter TCFIFO_TXCOUNT_M = REG_8_M(TCFIFO_TXCOUNT, 8), }; // UART FIFO Receive Watermark #define UART_RWFIFO(base) REG_8((base) + 0x15) enum { RWFIFO_RXWATER = 0, // Receive Watermark RWFIFO_RXWATER_M = REG_8_M(RWFIFO_RXWATER, 8), }; // UART FIFO Receive Count #define UART_RCFIFO(base) REG_8((base) + 0x16) enum { RCFIFO_RXCOUNT = 0, RCFIFO_RXCOUNT_M = REG_8_M(RCFIFO_RXCOUNT, 8), }; // UART 0 Only // UART 7816 Control Register #define UART_C7816(base) REG_8((base) + 0x18) // UART 7816 Interrupt Enable Register #define UART_IE7816(base) REG_8((base) + 0x19) // UART 7816 Interrupt Status Register #define UART_IS7816(base) REG_8((base) + 0x1A) // UART 7816 Wait Parameter Register #define UART_WP7816T0(base) REG_8((base) + 0x1B) // UART 7816 Wait Parameter Register #define UART_WP7816T1(base) REG_8((base) + 0x1B) // UART 7816 Wait N Register #define UART_WN7816(base) REG_8((base) + 0x1C) // UART 7816 Wait FD Register #define UART_WF7816(base) REG_8((base) + 0x1D) // UART 7816 Error Threshold Register #define UART_ET7816(base) REG_8((base) + 0x1E) // UART 7816 Transmit Length Register #define UART_TL7816(base) REG_8((base) + 0x1F) // UART CEA709.1-B Control Register 6 #define UART_C6(base) REG_8((base) + 0x21) // UART CEA709.1-B Packet Cycle Time Counter High #define UART_PCTH(base) REG_8((base) + 0x22) // UART CEA709.1-B Packet Cycle Time Counter Low #define UART_PCTL(base) REG_8((base) + 0x23) // UART CEA709.1-B Beta1 Timer #define UART_B1T(base) REG_8((base) + 0x24) // UART CEA709.1-B Secondary Delay Timer High #define UART_SDTH(base) REG_8((base) + 0x25) // UART CEA709.1-B Secondary Delay Timer Low #define UART_SDTL(base) REG_8((base) + 0x26) // UART CEA709.1-B Preamble #define UART_PRE(base) REG_8((base) + 0x27) // UART CEA709.1-B Transmit Packet Length #define UART_TPL(base) REG_8((base) + 0x28) // UART CEA709.1-B Interrupt Enable Register #define UART_IE(base) REG_8((base) + 0x29) // UART CEA709.1-B WBASE #define UART_WB(base) REG_8((base) + 0x2A) // UART CEA709.1-B Status Register #define UART_S3(base) REG_8((base) + 0x2B) // UART CEA709.1-B Status Register #define UART_S4(base) REG_8((base) + 0x2C) // UART CEA709.1-B Received Packet Length #define UART_RPL(base) REG_8((base) + 0x2D) // UART CEA709.1-B Received Preamble Length #define UART_RPREL(base) REG_8((base) + 0x2E) // UART CEA709.1-B Collision Pulse Width #define UART_CPW(base) REG_8((base) + 0x2F) // UART CEA709.1-B Receive Indeterminate Time #define UART_RIDT(base) REG_8((base) + 0x30) // UART CEA709.1-B Transmit Indeterminate Time #define UART_TIDT(base) REG_8((base) + 0x31) // Syntax Sugar #define UART0_BASE 0x4006A000 #define UART0_BDH UART_BDH(UART0_BASE) #define UART0_BDL UART_BDL(UART0_BASE) #define UART0_C1 UART_C1(UART0_BASE) #define UART0_C2 UART_C2(UART0_BASE) #define UART0_S1 UART_S1(UART0_BASE) #define UART0_S2 UART_S2(UART0_BASE) #define UART0_C3 UART_C3(UART0_BASE) #define UART0_D UART_D(UART0_BASE) #define UART0_MA1 UART_MA1(UART0_BASE) #define UART0_MA2 UART_MA2(UART0_BASE) #define UART0_C4 UART_C4(UART0_BASE) #define UART0_C5 UART_C5(UART0_BASE) #define UART0_ED UART_ED(UART0_BASE) #define UART0_MODEM UART_MODEM(UART0_BASE) #define UART0_IR UART_IR(UART0_BASE) #define UART0_PFIFO UART_PFIFO(UART0_BASE) #define UART0_CFIFO UART_CFIFO(UART0_BASE) #define UART0_SFIFO UART_SFIFO(UART0_BASE) #define UART0_TWFIFO UART_TWFIFO(UART0_BASE) #define UART0_TCFIFO UART_TCFIFO(UART0_BASE) #define UART0_RWFIFO UART_RWFIFO(UART0_BASE) #define UART0_RCFIFO UART_RCFIFO(UART0_BASE) #define UART0_C7816 UART_C7816(UART0_BASE) #define UART0_IE7816 UART_IE7816(UART0_BASE) #define UART0_IS7816 UART_IS7816(UART0_BASE) #define UART0_WP7816T0 UART_WP7816T0(UART0_BASE) #define UART0_WP7816T1 UART_WP7816T1(UART0_BASE) #define UART0_WN7816 UART_WN7816(UART0_BASE) #define UART0_WF7816 UART_WF7816(UART0_BASE) #define UART0_ET7816 UART_ET7816(UART0_BASE) #define UART0_TL7816 UART_TL7816(UART0_BASE) #define UART0_C6 UART_C6(UART0_BASE) #define UART0_PCTH UART_PCTH(UART0_BASE) #define UART0_PCTL UART_PCTL(UART0_BASE) #define UART0_B1T UART_B1T(UART0_BASE) #define UART0_SDTH UART_SDTH(UART0_BASE) #define UART0_SDTL UART_SDTL(UART0_BASE) #define UART0_PRE UART_PRE(UART0_BASE) #define UART0_TPL UART_TPL(UART0_BASE) #define UART0_IE UART_IE(UART0_BASE) #define UART0_WB UART_WB(UART0_BASE) #define UART0_S3 UART_S3(UART0_BASE) #define UART0_S4 UART_S4(UART0_BASE) #define UART0_RPL UART_RPL(UART0_BASE) #define UART0_RPREL UART_RPREL(UART0_BASE) #define UART0_CPW UART_CPW(UART0_BASE) #define UART0_RIDT UART_RIDT(UART0_BASE) #define UART0_TIDT UART_TIDT(UART0_BASE) #define UART1_BASE 0x4006B000 #define UART1_BDH UART_BDH(UART1_BASE) #define UART1_BDL UART_BDL(UART1_BASE) #define UART1_C1 UART_C1(UART1_BASE) #define UART1_C2 UART_C2(UART1_BASE) #define UART1_S1 UART_S1(UART1_BASE) #define UART1_S2 UART_S2(UART1_BASE) #define UART1_C3 UART_C3(UART1_BASE) #define UART1_D UART_D(UART1_BASE) #define UART1_MA1 UART_MA1(UART1_BASE) #define UART1_MA2 UART_MA2(UART1_BASE) #define UART1_C4 UART_C4(UART1_BASE) #define UART1_C5 UART_C5(UART1_BASE) #define UART1_ED UART_ED(UART1_BASE) #define UART1_MODEM UART_MODEM(UART1_BASE) #define UART1_IR UART_IR(UART1_BASE) #define UART1_PFIFO UART_PFIFO(UART1_BASE) #define UART1_CFIFO UART_CFIFO(UART1_BASE) #define UART1_SFIFO UART_SFIFO(UART1_BASE) #define UART1_TWFIFO UART_TWFIFO(UART1_BASE) #define UART1_TCFIFO UART_TCFIFO(UART1_BASE) #define UART1_RWFIFO UART_RWFIFO(UART1_BASE) #define UART1_RCFIFO UART_RCFIFO(UART1_BASE) #define UART2_BASE 0x4006C000 #define UART2_BDH UART_BDH(UART2_BASE) #define UART2_BDL UART_BDL(UART2_BASE) #define UART2_C1 UART_C1(UART2_BASE) #define UART2_C2 UART_C2(UART2_BASE) #define UART2_S1 UART_S1(UART2_BASE) #define UART2_S2 UART_S2(UART2_BASE) #define UART2_C3 UART_C3(UART2_BASE) #define UART2_D UART_D(UART2_BASE) #define UART2_MA1 UART_MA1(UART2_BASE) #define UART2_MA2 UART_MA2(UART2_BASE) #define UART2_C4 UART_C4(UART2_BASE) #define UART2_C5 UART_C5(UART2_BASE) #define UART2_ED UART_ED(UART2_BASE) #define UART2_MODEM UART_MODEM(UART2_BASE) #define UART2_IR UART_IR(UART2_BASE) #define UART2_PFIFO UART_PFIFO(UART2_BASE) #define UART2_CFIFO UART_CFIFO(UART2_BASE) #define UART2_SFIFO UART_SFIFO(UART2_BASE) #define UART2_TWFIFO UART_TWFIFO(UART2_BASE) #define UART2_TCFIFO UART_TCFIFO(UART2_BASE) #define UART2_RWFIFO UART_RWFIFO(UART2_BASE) #define UART2_RCFIFO UART_RCFIFO(UART2_BASE) #endif /* MK20DX256_REG_UART_H */