#ifndef MK20DX256_REG_MCG_H
#define MK20DX256_REG_MCG_H

#include <reg/regdefs.h>

#define MCG_C1 REG_8(0x40064000) /* MCG Control 1 Register */
#define C1_CLKS 6 /* Clock Source Select */
#define C1_CLKS_M (uint8_t)(BITS(2) << C1_CLKS)
#define C1_FRDIV 3 /* FLL External Reference Divider */
#define C1_FRDIV_M (uint8_t)(BITS(3) << C1_FRDIV)
#define C1_IREFS 2 /* Internal Reference Select */
#define C1_IRCLKEN 1 /* Internal Reference Clock Enable */
#define C1_IREFSTEN 0 /* Internal Reference Stop Enable */

#define MCG_C2 REG_8(0x40064001) /* MCG Control 2 Register */
#define C2_LOCRE0 7 /* Loss of Clock Reset Enable */
#define C2_RANGE0 4 /* Frequency Range Select */
#define C2_RANGE0_M (uint8_t)(BITS(2) << C2_RANGE0)
#define C2_HGO0 3 /* High Gain Oscillator Select */
#define C2_EREFS0 2 /* External Reference Select */
#define C2_LP 1 /* Low Power Select */
#define C2_IRCS 0 /* Internal Reference Clock Select */

#define MCG_C3 REG_8(0x40064002) /* MCG Control 3 Register */
#define MCG_C4 REG_8(0x40064003) /* MCG Control 4 Register */

#define MCG_C5 REG_8(0x40064004) /* MCG Control 5 Register */
#define C5_PLLCLKEN0 6 /* PLL Clock Enable */
#define C5_PLLSTEN0 5 /* PLL Stop Enable */
#define C5_PRDIV0 0 /* PLL External Reference Divider */
#define C5_PRDIV0_M (uint8_t)(BITS(5) << C5_PRDIV0)

#define MCG_C6 REG_8(0x40064005) /* MCG Control 6 Register */
#define C6_LOLIE0 7 /* Loss of Lock Interrrupt Enable */
#define C6_PLLS 6 /* PLL Select */
#define C6_CME0 5 /* Clock Monitor Enable */
#define C6_VDIV0 0 /* VCO 0 Divider */
#define C6_VDIV0_M (uint8_t)(BITS(5) << C6_VDIV0)

#define MCG_S REG_8(0x40064006) /* MCG Status Register */
#define S_LOLS0 7 /* Loss of Lock Status */
#define S_LOCK0 6 /* Lock Status */
#define S_PLLST 5 /* PLL Select Status */
#define S_IREFST 4 /* Internal Reference Status */
#define S_CLKST 2 /* Clock Mode Status */
#define S_CLKST_M (uint8_t)(BITS(2) << S_CLKST)
#define S_OSCINIT0 1 /* OSC Initialization */
#define S_IRCST 0 /* Internal Reference Clock Status */

#define MCG_SC REG_8(0x40064008) /* MCG Status and Control Register */
#define MCG_ATCVH REG_8(0x4006400A) /* MCG Auto Trim Compare Value High Register */
#define MCG_ATCVL REG_8(0x4006400B) /* MCG Auto Trim Compare Value Low Register */
#define MCG_C7 REG_8(0x4006400C) /* MCG Control 7 Register */
#define MCG_C8 REG_8(0x4006400D) /* MCG Control 8 Register */

#endif /* MK20DX256_REG_MCG_H */