/* Multipurpose Clock Generator (MCG) (Chapter 24) */
#ifndef MK20DX256_REG_MCG_H
#define MK20DX256_REG_MCG_H

#include <reg/regdefs.h>

// MCG Control 1 Register
#define MCG_C1 REG_8(0x40064000)
enum {
	C1_CLKS = 6, // Clock Source Select
	C1_CLKS_M = REG_8_M(C1_CLKS, 2),
	C1_FRDIV = 3, // FLL External Reference Divider
	C1_FRDIV_M = REG_8_M(C1_FRDIV, 3),
	C1_IREFS = 2, // Internal Reference Select
	C1_IRCLKEN = 1, // Internal Reference Clock Enable
	C1_IREFSTEN = 0, // Internal Reference Stop Enable
};

// MCG Control 2 Register
#define MCG_C2 REG_8(0x40064001)
enum {
	C2_LOCRE0 = 7, // Loss of Clock Reset Enable
	C2_RANGE0 = 4, // Frequency Range Select
	C2_RANGE0_M = REG_8_M(C2_RANGE0, 2),
	C2_HGO0 = 3, // High Gain Oscillator Select
	C2_EREFS0 = 2, // External Reference Select
	C2_LP = 1, // Low Power Select
	C2_IRCS = 0, // Internal Reference Clock Select
};

// MCG Control 3 Register
#define MCG_C3 REG_8(0x40064002)
enum {
	C3_SCTRIM = 0, // Slow Internal Reference Clock Trim Setting
	C3_SCTRIM_M = REG_8_M(C3_SCTRIM, 8),
};

// MCG Control 4 Register
#define MCG_C4 REG_8(0x40064003)
enum {
	C4_DMX32 = 7, // DCO Maximum Frequency with 32.768 kHz Reference
	C4_DRST_DRS = 5, // DCO Range Select
	C4_DRST_DRS_M = REG_8_M(C4_DRST_DRS, 2),
	C4_FCTRIM = 1, // Fast Internal Reference Clock Trim Setting
	C4_FCTRIM_M = REG_8_M(C4_FCTRIM, 4),
	C4_SCFTRIM = 0, // Slow Internal Reference Clock Fine Trim
};

// MCG Control 5 Register
#define MCG_C5 REG_8(0x40064004)
enum {
	C5_PLLCLKEN0 = 6, // PLL Clock Enable
	C5_PLLSTEN0 = 5, // PLL Stop Enable
	C5_PRDIV0 = 0, // PLL External Reference Divider
	C5_PRDIV0_M = REG_8_M(C5_PRDIV0, 5),
};

// MCG Control 6 Register
#define MCG_C6 REG_8(0x40064005)
enum {
	C6_LOLIE0 = 7, // Loss of Lock Interrrupt Enable
	C6_PLLS = 6, // PLL Select
	C6_CME0 = 5, // Clock Monitor Enable
	C6_VDIV0 = 0, // VCO 0 Divider
	C6_VDIV0_M = REG_8_M(C6_VDIV0, 5),
};

// MCG Status Register
#define MCG_S REG_8(0x40064006)
enum {
	S_LOLS0 = 7, // Loss of Lock Status
	S_LOCK0 = 6, // Lock Status
	S_PLLST = 5, // PLL Select Status
	S_IREFST = 4, // Internal Reference Status
	S_CLKST = 2, // Clock Mode Status
	S_CLKST_M = REG_8_M(S_CLKST, 2),
	S_OSCINIT0 = 1, // OSC Initialization
	S_IRCST = 0, // Internal Reference Clock Status
};

// MCG Status and Control Register
#define MCG_SC REG_8(0x40064008)
enum {
	SC_ATME = 7, // Automatic Trim Machine Enable
	SC_ATMS = 6, // Automatic Trim Machine Select
	SC_ATMF = 5, // Automatic Trim Machine Fail Flag
	SC_FLTPRSRV = 4, // FLL Filter Preserve Enable
	SC_FCRDIV = 1, // Fast Clock Internal Reference Divider
	SC_FCRDIV_M = REG_8_M(SC_FCRDIV, 3),
	SC_LOCS0 = 0, // OSC0 Loss of Clock Status
};

// MCG Auto Trim Compare Value High Register
#define MCG_ATCVH REG_8(0x4006400A)
enum {
	ATCVH_ATCVH = 0, // ATM Compare Value High
	ATCVH_ATCVH_M = REG_8_M(ATCVH_ATCVH, 8),
};

// MCG Auto Trim Compare Value Low Register
#define MCG_ATCVL REG_8(0x4006400B)
enum {
	ATCVL_ATCVL = 0, // ATM Compare Value Low
	ATCVL_ATCVL_M = REG_8_M(ATCVL_ATCVL, 8),
};

// MCG Control 7 Register
#define MCG_C7 REG_8(0x4006400C)
enum {
	C7_OSCSEL = 0, // MCG OSC Clock Select
};

// MCG Control 8 Register
#define MCG_C8 REG_8(0x4006400D)
enum {
	C8_LOCRE1 = 7, // Loss of Clock Reset Enable
	C8_LOLRE = 6, // Loss of Lock Reset Enable
	C8_CME1 = 5, // Clock Monitor Enable1
	C8_LOCS1 = 0, // RTC Loss of Clock Status
};

#endif /* MK20DX256_REG_MCG_H */