From fae8c5fccf12f6bf9a609b99fe7b5e072a4d627a Mon Sep 17 00:00:00 2001
From: Tomasz Kramkowski <tk@the-tk.com>
Date: Wed, 24 May 2017 20:46:03 +0100
Subject: gpio and port: make base + offset based

---
 reg/port.h | 91 +++++++++++++++++++++++++++++++++++++-------------------------
 1 file changed, 55 insertions(+), 36 deletions(-)

(limited to 'reg/port.h')

diff --git a/reg/port.h b/reg/port.h
index 23cf77f..4a260b0 100644
--- a/reg/port.h
+++ b/reg/port.h
@@ -5,15 +5,7 @@
 #include <reg/regdefs.h>
 
 // Pin Control Register n
-#define PORTA_PCR(n) REG_32(0x40049000 + 4 * (n))
-// Pin Control Register n
-#define PORTB_PCR(n) REG_32(0x4004A000 + 4 * (n))
-// Pin Control Register n
-#define PORTC_PCR(n) REG_32(0x4004B000 + 4 * (n))
-// Pin Control Register n
-#define PORTD_PCR(n) REG_32(0x4004C000 + 4 * (n))
-// Pin Control Register n
-#define PORTE_PCR(n) REG_32(0x4004D000 + 4 * (n))
+#define PORT_PCR(base, n) REG_32((base) + 0x00 + 4 * (n))
 enum {
 	PCR_ISF = 24, // Interrupt Status Flag
 	PCR_IRQC = 16, // Interrupt Configuration
@@ -30,36 +22,63 @@ enum {
 };
 
 // Global Pin Control Low Register
-#define PORTA_GPCLR REG_32(0x40049080)
-// Global Pin Control Low Register
-#define PORTB_GPCLR REG_32(0x4004A080)
-// Global Pin Control Low Register
-#define PORTC_GPCLR REG_32(0x4004B080)
-// Global Pin Control Low Register
-#define PORTD_GPCLR REG_32(0x4004C080)
-// Global Pin Control Low Register
-#define PORTE_GPCLR REG_32(0x4004D080)
+#define PORT_GPCLR(base) REG_32((base) + 0x80)
+enum {
+	GPCLR_GPWE = 16, // Global Pin Write Enable
+#define GPCLR_GPWE_M REG_32_M(GPCLR_GPWE, 16)
+	GPCLR_GPWD = 0, // Global Pin Write Data
+#define GPCLR_GPWD_M REG_32_M(GPCLR_GPWD, 16)
+};
 
 // Global Pin Control High Register
-#define PORTA_GPCHR REG_32(0x40049084)
-// Global Pin Control High Register
-#define PORTB_GPCHR REG_32(0x4004A084)
-// Global Pin Control High Register
-#define PORTC_GPCHR REG_32(0x4004B084)
-// Global Pin Control High Register
-#define PORTD_GPCHR REG_32(0x4004C084)
-// Global Pin Control High Register
-#define PORTE_GPCHR REG_32(0x4004D084)
+#define PORT_GPCHR(base) REG_32((base) + 0x84)
+enum {
+	GPCHR_GPWE = 16, // Global Pin Write Enable
+#define GPCHR_GPWE_M REG_32_M(GPCHR_GPWE, 16)
+	GPCHR_GPWD = 0, // Global Pin Write Data
+#define GPCHR_GPWD_M REG_32_M(GPCHR_GPWD, 16)
+};
 
 // Interrupt Status Flag Register
-#define PORTA_ISFR REG_32(0x400490A0)
-// Interrupt Status Flag Register
-#define PORTB_ISFR REG_32(0x4004A0A0)
-// Interrupt Status Flag Register
-#define PORTC_ISFR REG_32(0x4004B0A0)
-// Interrupt Status Flag Register
-#define PORTD_ISFR REG_32(0x4004C0A0)
-// Interrupt Status Flag Register
-#define PORTE_ISFR REG_32(0x4004D0A0)
+#define PORT_ISFR(base) REG_32((base) + 0xa0)
+enum {
+	ISFR_ISF = 0, // Interrupt Status Flag
+#define ISFR_ISF_M REG_32_M(ISFR_ISF, 32);
+};
+
+#define PORTA_BASE 0x40049000
+
+#define PORTA_GPCHR PORT_GPCHR(PORTA_BASE)
+#define PORTA_GPCLR PORT_GPCLR(PORTA_BASE)
+#define PORTA_ISFR PORT_ISFR(PORTA_BASE)
+#define PORTA_PCR(n) PORT_PCR(n, PORTA_BASE)
+
+#define PORTB_BASE 0x4004A000
+
+#define PORTB_GPCHR PORT_GPCHR(PORTB_BASE)
+#define PORTB_GPCLR PORT_GPCLR(PORTB_BASE)
+#define PORTB_ISFR PORT_ISFR(PORTB_BASE)
+#define PORTB_PCR(n) PORT_PCR(n, PORTB_BASE)
+
+#define PORTC_BASE 0x4004B000
+
+#define PORTC_GPCHR PORT_GPCHR(PORTC_BASE)
+#define PORTC_GPCLR PORT_GPCLR(PORTC_BASE)
+#define PORTC_ISFR PORT_ISFR(PORTC_BASE)
+#define PORTC_PCR(n) PORT_PCR(n, PORTC_BASE)
+
+#define PORTD_BASE 0x4004C000
+
+#define PORTD_GPCHR PORT_GPCHR(PORTD_BASE)
+#define PORTD_GPCLR PORT_GPCLR(PORTD_BASE)
+#define PORTD_ISFR PORT_ISFR(PORTD_BASE)
+#define PORTD_PCR(n) PORT_PCR(n, PORTD_BASE)
+
+#define PORTE_BASE 0x4004D000
+
+#define PORTE_GPCHR PORT_GPCHR(PORTE_BASE)
+#define PORTE_GPCLR PORT_GPCLR(PORTE_BASE)
+#define PORTE_ISFR PORT_ISFR(PORTE_BASE)
+#define PORTE_PCR(n) PORT_PCR(n, PORTE_BASE)
 
 #endif /* MK20DX256_REG_PORT_H */
-- 
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