From fae8c5fccf12f6bf9a609b99fe7b5e072a4d627a Mon Sep 17 00:00:00 2001
From: Tomasz Kramkowski <tk@the-tk.com>
Date: Wed, 24 May 2017 20:46:03 +0100
Subject: gpio and port: make base + offset based

---
 reg/gpio.h | 130 ++++++++++++++++++++++++++++++++++++-------------------------
 1 file changed, 76 insertions(+), 54 deletions(-)

(limited to 'reg/gpio.h')

diff --git a/reg/gpio.h b/reg/gpio.h
index 76d84c5..9335d5e 100644
--- a/reg/gpio.h
+++ b/reg/gpio.h
@@ -4,68 +4,90 @@
 #include <reg/regdefs.h>
 
 // Port Data Output Register
-#define GPIOA_PDOR REG_32(0x400FF000)
-// Port Set Output Register
-#define GPIOA_PSOR REG_32(0x400FF004)
-// Port Clear Output Register
-#define GPIOA_PCOR REG_32(0x400FF008)
-// Port Toggle Output Register
-#define GPIOA_PTOR REG_32(0x400FF00C)
-// Port Data Input Register
-#define GPIOA_PDIR REG_32(0x400FF010)
-// Port Data Direction Register
-#define GPIOA_PDDR REG_32(0x400FF014)
+#define GPIO_PDOR(base) REG_32((base) + 0x00)
+enum {
+	PDOR_PDO = 0, // Port Data Output
+#define PDOR_PDO_M REG_32_M(PDOR_PDO, 32)
+};
 
-// Port Data Output Register
-#define GPIOB_PDOR REG_32(0x400FF040)
 // Port Set Output Register
-#define GPIOB_PSOR REG_32(0x400FF044)
-// Port Clear Output Register
-#define GPIOB_PCOR REG_32(0x400FF048)
-// Port Toggle Output Register
-#define GPIOB_PTOR REG_32(0x400FF04C)
-// Port Data Input Register
-#define GPIOB_PDIR REG_32(0x400FF050)
-// Port Data Direction Register
-#define GPIOB_PDDR REG_32(0x400FF054)
+#define GPIO_PSOR(base) REG_32((base) + 0x04)
+enum {
+	PSOR_PTSO = 0, // Port Set Output
+#define PSOR_PTSO_M REG_32_M(PSOR_PTSO, 32)
+};
 
-// Port Data Output Register
-#define GPIOC_PDOR REG_32(0x400FF080)
-// Port Set Output Register
-#define GPIOC_PSOR REG_32(0x400FF084)
 // Port Clear Output Register
-#define GPIOC_PCOR REG_32(0x400FF088)
-// Port Toggle Output Register
-#define GPIOC_PTOR REG_32(0x400FF08C)
-// Port Data Input Register
-#define GPIOC_PDIR REG_32(0x400FF090)
-// Port Data Direction Register
-#define GPIOC_PDDR REG_32(0x400FF094)
+#define GPIO_PCOR(base) REG_32((base) + 0x08)
+enum {
+	PCOR_PTCO = 0, // Port Clear Output
+#define PCOR_PTCO_M REG_32_M(PCOR_PTCO, 32)
+};
 
-// Port Data Output Register
-#define GPIOD_PDOR REG_32(0x400FF0C0)
-// Port Set Output Register
-#define GPIOD_PSOR REG_32(0x400FF0C4)
-// Port Clear Output Register
-#define GPIOD_PCOR REG_32(0x400FF0C8)
 // Port Toggle Output Register
-#define GPIOD_PTOR REG_32(0x400FF0CC)
-// Port Data Input Register
-#define GPIOD_PDIR REG_32(0x400FF0D0)
-// Port Data Direction Register
-#define GPIOD_PDDR REG_32(0x400FF0D4)
+#define GPIO_PTOR(base) REG_32((base) + 0x0C)
+enum {
+	PTOR_PTTO = 0, // Port Toggle Output
+#define PTOR_PTTO_M REG_32_M(PTOR_PTTO, 32)
+};
 
-// Port Data Output Register
-#define GPIOE_PDOR REG_32(0x400FF100)
-// Port Set Output Register
-#define GPIOE_PSOR REG_32(0x400FF104)
-// Port Clear Output Register
-#define GPIOE_PCOR REG_32(0x400FF108)
-// Port Toggle Output Register
-#define GPIOE_PTOR REG_32(0x400FF10C)
 // Port Data Input Register
-#define GPIOE_PDIR REG_32(0x400FF110)
+#define GPIO_PDIR(base) REG_32((base) + 0x10)
+enum {
+	PDIR_PDI = 0, // Port Data Input
+#define PDIR_PDI_M REG_32_M(PDIR_PDI, 32)
+};
+
 // Port Data Direction Register
-#define GPIOE_PDDR REG_32(0x400FF114)
+#define GPIO_PDDR(base) REG_32((base) + 0x14)
+enum {
+	PDDR_PDD = 0, // Port Data Direction
+#define PDDR_PDD_M REG_32_M(PDDR_PDD, 32)
+};
+
+#define GPIOA_BASE 0x400FF000
+
+#define GPIOA_PDOR GPIO_PDOR(GPIOA_BASE)
+#define GPIOA_PSOR GPIO_PSOR(GPIOA_BASE)
+#define GPIOA_PCOR GPIO_PCOR(GPIOA_BASE)
+#define GPIOA_PTOR GPIO_PTOR(GPIOA_BASE)
+#define GPIOA_PDIR GPIO_PDIR(GPIOA_BASE)
+#define GPIOA_PDDR GPIO_PDDR(GPIOA_BASE)
+
+#define GPIOB_BASE 0x400FF040
+
+#define GPIOB_PDOR GPIO_PDOR(GPIOB_BASE)
+#define GPIOB_PSOR GPIO_PSOR(GPIOB_BASE)
+#define GPIOB_PCOR GPIO_PCOR(GPIOB_BASE)
+#define GPIOB_PTOR GPIO_PTOR(GPIOB_BASE)
+#define GPIOB_PDIR GPIO_PDIR(GPIOB_BASE)
+#define GPIOB_PDDR GPIO_PDDR(GPIOB_BASE)
+
+#define GPIOC_BASE 0x400FF080
+
+#define GPIOC_PDOR GPIO_PDOR(GPIOC_BASE)
+#define GPIOC_PSOR GPIO_PSOR(GPIOC_BASE)
+#define GPIOC_PCOR GPIO_PCOR(GPIOC_BASE)
+#define GPIOC_PTOR GPIO_PTOR(GPIOC_BASE)
+#define GPIOC_PDIR GPIO_PDIR(GPIOC_BASE)
+#define GPIOC_PDDR GPIO_PDDR(GPIOC_BASE)
+
+#define GPIOD_BASE 0x400FF0C0
+
+#define GPIOD_PDOR GPIO_PDOR(GPIOD_BASE)
+#define GPIOD_PSOR GPIO_PSOR(GPIOD_BASE)
+#define GPIOD_PCOR GPIO_PCOR(GPIOD_BASE)
+#define GPIOD_PTOR GPIO_PTOR(GPIOD_BASE)
+#define GPIOD_PDIR GPIO_PDIR(GPIOD_BASE)
+#define GPIOD_PDDR GPIO_PDDR(GPIOD_BASE)
+
+#define GPIOE_BASE 0x400FF100
+
+#define GPIOE_PDOR GPIO_PDOR(GPIOE_BASE)
+#define GPIOE_PSOR GPIO_PSOR(GPIOE_BASE)
+#define GPIOE_PCOR GPIO_PCOR(GPIOE_BASE)
+#define GPIOE_PTOR GPIO_PTOR(GPIOE_BASE)
+#define GPIOE_PDIR GPIO_PDIR(GPIOE_BASE)
+#define GPIOE_PDDR GPIO_PDDR(GPIOE_BASE)
 
 #endif /* MK20DX256_REG_GPIO_H */
-- 
cgit v1.2.3-54-g00ecf