From fa2eda4bbf5f25b46dde84acdd1ed977bd2ee25b Mon Sep 17 00:00:00 2001 From: Tomasz Kramkowski Date: Mon, 27 Mar 2017 15:20:36 +0100 Subject: reg/{mcg,pmc,wdog}: Use _M macros. --- reg/mcg.h | 12 ++++++------ reg/pmc.h | 4 ++-- reg/wdog.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/reg/mcg.h b/reg/mcg.h index 4b2ab6c..5972439 100644 --- a/reg/mcg.h +++ b/reg/mcg.h @@ -5,9 +5,9 @@ #define MCG_C1 REG_8(0x40064000) /* MCG Control 1 Register */ #define C1_CLKS 6 /* Clock Source Select */ -#define C1_CLKS_M (uint8_t)(BITS(2) << C1_CLKS) +#define C1_CLKS_M REG_8_M(C1_CLKS, 2) #define C1_FRDIV 3 /* FLL External Reference Divider */ -#define C1_FRDIV_M (uint8_t)(BITS(3) << C1_FRDIV) +#define C1_FRDIV_M REG_8_M(C1_FRDIV, 3) #define C1_IREFS 2 /* Internal Reference Select */ #define C1_IRCLKEN 1 /* Internal Reference Clock Enable */ #define C1_IREFSTEN 0 /* Internal Reference Stop Enable */ @@ -15,7 +15,7 @@ #define MCG_C2 REG_8(0x40064001) /* MCG Control 2 Register */ #define C2_LOCRE0 7 /* Loss of Clock Reset Enable */ #define C2_RANGE0 4 /* Frequency Range Select */ -#define C2_RANGE0_M (uint8_t)(BITS(2) << C2_RANGE0) +#define C2_RANGE0_M REG_8_M(C2_RANGE0, 2) #define C2_HGO0 3 /* High Gain Oscillator Select */ #define C2_EREFS0 2 /* External Reference Select */ #define C2_LP 1 /* Low Power Select */ @@ -28,14 +28,14 @@ #define C5_PLLCLKEN0 6 /* PLL Clock Enable */ #define C5_PLLSTEN0 5 /* PLL Stop Enable */ #define C5_PRDIV0 0 /* PLL External Reference Divider */ -#define C5_PRDIV0_M (uint8_t)(BITS(5) << C5_PRDIV0) +#define C5_PRDIV0_M REG_8_M(C5_PRDIV0, 5) #define MCG_C6 REG_8(0x40064005) /* MCG Control 6 Register */ #define C6_LOLIE0 7 /* Loss of Lock Interrrupt Enable */ #define C6_PLLS 6 /* PLL Select */ #define C6_CME0 5 /* Clock Monitor Enable */ #define C6_VDIV0 0 /* VCO 0 Divider */ -#define C6_VDIV0_M (uint8_t)(BITS(5) << C6_VDIV0) +#define C6_VDIV0_M REG_8_M(C6_VDIV0, 5) #define MCG_S REG_8(0x40064006) /* MCG Status Register */ #define S_LOLS0 7 /* Loss of Lock Status */ @@ -43,7 +43,7 @@ #define S_PLLST 5 /* PLL Select Status */ #define S_IREFST 4 /* Internal Reference Status */ #define S_CLKST 2 /* Clock Mode Status */ -#define S_CLKST_M (uint8_t)(BITS(2) << S_CLKST) +#define S_CLKST_M REG_8_M(S_CLKST, 2) #define S_OSCINIT0 1 /* OSC Initialization */ #define S_IRCST 0 /* Internal Reference Clock Status */ diff --git a/reg/pmc.h b/reg/pmc.h index 3bfa128..cb045ea 100644 --- a/reg/pmc.h +++ b/reg/pmc.h @@ -9,14 +9,14 @@ #define LVDSC1_LVDIE 5 /* Low-Voltage Detect Interrupt Enable */ #define LVDSC1_LVDRE 4 /* Low-Voltage Detect Reset Enable */ #define LVDSC1_LVDV 0 /* Low-Voltage Detect Voltage Select */ -#define LVDSC1_LVDV_M (uint8_t)(BITS(2) << LVDSC1_LVDV) +#define LVDSC1_LVDV_M REG_8_M(LVDSC1_LVDV, 2) #define PMC_LVDSC2 REG_8(0x4007D001) /* Low Voltage Detect Status And Control 2 register */ #define LVDSC2_LVWF 7 /* Low-Voltage Warning Flag */ #define LVDSC2_LVWACK 6 /* Low-Voltage Warning Acknowledge */ #define LVDSC2_LVWIE 5 /* Low-Voltage Warning Interrupt Enable */ #define LVDSC2_LVWV 0 /* Low-Voltage Warning Voltage Select */ -#define LVDSC2_LVWV_M (uint8_t)(BITS(2) << LVDSC2_LVWV) +#define LVDSC2_LVWV_M REG_8_M(LVDSC2_LVWV, 2) #define PMC_REGSC REG_8(0x4007D002) /* Regulator Status And Control register */ #define REGSC_BGEN 4 /* Bandgap Enable In VLPx Operation */ diff --git a/reg/wdog.h b/reg/wdog.h index 8b3b23e..5d9d5eb 100644 --- a/reg/wdog.h +++ b/reg/wdog.h @@ -6,7 +6,7 @@ #define WDOG_STCTRLH REG_16(0x40052000) /* Watchdog Status and Control Register High */ #define STCTRLH_DISTESTWDOG 14 /* Functional test mode disable */ #define STCTRLH_BYTESEL 12 /* Byte test mode byte selector */ -#define STCTRLH_BYTESEL_M (uint16_t)(BITS(2) << STCTRLH_BYTESEL) +#define STCTRLH_BYTESEL_M REG_16_M(STCTRLH_BYTESEL, 2) #define STCTRLH_TESTSEL 11 /* Functional test mode test selector */ #define STCTRLH_TESTWDOG 10 /* Functional test mode enable */ #define STCTRLH_WAITEN 7 /* Wait mode WDOG enable */ -- cgit v1.2.3-54-g00ecf