From 7d7f3daeba7f07808e3e01d5f8d9fb649509d66a Mon Sep 17 00:00:00 2001
From: Tomasz Kramkowski <tk@the-tk.com>
Date: Fri, 19 May 2017 21:30:00 +0100
Subject: complete some headers

---
 reg/mcg.h  | 44 ++++++++++++++++++++++++++++++++++++++++++++
 reg/pmc.h  |  1 +
 reg/port.h |  1 +
 3 files changed, 46 insertions(+)

diff --git a/reg/mcg.h b/reg/mcg.h
index 1acae9e..706e981 100644
--- a/reg/mcg.h
+++ b/reg/mcg.h
@@ -1,3 +1,4 @@
+/* Multipurpose Clock Generator (MCG) (Chapter 24) */
 #ifndef MK20DX256_REG_MCG_H
 #define MK20DX256_REG_MCG_H
 
@@ -29,8 +30,21 @@ enum {
 
 // MCG Control 3 Register
 #define MCG_C3 REG_8(0x40064002)
+enum {
+	C3_SCTRIM = 0, // Slow Internal Reference Clock Trim Setting
+	C3_SCTRIM_M = REG_8_M(C3_SCTRIM, 8),
+};
+
 // MCG Control 4 Register
 #define MCG_C4 REG_8(0x40064003)
+enum {
+	C4_DMX32 = 7, // DCO Maximum Frequency with 32.768 kHz Reference
+	C4_DRST_DRS = 5, // DCO Range Select
+	C4_DRST_DRS_M = REG_8_M(C4_DRST_DRS, 2),
+	C4_FCTRIM = 1, // Fast Internal Reference Clock Trim Setting
+	C4_FCTRIM_M = REG_8_M(C4_FCTRIM, 4),
+	C4_SCFTRIM = 0, // Slow Internal Reference Clock Fine Trim
+};
 
 // MCG Control 5 Register
 #define MCG_C5 REG_8(0x40064004)
@@ -66,13 +80,43 @@ enum {
 
 // MCG Status and Control Register
 #define MCG_SC REG_8(0x40064008)
+enum {
+	SC_ATME = 7, // Automatic Trim Machine Enable
+	SC_ATMS = 6, // Automatic Trim Machine Select
+	SC_ATMF = 5, // Automatic Trim Machine Fail Flag
+	SC_FLTPRSRV = 4, // FLL Filter Preserve Enable
+	SC_FCRDIV = 1, // Fast Clock Internal Reference Divider
+	SC_FCRDIV_M = REG_8_M(SC_FCRDIV, 3),
+	SC_LOCS0 = 0, // OSC0 Loss of Clock Status
+};
+
 // MCG Auto Trim Compare Value High Register
 #define MCG_ATCVH REG_8(0x4006400A)
+enum {
+	ATCVH_ATCVH = 0, // ATM Compare Value High
+	ATCVH_ATCVH_M = REG_8_M(ATCVH_ATCVH, 8),
+};
+
 // MCG Auto Trim Compare Value Low Register
 #define MCG_ATCVL REG_8(0x4006400B)
+enum {
+	ATCVL_ATCVL = 0, // ATM Compare Value Low
+	ATCVL_ATCVL_M = REG_8_M(ATCVL_ATCVL, 8),
+};
+
 // MCG Control 7 Register
 #define MCG_C7 REG_8(0x4006400C)
+enum {
+	C7_OSCSEL = 0, // MCG OSC Clock Select
+};
+
 // MCG Control 8 Register
 #define MCG_C8 REG_8(0x4006400D)
+enum {
+	C8_LOCRE1 = 7, // Loss of Clock Reset Enable
+	C8_LOLRE = 6, // Loss of Lock Reset Enable
+	C8_CME1 = 5, // Clock Monitor Enable1
+	C8_LOCS1 = 0, // RTC Loss of Clock Status
+};
 
 #endif /* MK20DX256_REG_MCG_H */
diff --git a/reg/pmc.h b/reg/pmc.h
index befbb50..7e8f9c3 100644
--- a/reg/pmc.h
+++ b/reg/pmc.h
@@ -1,3 +1,4 @@
+/* Power Management Controller (Chapter 15) */
 #ifndef MK20DX256_REG_PMC_H
 #define MK20DX256_REG_PMC_H
 
diff --git a/reg/port.h b/reg/port.h
index 704eaaf..23cf77f 100644
--- a/reg/port.h
+++ b/reg/port.h
@@ -1,3 +1,4 @@
+/* Port control and interrupts (PORT) (Chapter 11) */
 #ifndef MK20DX256_REG_PORT_H
 #define MK20DX256_REG_PORT_H
 
-- 
cgit v1.2.3-54-g00ecf