From 7c6c15e2fe40b1d793616d26c148e4e3a08df879 Mon Sep 17 00:00:00 2001 From: Tomasz Kramkowski Date: Sun, 26 Feb 2017 12:17:44 +0000 Subject: reg/sim: Adhere to new style --- reg/sim.h | 167 ++++++++++++++++++++++++++++++++++++++------------------------ 1 file changed, 104 insertions(+), 63 deletions(-) diff --git a/reg/sim.h b/reg/sim.h index 93839e8..59b9107 100644 --- a/reg/sim.h +++ b/reg/sim.h @@ -3,68 +3,109 @@ #include -#define SIM_SOPT REG_32(0x140047000) /* System Options Register 1 */ -#define SIM_SOPT1CFG REG_32(0x40047004) /* SOPT1 Configuration Register */ - -#define SIM_SOPT2 REG_32(0x40048004) /* System Options Register 2 */ -#define SOPT2_USBSRC 18 /* USB clock source select */ -#define SOPT2_PLLFLLSEL 16 /* PLL/FLL clock select */ -#define SOPT2_TRACECLKSEL 12 /* Debug trace clock select */ -#define SOPT2_PTD7PAD 11 /* PTD7 pad drive strength */ -#define SOPT2_CLKOUTSEL 5 /* CLKOUT select */ -#define SOPT2_CLKOUTSEL_M (BITS(3) << SOPT2_CLKOUTSEL) -#define SOPT2_RTCCLKOUTSEL 4 /* RTC clock out select */ - -#define SIM_SOPT4 REG_32(0x4004800C) /* System Options Register 4 */ -#define SIM_SOPT5 REG_32(0x40048010) /* System Options Register 5 */ -#define SIM_SOPT7 REG_32(0x40048018) /* System Options Register 7 */ -#define SIM_SDID REG_32(0x40048024) /* System Device Identification Register */ -#define SIM_SCGC1 REG_32(0x40048028) /* System Clock Gating Control Register 1 */ -#define SIM_SCGC2 REG_32(0x4004802C) /* System Clock Gating Control Register 2 */ -#define SIM_SCGC3 REG_32(0x40048030) /* System Clock Gating Control Register 3 */ - -#define SIM_SCGC4 REG_32(0x40048034) /* System Clock Gating Control Register 4 */ -#define SCGC4_VREF 20 /* VREF Clock Gate Control */ -#define SCGC4_CMP 19 /* Comparator Clock Gate Control */ -#define SCGC4_USBOTG 18 /* USB Clock Gate Control */ -#define SCGC4_UART2 12 /* UART2 Clock Gate Control */ -#define SCGC4_UART1 11 /* UART1 Clock Gate Control */ -#define SCGC4_UART0 10 /* UART0 Clock Gate Control */ -#define SCGC4_I2C1 7 /* I2C1 Clock Gate Control */ -#define SCGC4_I2C0 6 /* I2C0 Clock Gate Control */ -#define SCGC4_CMT 2 /* CMT Clock Gate Control */ -#define SCGC4_EWM 1 /* EWM Clock Gate Control */ - -#define SIM_SCGC5 REG_32(0x40048038) /* System Clock Gating Control Register 5 */ -#define SCGC5_PORTE 13 /* Port E Clock Gate Control */ -#define SCGC5_PORTD 12 /* Port D Clock Gate Control */ -#define SCGC5_PORTC 11 /* Port C Clock Gate Control */ -#define SCGC5_PORTB 10 /* Port B Clock Gate Control */ -#define SCGC5_PORTA 9 /* Port A Clock Gate Control */ -#define SCGC5_TSI 5 /* TSI Clock Gate Control */ -#define SCGC5_LPTIMER 0 /* Low Power Timer Access Control */ - -#define SIM_SCGC6 REG_32(0x4004803C) /* System Clock Gating Control Register 6 */ -#define SIM_SCGC7 REG_32(0x40048040) /* System Clock Gating Control Register 7 */ - -#define SIM_CLKDIV1 REG_32(0x40048044) /* System Clock Divider Register 1 */ -#define CLKDIV1_OUTDIV1 28 /* Clock 1 output divider value */ -#define CLKDIV1_OUTDIV1_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV1) -#define CLKDIV1_OUTDIV2 24 /* Clock 2 output divider value */ -#define CLKDIV1_OUTDIV2_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV2) -#define CLKDIV1_OUTDIV4 16 /* Clock 4 output divider value */ -#define CLKDIV1_OUTDIV4_M (uint32_t)(BITS(4) << CLKDIV1_OUTDIV4) - -#define SIM_CLKDIV2 REG_32(0x40048048) /* System Clock Divider Register 2 */ -#define CLKDIV2_USBDIV 1 /* USB clock divider divisor */ -#define CLKDIV2_USBDIV_M (uint32_t)(BITS(3) << CLKDIV2_USBDIV) -#define CLKDIV2_USBFRAC 0 /* USB clock divider fraction */ - -#define SIM_FCFG1 REG_32(0x4004804C) /* Flash Configuration Register 1 */ -#define SIM_FCFG2 REG_32(0x40048050) /* Flash Configuration Register 2 */ -#define SIM_UIDH REG_32(0x40048054) /* Unique Identification Register High */ -#define SIM_UIDMH REG_32(0x40048058) /* Unique Identification Register Mid-High */ -#define SIM_UIDML REG_32(0x4004805C) /* Unique Identification Register Mid Low */ -#define SIM_UIDL REG_32(0x40048060) /* Unique Identification Register Low */ +// System Options Register 1 +#define SIM_SOPT REG_32(0x140047000) +#define SIM_SOPT1CFG REG_32(0x40047004) // SOPT1 Configuration Register + +// System Options Register 2 +#define SIM_SOPT2 REG_32(0x40048004) +#define SOPT2_USBSRC 18 // USB clock source select +#define SOPT2_PLLFLLSEL 16 // PLL/FLL clock select +#define SOPT2_TRACECLKSEL 12 // Debug trace clock select +#define SOPT2_PTD7PAD 11 // PTD7 pad drive strength +#define SOPT2_CLKOUTSEL 5 // CLKOUT select +#define SOPT2_CLKOUTSEL_M REG_32_M(SOPT2_CLKOUTSEL, 3) +#define SOPT2_RTCCLKOUTSEL 4 // RTC clock out select + +// System Options Register 4 +#define SIM_SOPT4 REG_32(0x4004800C) + +// System Options Register 5 +#define SIM_SOPT5 REG_32(0x40048010) +#define SOPT5_UART1RXSRC 6 // UART 1 receive data source select +#define SOPT5_UART1RXSRC_M REG_32_M(SOPT5_UART1RXSRC, 2) +#define SOPT5_UART1TXSRC 4 // UART 1 transmit data source select +#define SOPT5_UART1TXSRC_M REG_32_M(SOPT5_UART1TXSRC, 2) +#define SOPT5_UART0RXSRC 2 // UART 0 receive data source select +#define SOPT5_UART0RXSRC_M REG_32_M(SOPT5_UART0RXSRC, 2) +#define SOPT5_UART0TXSRC 0 // UART 0 transmit data source select +#define SOPT5_UART0TXSRC_M REG_32_M(SOPT5_UART0TXSRC, 2) + +// System Options Register 7 +#define SIM_SOPT7 REG_32(0x40048018) + +// System Device Identification Register +#define SIM_SDID REG_32(0x40048024) + +// System Clock Gating Control Register 1 +#define SIM_SCGC1 REG_32(0x40048028) + +// System Clock Gating Control Register 2 +#define SIM_SCGC2 REG_32(0x4004802C) + +// System Clock Gating Control Register 3 +#define SIM_SCGC3 REG_32(0x40048030) + +// System Clock Gating Control Register 4 +#define SIM_SCGC4 REG_32(0x40048034) +#define SCGC4_VREF 20 // VREF Clock Gate Control +#define SCGC4_CMP 19 // Comparator Clock Gate Control +#define SCGC4_USBOTG 18 // USB Clock Gate Control +#define SCGC4_UART2 12 // UART2 Clock Gate Control +#define SCGC4_UART1 11 // UART1 Clock Gate Control +#define SCGC4_UART0 10 // UART0 Clock Gate Control +#define SCGC4_I2C1 7 // I2C1 Clock Gate Control +#define SCGC4_I2C0 6 // I2C0 Clock Gate Control +#define SCGC4_CMT 2 // CMT Clock Gate Control +#define SCGC4_EWM 1 // EWM Clock Gate Control + +// System Clock Gating Control Register 5 +#define SIM_SCGC5 REG_32(0x40048038) +#define SCGC5_PORTE 13 // Port E Clock Gate Control +#define SCGC5_PORTD 12 // Port D Clock Gate Control +#define SCGC5_PORTC 11 // Port C Clock Gate Control +#define SCGC5_PORTB 10 // Port B Clock Gate Control +#define SCGC5_PORTA 9 // Port A Clock Gate Control +#define SCGC5_TSI 5 // TSI Clock Gate Control +#define SCGC5_LPTIMER 0 // Low Power Timer Access Control + +// System Clock Gating Control Register 6 +#define SIM_SCGC6 REG_32(0x4004803C) + +// System Clock Gating Control Register 7 +#define SIM_SCGC7 REG_32(0x40048040) + +// System Clock Divider Register 1 +#define SIM_CLKDIV1 REG_32(0x40048044) +#define CLKDIV1_OUTDIV1 28 // Clock 1 output divider value +#define CLKDIV1_OUTDIV1_M REG_32_M(CLKDIV1_OUTDIV1, 4) +#define CLKDIV1_OUTDIV2 24 // Clock 2 output divider value +#define CLKDIV1_OUTDIV2_M REG_32_M(CLKDIV1_OUTDIV2, 4) +#define CLKDIV1_OUTDIV4 16 // Clock 4 output divider value +#define CLKDIV1_OUTDIV4_M REG_32_M(CLKDIV1_OUTDIV4, 4) + +// System Clock Divider Register 2 +#define SIM_CLKDIV2 REG_32(0x40048048) +#define CLKDIV2_USBDIV 1 // USB clock divider divisor +#define CLKDIV2_USBDIV_M REG_32_M(CLKDIV2_USBDIV, 3) +#define CLKDIV2_USBFRAC 0 // USB clock divider fraction + +// Flash Configuration Register 1 +#define SIM_FCFG1 REG_32(0x4004804C) + +// Flash Configuration Register 2 +#define SIM_FCFG2 REG_32(0x40048050) + +// Unique Identification Register High +#define SIM_UIDH REG_32(0x40048054) + +// Unique Identification Register Mid-High +#define SIM_UIDMH REG_32(0x40048058) + +// Unique Identification Register Mid Low +#define SIM_UIDML REG_32(0x4004805C) + +// Unique Identification Register Low +#define SIM_UIDL REG_32(0x40048060) #endif /* LIB_REG_SIM_H */ -- cgit v1.2.3-54-g00ecf