From 40f8bed253568a2ab609c12f3a4aae5ad322f414 Mon Sep 17 00:00:00 2001
From: Tomasz Kramkowski <tk@the-tk.com>
Date: Wed, 24 May 2017 13:51:12 +0100
Subject: I2C register definitions

---
 reg/i2c.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 145 insertions(+)
 create mode 100644 reg/i2c.h

diff --git a/reg/i2c.h b/reg/i2c.h
new file mode 100644
index 0000000..bd4883f
--- /dev/null
+++ b/reg/i2c.h
@@ -0,0 +1,145 @@
+#ifndef MK20DX256_REG_I2C_H
+#define MK20DX256_REG_I2C_H
+
+#include "regdefs.h"
+
+// I2C Address Register 1
+#define I2C_A1(base) REG_8((base) + 0x0)
+enum {
+	A1_AD = 1, // Address
+	A1_AD_M = REG_8_M(A1_AD, 7),
+};
+
+// I2C Frequency Divider register
+#define I2C_F(base) REG_8((base) + 0x1)
+enum {
+	F_MULT = 6,
+	F_MULT_M = REG_8_M(F_MULT, 2),
+	F_ICR = 0, // ClockRate
+	F_ICR_M = REG_8_M(F_ICR, 6),
+};
+
+// I2C Control Register 1
+#define I2C_C1(base) REG_8((base) + 0x2)
+enum {
+	C1_IICEN = 7, // I2C Enable
+	C1_IICIE = 6, // I2C Interrupt Enable
+	C1_MST = 5, // Master Mode Select
+	C1_TX = 4, // Transmit Mode Select
+	C1_TXAK = 3, // Transmit Acknowledge Enable
+	C1_RSTA = 2, // Repeat START
+	C1_WUEN = 1, // Wakeup Enable
+	C1_DMAEN = 0, // DMA Enable
+};
+
+// I2C Status register
+#define I2C_S(base) REG_8((base) + 0x3)
+enum {
+	S_TCF = 7, // Transfer Complete Flag
+	S_IAAS = 6, // Addressed As A Slave
+	S_BUSY = 5, // Bus Busy
+	S_ARBL = 4, // Arbitration Lost
+	S_RAM = 3, // Range Address Match
+	S_SRW = 2, // Slave Read/Write
+	S_IICIF = 1, // Interrupt Flag
+	S_RXAK = 0, // Receive Acknowledge
+};
+
+// I2C Data I/O register
+#define I2C_D(base) REG_8((base) + 0x4)
+enum {
+	D_DATA = 0, // Data
+	D_DATA_M = REG_8_M(D_DATA, 8),
+};
+
+// I2C Control Register 2
+#define I2C_C2(base) REG_8((base) + 0x5)
+enum {
+	C2_GCAEN = 7, // General Call Address Enable
+	C2_ADEXT = 6, // Address Extension
+	C2_HDRS = 5, // High Drive Select
+	C2_SBRC = 4, // Slave Baud Rate Control
+	C2_RMEN = 3, // Range Address Matching Enable
+	C2_AD = 0, // Slave Address
+	C2_AD_M = REG_8_M(C2_AD, 3),
+};
+
+// I2C Programmable Input Glitch Filter register
+#define I2C_FLT(base) REG_8((base) + 0x6)
+enum {
+	FLT_FLT = 0, // I2C Programmable Filter Factor
+	FLT_FLT_M = REG_8_M(FLT_FLT, 5),
+};
+
+// I2C Range Address register
+#define I2C_RA(base) REG_8((base) + 0x7)
+enum {
+	RA_RAD = 1, // Range Slave Address
+	RA_RAD_M = REG_8_M(RA_RAD, 7),
+};
+
+// I2C SMBus Control and Status register
+#define I2C_SMB(base) REG_8((base) + 0x8)
+enum {
+	SMB_FACK = 7, // Fast NACK/ACK Enable
+	SMB_ALERTEN = 6, // SMBus Alert Response Address Enable
+	SMB_SIICAEN = 5, // Second I2C Address Enable
+	SMB_TCKSEL = 4, // Timeout Counter Clock Select
+	SMB_SLTF = 3, // SCL Low Timeout Flag
+	SMB_SHTF1 = 2, // SCL High Timeout Flag 1
+	SMB_SHTF2 = 1, // SCL High Timeout Flag 2
+	SMB_SHTF2IE = 0, // SHTF2 Interrupt Enable
+};
+
+// I2C Address Register 2
+#define I2C_A2(base) REG_8((base) + 0x9)
+enum {
+	A2_SAD = 1, // SMBus Address
+	A2_SAD_M = REG_8_M(A2_SAD, 7),
+};
+
+// I2C SCL Low Timeout Register High
+#define I2C_SLTH(base) REG_8((base) + 0xA)
+enum {
+	SLTH_SSLT = 0,
+	SLTH_SSLT_M = REG_8_M(SLTH_SSLT, 8),
+};
+
+// I2C SCL Low Timeout Register Low
+#define I2C_SLTL(base) REG_8((base) + 0xB)
+enum {
+	SLTL_SSLT = 0,
+	SLTL_SSLT_M = REG_8_M(SLTL_SSLT, 8),
+};
+
+#define I2C0_BASE 0x40066000
+
+#define I2C0_A1 I2C_A1(I2C0_BASE)
+#define I2C0_F I2C_F(I2C0_BASE)
+#define I2C0_C1 I2C_C1(I2C0_BASE)
+#define I2C0_S I2C_S(I2C0_BASE)
+#define I2C0_D I2C_D(I2C0_BASE)
+#define I2C0_C2 I2C_C2(I2C0_BASE)
+#define I2C0_FLT I2C_FLT(I2C0_BASE)
+#define I2C0_RA I2C_RA(I2C0_BASE)
+#define I2C0_SMB I2C_SMB(I2C0_BASE)
+#define I2C0_A2 I2C_A2(I2C0_BASE)
+#define I2C0_SLTH I2C_SLTH(I2C0_BASE)
+#define I2C0_SLTL I2C_SLTL(I2C0_BASE)
+
+#define I2C1_BASE 0x40067000
+
+#define I2C1_A1 I2C_A1(I2C1_BASE)
+#define I2C1_F I2C_F(I2C1_BASE)
+#define I2C1_C1 I2C_C1(I2C1_BASE)
+#define I2C1_S I2C_S(I2C1_BASE)
+#define I2C1_D I2C_D(I2C1_BASE)
+#define I2C1_C2 I2C_C2(I2C1_BASE)
+#define I2C1_FLT I2C_FLT(I2C1_BASE)
+#define I2C1_RA I2C_RA(I2C1_BASE)
+#define I2C1_SMB I2C_SMB(I2C1_BASE)
+#define I2C1_A2 I2C_A2(I2C1_BASE)
+#define I2C1_SLTH I2C_SLTH(I2C1_BASE)
+#define I2C1_SLTL I2C_SLTL(I2C1_BASE)
+
+#endif /* MK20DX256_REG_I2C_H */
-- 
cgit v1.2.3-54-g00ecf