From a42f615881a31c487067153aa7ce385146a5807c Mon Sep 17 00:00:00 2001 From: bigtreetech Date: Wed, 23 Nov 2022 11:29:44 +0800 Subject: stm32: add STM32H723 support Signed-off-by: Chen.BJ from BigTreeTech chenbj@biqu3d.com Signed-off-by: Kevin O'Connor --- src/stm32/stm32h7.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/stm32/stm32h7.c') diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index d24d07b7..3423e7eb 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -83,10 +83,11 @@ DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); static void clock_setup(void) { +#if !CONFIG_MACH_STM32H723 // Ensure USB OTG ULPI is not enabled CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN); CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN); - +#endif // Set this despite correct defaults. // "The software has to program the supply configuration in PWR control // register 3" (pg. 259) @@ -143,7 +144,11 @@ clock_setup(void) // Enable VOS0 (overdrive) if (CONFIG_CLOCK_FREQ > 400000000) { RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; +#if !CONFIG_MACH_STM32H723 SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN; +#else + PWR->CR3 |= PWR_CR3_BYPASS; +#endif while (!(PWR->D3CR & PWR_D3CR_VOSRDY)) ; } -- cgit v1.2.3-70-g09d2