From 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 31 May 2025 17:00:18 -0400 Subject: stm32: Add comments on PLL frequency requirements to clock setup code Signed-off-by: Kevin O'Connor --- src/stm32/stm32h7.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/stm32/stm32h7.c') diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index f65eeed7..c6da0eac 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -82,6 +82,9 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB4ENR; } +// PLL1 (h723) input: 2 to 16Mhz, vco: 192 to 836Mhz, output: 1.5 to 550Mhz +// PLL1 (h743v) input: 2 to 16Mhz, vco: 192 to 960Mhz, output: 1.5 to 480Mhz + #if !CONFIG_STM32_CLOCK_REF_INTERNAL DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); #endif -- cgit v1.2.3-70-g09d2