From 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 31 May 2025 17:00:18 -0400 Subject: stm32: Add comments on PLL frequency requirements to clock setup code Signed-off-by: Kevin O'Connor --- src/stm32/stm32g4.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/stm32/stm32g4.c') diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index 02c9656f..3301071e 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -76,6 +76,8 @@ gpio_clock_enable(GPIO_TypeDef *regs) RCC->AHB2ENR; } +// PLL (g4) input: 2.66 to 16Mhz, vco: 96 to 344Mhz, output: 2.06 to 170Mhz + #if !CONFIG_STM32_CLOCK_REF_INTERNAL DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1"); #endif -- cgit v1.2.3-70-g09d2