From 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 Mon Sep 17 00:00:00 2001
From: Kevin O'Connor <kevin@koconnor.net>
Date: Sat, 31 May 2025 17:00:18 -0400
Subject: stm32: Add comments on PLL frequency requirements to clock setup code

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
---
 src/stm32/stm32f7.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/stm32/stm32f7.c')

diff --git a/src/stm32/stm32f7.c b/src/stm32/stm32f7.c
index f6f27618..c86bca3d 100644
--- a/src/stm32/stm32f7.c
+++ b/src/stm32/stm32f7.c
@@ -57,6 +57,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHB1ENR;
 }
 
+// PLL (f765) input: 0.95 to 2.1Mhz, vco: 100 to 432Mhz, output: 24 to 216Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
 #endif
-- 
cgit v1.2.3-70-g09d2