From e3905eb2419b4d7bc8200a87e1dcac5c6eba9064 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Wed, 6 Oct 2021 19:48:03 -0400 Subject: stm32: Add an MACH_STM32F4x5 alias for F405, F407, and F429 chips The F405, F407, and F429 chips are in the same series and almost all code definitions should apply to all chips in that series. Implement the alias and fix defintions in adc.c and Kconfig that were only applying to a subset of that series. Signed-off-by: Kevin O'Connor --- src/stm32/stm32f4.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/stm32/stm32f4.c') diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c index 4bab40bc..06312832 100644 --- a/src/stm32/stm32f4.c +++ b/src/stm32/stm32f4.c @@ -144,8 +144,7 @@ enable_clock_stm32f20x(void) static void enable_clock_stm32f40x(void) { -#if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 \ - || CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F429 +#if CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F4x5 uint32_t pll_base = (CONFIG_STM32_CLOCK_REF_25M) ? 1000000 : 2000000; uint32_t pllp = (CONFIG_MACH_STM32F401) ? 4 : 2; uint32_t pll_freq = CONFIG_CLOCK_FREQ * pllp, pllcfgr; @@ -222,8 +221,7 @@ clock_setup(void) // Configure and enable PLL if (CONFIG_MACH_STM32F207) enable_clock_stm32f20x(); - else if (CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 - || CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F429) + else if (CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F4x5) enable_clock_stm32f40x(); else enable_clock_stm32f446(); -- cgit v1.2.3-70-g09d2