From a6d90bb95e5fdf56993796660ee559ab5666ad0d Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Mon, 16 Sep 2019 21:39:29 -0400 Subject: stm32: Support stm32f042 build from stm32/ directory Signed-off-by: Kevin O'Connor --- src/stm32/stm32f0.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'src/stm32/stm32f0.c') diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index 199fb066..d3c1afb4 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -124,6 +124,29 @@ pll_setup(void) RCC->CFGR3 = RCC_CFGR3_USBSW; } +// Configure and enable internal 48Mhz clock on the stm32f042 +static void +hsi48_setup(void) +{ +#if CONFIG_MACH_STM32F042 + // Enable HSI48 + RCC->CR2 |= RCC_CR2_HSI48ON; + while (!(RCC->CR2 & RCC_CR2_HSI48RDY)) + ; + + // Switch system clock to HSI48 + RCC->CFGR = RCC_CFGR_SW_HSI48; + while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_HSI48) + ; + + // Enable USB clock recovery + if (CONFIG_USBSERIAL) { + enable_pclock(CRS_BASE); + CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + } +#endif +} + // Main clock setup called at chip startup void clock_setup(void) @@ -132,5 +155,8 @@ clock_setup(void) FLASH->ACR = (1 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE; // Configure main clock - pll_setup(); + if (CONFIG_MACH_STM32F042 && CONFIG_STM32_CLOCK_REF_INTERNAL) + hsi48_setup(); + else + pll_setup(); } -- cgit v1.2.3-70-g09d2