From 28bca7da7741bafbbe8619da2c46892b38696191 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Mon, 18 Jan 2021 12:47:59 -0500 Subject: stm32: Support setting the stm32f0 internal clock trim value Signed-off-by: Kevin O'Connor --- src/stm32/stm32f0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/stm32/stm32f0.c') diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c index 3b4d35d4..0232b602 100644 --- a/src/stm32/stm32f0.c +++ b/src/stm32/stm32f0.c @@ -127,7 +127,8 @@ pll_setup(void) if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { // Configure 48Mhz PLL from external crystal (HSE) uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ; - RCC->CR |= RCC_CR_HSEON; + RCC->CR = ((RCC->CR & ~RCC_CR_HSITRIM) | RCC_CR_HSEON + | (CONFIG_STM32F0_TRIM << RCC_CR_HSITRIM_Pos)); cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((div - 2) << RCC_CFGR_PLLMUL_Pos); } else { // Configure 48Mhz PLL from internal 8Mhz oscillator (HSI) -- cgit v1.2.3-70-g09d2