From 105ce35e1ba813b7ebe1be2a87fd852a5f7b66f5 Mon Sep 17 00:00:00 2001
From: Kevin O'Connor <kevin@koconnor.net>
Date: Sat, 31 May 2025 17:00:18 -0400
Subject: stm32: Add comments on PLL frequency requirements to clock setup code

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
---
 src/stm32/stm32f0.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/stm32/stm32f0.c')

diff --git a/src/stm32/stm32f0.c b/src/stm32/stm32f0.c
index d7af831e..b0691c64 100644
--- a/src/stm32/stm32f0.c
+++ b/src/stm32/stm32f0.c
@@ -52,6 +52,8 @@ gpio_clock_enable(GPIO_TypeDef *regs)
     RCC->AHBENR;
 }
 
+// PLL (f0) input: 1 to 24Mhz, output: 16 to 48Mhz
+
 #if !CONFIG_STM32_CLOCK_REF_INTERNAL
 DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
 #endif
-- 
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