From 8b6753d68f681b0ed7e76b5e05b2bc7da6d5aa1d Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Fri, 24 Dec 2021 12:23:56 -0500 Subject: stm32: Unify enable_pclock() code Unify the handling of the enable_pclock() and is_enabled_pclock() code across all stm32 chips. All chips will now perform a peripheral reset on enable_pclock() (this is a change for stm32f0 and stm32h7). The enable_pclock() code will now also disable irqs during the enable. Signed-off-by: Kevin O'Connor --- src/stm32/internal.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/stm32/internal.h') diff --git a/src/stm32/internal.h b/src/stm32/internal.h index 6101e0f2..f0535ab9 100644 --- a/src/stm32/internal.h +++ b/src/stm32/internal.h @@ -18,22 +18,28 @@ #include "stm32h7xx.h" #endif +// gpio.c extern GPIO_TypeDef * const digital_regs[]; - #define GPIO(PORT, NUM) (((PORT)-'A') * 16 + (NUM)) #define GPIO2PORT(PIN) ((PIN) / 16) #define GPIO2BIT(PIN) (1<<((PIN) % 16)) +// gpioperiph.c #define GPIO_INPUT 0 #define GPIO_OUTPUT 1 #define GPIO_OPEN_DRAIN 0x100 #define GPIO_FUNCTION(fn) (2 | ((fn) << 4)) #define GPIO_ANALOG 3 +void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup); +// clockline.c void enable_pclock(uint32_t periph_base); int is_enabled_pclock(uint32_t periph_base); + +// stm32??.c +struct cline { volatile uint32_t *en, *rst; uint32_t bit; }; +struct cline lookup_clock_line(uint32_t periph_base); uint32_t get_pclock_frequency(uint32_t periph_base); void gpio_clock_enable(GPIO_TypeDef *regs); -void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup); #endif // internal.h -- cgit v1.2.3-70-g09d2