From 399d53996994f9f716979b489064989bc49079bf Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 2 Mar 2019 12:01:44 -0500 Subject: Makefile: Reduce use of $^ in build rules It's rare to use all of a target's prerequisites in a recipe - replace most cases with $< (the target's first prerequisite). Signed-off-by: Kevin O'Connor --- src/pru/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/pru') diff --git a/src/pru/Makefile b/src/pru/Makefile index 38f262ec..5fea9e17 100644 --- a/src/pru/Makefile +++ b/src/pru/Makefile @@ -31,7 +31,7 @@ $(OUT)pru0.elf: $(patsubst %.c, $(OUT)src/%.o,$(pru0-y)) $(OUT)pru1.elf: $(OUT)klipper.elf @echo " Linking $@" - $(Q)$(CC) $(CFLAGS_pru1.elf) $^ -o $@ + $(Q)$(CC) $(CFLAGS_pru1.elf) $< -o $@ flash: $(OUT)pru0.elf $(OUT)pru1.elf @echo " Flashing" -- cgit v1.2.3-70-g09d2